IxEthMii_p.h 6.0 KB

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  1. /**
  2. * @file IxEthMii_p.h
  3. *
  4. * @author Intel Corporation
  5. * @date
  6. *
  7. * @brief MII Header file
  8. *
  9. * Design Notes:
  10. *
  11. *
  12. * @par
  13. * IXP400 SW Release version 2.0
  14. *
  15. * -- Copyright Notice --
  16. *
  17. * @par
  18. * Copyright 2001-2005, Intel Corporation.
  19. * All rights reserved.
  20. *
  21. * @par
  22. * SPDX-License-Identifier: BSD-3-Clause
  23. * @par
  24. * -- End of Copyright Notice --
  25. */
  26. #ifndef IxEthMii_p_H
  27. #define IxEthMii_p_H
  28. /* MII definitions - these have been verified against the LXT971 and
  29. LXT972 PHYs*/
  30. #define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */
  31. #define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */
  32. #define IX_ETH_MII_STAT_REG 0x1 /* Status Register */
  33. #define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
  34. #define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
  35. #define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
  36. /* Advertisement Register */
  37. #define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
  38. /* partner ability Register */
  39. #define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
  40. /* Expansion Register */
  41. #define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
  42. /* next-page transmit Register */
  43. #define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/
  44. /* MII control register bit */
  45. #define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */
  46. #define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
  47. #define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */
  48. #define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
  49. #define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */
  50. #define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
  51. #define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
  52. #define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
  53. #define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
  54. #define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */
  55. #define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */
  56. #define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */
  57. /* MII Status register bit definitions */
  58. #define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
  59. #define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
  60. #define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
  61. #define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
  62. #define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
  63. #define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
  64. #define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
  65. #define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
  66. #define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */
  67. #define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */
  68. #define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */
  69. /* LXT971/2 Status 2 register bit definitions */
  70. #define IX_ETH_MII_SR2_100 0x4000
  71. #define IX_ETH_MII_SR2_TX 0x2000
  72. #define IX_ETH_MII_SR2_RX 0x1000
  73. #define IX_ETH_MII_SR2_COL 0x0800
  74. #define IX_ETH_MII_SR2_LINK 0x0400
  75. #define IX_ETH_MII_SR2_FD 0x0200
  76. #define IX_ETH_MII_SR2_AUTO 0x0100
  77. #define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080
  78. #define IX_ETH_MII_SR2_POLARITY 0x0020
  79. #define IX_ETH_MII_SR2_PAUSE 0x0010
  80. #define IX_ETH_MII_SR2_ERROR 0x0008
  81. /* MII Link Code word bit definitions */
  82. #define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */
  83. #define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */
  84. #define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */
  85. /* MII Next Page bit definitions */
  86. #define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */
  87. #define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */
  88. #define IX_ETH_MII_NP_MSG 0x2000 /* message page */
  89. #define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */
  90. #define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */
  91. /* MII Expansion Register bit definitions */
  92. #define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */
  93. #define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
  94. #define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
  95. #define IX_ETH_MII_EXP_PR 0x0002 /* full page received */
  96. #define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */
  97. /* technology ability field bit definitions */
  98. #define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */
  99. #define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
  100. #define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
  101. #define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
  102. #define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
  103. #define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */
  104. #define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK
  105. #define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */
  106. #define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */
  107. #define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */
  108. #define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
  109. /* Definitions for MII access routines*/
  110. #define IX_ETH_MII_GO BIT(31)
  111. #define IX_ETH_MII_WRITE BIT(26)
  112. #define IX_ETH_MII_TIMEOUT_10TH_SECS (5)
  113. #define IX_ETH_MII_10TH_SEC_IN_MILLIS (100)
  114. #define IX_ETH_MII_READ_FAIL BIT(31)
  115. /* When we reset the PHY we delay for 2 seconds to allow the reset to
  116. complete*/
  117. #define IX_ETH_MII_RESET_DELAY_MS (2000)
  118. #define IX_ETH_MII_RESET_POLL_MS (50)
  119. #define IX_ETH_MII_REG_SHL 16
  120. #define IX_ETH_MII_ADDR_SHL 21
  121. /* supported PHYs */
  122. #define IX_ETH_MII_LXT971_PHY_ID 0x001378E0
  123. #define IX_ETH_MII_LXT972_PHY_ID 0x001378E2
  124. #define IX_ETH_MII_LXT973_PHY_ID 0x00137A10
  125. #define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11
  126. #define IX_ETH_MII_KS8995_PHY_ID 0x00221450
  127. #define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF
  128. #define IX_ETH_MII_INVALID_PHY_ID 0x00000000
  129. #define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff
  130. #endif /*IxEthAccMii_p_H*/