IxEthAcc_p.h 9.5 KB

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  1. /**
  2. * @file IxEthAcc_p.h
  3. *
  4. * @author Intel Corporation
  5. * @date 12-Feb-2002
  6. *
  7. * @brief Internal Header file for IXP425 Ethernet Access component.
  8. *
  9. * Design Notes:
  10. *
  11. *
  12. * @par
  13. * IXP400 SW Release version 2.0
  14. *
  15. * -- Copyright Notice --
  16. *
  17. * @par
  18. * Copyright 2001-2005, Intel Corporation.
  19. * All rights reserved.
  20. *
  21. * @par
  22. * SPDX-License-Identifier: BSD-3-Clause
  23. * @par
  24. * -- End of Copyright Notice --
  25. */
  26. /**
  27. * @addtogroup IxEthAccPri
  28. *@{
  29. */
  30. #ifndef IxEthAcc_p_H
  31. #define IxEthAcc_p_H
  32. /*
  33. * Os/System dependancies.
  34. */
  35. #include "IxOsal.h"
  36. /*
  37. * Intermodule dependancies
  38. */
  39. #include "IxNpeDl.h"
  40. #include "IxQMgr.h"
  41. #include "IxEthNpe.h"
  42. /*
  43. * Intra module dependancies
  44. */
  45. #include "IxEthAccDataPlane_p.h"
  46. #include "IxEthAccMac_p.h"
  47. #define INLINE __inline__
  48. #ifdef NDEBUG
  49. #define IX_ETH_ACC_PRIVATE static
  50. #else
  51. #define IX_ETH_ACC_PRIVATE
  52. #endif /* ndef NDEBUG */
  53. #define IX_ETH_ACC_PUBLIC
  54. #define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false )
  55. #ifndef NDEBUG
  56. #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  57. #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  58. #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  59. #else
  60. #define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  61. #define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);}
  62. #define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {}
  63. #endif
  64. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void);
  65. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void);
  66. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback);
  67. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId);
  68. IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries);
  69. /* prototypes for the private control plane functions (used by the control interface wrapper) */
  70. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId);
  71. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId);
  72. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled);
  73. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId);
  74. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId);
  75. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  76. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  77. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  78. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId);
  79. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr);
  80. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId);
  81. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId);
  82. IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId);
  83. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode);
  84. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode);
  85. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId);
  86. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId);
  87. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
  88. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
  89. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId);
  90. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId);
  91. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched);
  92. IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched);
  93. /**
  94. * @struct ixEthAccRxDataStats
  95. * @brief Stats data structures for data path. - Not obtained from h/w
  96. *
  97. */
  98. typedef struct
  99. {
  100. UINT32 rxFrameClientCallback;
  101. UINT32 rxFreeRepOK;
  102. UINT32 rxFreeRepDelayed;
  103. UINT32 rxFreeRepFromSwQOK;
  104. UINT32 rxFreeRepFromSwQDelayed;
  105. UINT32 rxFreeLateNotificationEnabled;
  106. UINT32 rxFreeLowCallback;
  107. UINT32 rxFreeOverflow;
  108. UINT32 rxFreeLock;
  109. UINT32 rxDuringDisable;
  110. UINT32 rxSwQDuringDisable;
  111. UINT32 rxUnlearnedMacAddress;
  112. UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
  113. UINT32 rxUnexpectedError;
  114. UINT32 rxFiltered;
  115. } IxEthAccRxDataStats;
  116. /**
  117. * @struct IxEthAccTxDataStats
  118. * @brief Stats data structures for data path. - Not obtained from h/w
  119. *
  120. */
  121. typedef struct
  122. {
  123. UINT32 txQOK;
  124. UINT32 txQDelayed;
  125. UINT32 txFromSwQOK;
  126. UINT32 txFromSwQDelayed;
  127. UINT32 txLowThreshCallback;
  128. UINT32 txDoneClientCallback;
  129. UINT32 txDoneClientCallbackDisable;
  130. UINT32 txOverflow;
  131. UINT32 txLock;
  132. UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1];
  133. UINT32 txLateNotificationEnabled;
  134. UINT32 txDoneDuringDisable;
  135. UINT32 txDoneSwQDuringDisable;
  136. UINT32 txUnexpectedError;
  137. } IxEthAccTxDataStats;
  138. /* port Disable state machine : list of states */
  139. typedef enum
  140. {
  141. /* general port states */
  142. DISABLED = 0,
  143. ACTIVE,
  144. /* particular Tx/Rx states */
  145. REPLENISH,
  146. RECEIVE,
  147. TRANSMIT,
  148. TRANSMIT_DONE
  149. } IxEthAccPortDisableState;
  150. typedef struct
  151. {
  152. BOOL fullDuplex;
  153. BOOL rxFCSAppend;
  154. BOOL txFCSAppend;
  155. BOOL txPADAppend;
  156. BOOL enabled;
  157. BOOL promiscuous;
  158. BOOL joinAll;
  159. IxOsalMutex ackMIBStatsLock;
  160. IxOsalMutex ackMIBStatsResetLock;
  161. IxOsalMutex MIBStatsGetAccessLock;
  162. IxOsalMutex MIBStatsGetResetAccessLock;
  163. IxOsalMutex npeLoopbackMessageLock;
  164. IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES];
  165. UINT32 mcastAddrIndex;
  166. IX_OSAL_MBUF *portDisableTxMbufPtr;
  167. IX_OSAL_MBUF *portDisableRxMbufPtr;
  168. volatile IxEthAccPortDisableState portDisableState;
  169. volatile IxEthAccPortDisableState rxState;
  170. volatile IxEthAccPortDisableState txState;
  171. BOOL initDone;
  172. BOOL macInitialised;
  173. } IxEthAccMacState;
  174. /**
  175. * @struct IxEthAccRxInfo
  176. * @brief System-wide data structures associated with the data plane.
  177. *
  178. */
  179. typedef struct
  180. {
  181. IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */
  182. IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */
  183. } IxEthAccInfo;
  184. /**
  185. * @struct IxEthAccRxDataInfo
  186. * @brief Per Port data structures associated with the receive data plane.
  187. *
  188. */
  189. typedef struct
  190. {
  191. IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */
  192. IxEthAccPortRxCallback rxCallbackFn;
  193. UINT32 rxCallbackTag;
  194. IxEthAccDataPlaneQList freeBufferList;
  195. IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn;
  196. UINT32 rxMultiBufferCallbackTag;
  197. BOOL rxMultiBufferCallbackInUse;
  198. IxEthAccRxDataStats stats; /**< Receive s/w stats */
  199. } IxEthAccRxDataInfo;
  200. /**
  201. * @struct IxEthAccTxDataInfo
  202. * @brief Per Port data structures associated with the transmit data plane.
  203. *
  204. */
  205. typedef struct
  206. {
  207. IxEthAccPortTxDoneCallback txBufferDoneCallbackFn;
  208. UINT32 txCallbackTag;
  209. IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
  210. IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
  211. IxQMgrQId txQueue; /**< txQueue for this port */
  212. IxEthAccTxDataStats stats; /**< Transmit s/w stats */
  213. } IxEthAccTxDataInfo;
  214. /**
  215. * @struct IxEthAccPortDataInfo
  216. * @brief Per Port data structures associated with the port data plane.
  217. *
  218. */
  219. typedef struct
  220. {
  221. BOOL portInitialized;
  222. UINT32 npeId; /**< NpeId for this port */
  223. IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
  224. IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
  225. } IxEthAccPortDataInfo;
  226. extern IxEthAccPortDataInfo ixEthAccPortData[];
  227. #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized)
  228. extern BOOL ixEthAccServiceInit;
  229. #define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true )
  230. /*
  231. * Maximum number of frames to consume from the Rx Frame Q.
  232. */
  233. #define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128)
  234. /*
  235. * Max number of times to load the Rx Free Q from callback.
  236. */
  237. #define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */
  238. /*
  239. * Max number of times to read from the Tx Done Q in one sitting.
  240. */
  241. #define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256)
  242. /*
  243. * Max number of times to take buffers from S/w queues and write them to the H/w Tx
  244. * queues on receipt of a Tx low threshold callback
  245. */
  246. #define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16)
  247. #define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size))
  248. #define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size))
  249. #define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size)
  250. #endif /* ndef IxEthAcc_p_H */