IxEthAccMac_p.h 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224
  1. /*
  2. *
  3. * @par
  4. * IXP400 SW Release version 2.0
  5. *
  6. * -- Copyright Notice --
  7. *
  8. * @par
  9. * Copyright 2001-2005, Intel Corporation.
  10. * All rights reserved.
  11. *
  12. * @par
  13. * SPDX-License-Identifier: BSD-3-Clause
  14. * @par
  15. * -- End of Copyright Notice --
  16. */
  17. #ifndef IxEthAccMac_p_H
  18. #define IxEthAccMac_p_H
  19. #include "IxOsal.h"
  20. #define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256
  21. #define IX_ETH_ACC_NUM_PORTS 3
  22. #define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536
  23. #define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64)
  24. #define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64
  25. /*
  26. *
  27. * MAC register definitions
  28. *
  29. */
  30. #define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE
  31. #define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE
  32. #define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE
  33. #define IX_ETH_ACC_MAC_TX_CNTRL1 0x000
  34. #define IX_ETH_ACC_MAC_TX_CNTRL2 0x004
  35. #define IX_ETH_ACC_MAC_RX_CNTRL1 0x010
  36. #define IX_ETH_ACC_MAC_RX_CNTRL2 0x014
  37. #define IX_ETH_ACC_MAC_RANDOM_SEED 0x020
  38. #define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030
  39. #define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038
  40. #define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040
  41. #define IX_ETH_ACC_MAC_TX_DEFER 0x050
  42. #define IX_ETH_ACC_MAC_RX_DEFER 0x054
  43. #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060
  44. #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064
  45. #define IX_ETH_ACC_MAC_SLOT_TIME 0x070
  46. #define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080
  47. #define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084
  48. #define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088
  49. #define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c
  50. #define IX_ETH_ACC_MAC_MDIO_STS_1 0x090
  51. #define IX_ETH_ACC_MAC_MDIO_STS_2 0x094
  52. #define IX_ETH_ACC_MAC_MDIO_STS_3 0x098
  53. #define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c
  54. #define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0
  55. #define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4
  56. #define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8
  57. #define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC
  58. #define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0
  59. #define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4
  60. #define IX_ETH_ACC_MAC_ADDR_1 0x0C0
  61. #define IX_ETH_ACC_MAC_ADDR_2 0x0C4
  62. #define IX_ETH_ACC_MAC_ADDR_3 0x0C8
  63. #define IX_ETH_ACC_MAC_ADDR_4 0x0CC
  64. #define IX_ETH_ACC_MAC_ADDR_5 0x0D0
  65. #define IX_ETH_ACC_MAC_ADDR_6 0x0D4
  66. #define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0
  67. #define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0
  68. #define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4
  69. #define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8
  70. #define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC
  71. #define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100
  72. #define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104
  73. #define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC
  74. /*
  75. *
  76. *Bit definitions
  77. *
  78. */
  79. /* TX Control Register 1*/
  80. #define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0)
  81. #define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1)
  82. #define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2)
  83. #define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3)
  84. #define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4)
  85. #define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5)
  86. #define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6)
  87. /* TX Control Register 2 */
  88. #define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf
  89. /* RX Control Register 1 */
  90. #define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0)
  91. #define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1)
  92. #define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2)
  93. #define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3)
  94. #define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4)
  95. #define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5)
  96. #define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6)
  97. #define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7)
  98. /* RX Control Register 2 */
  99. #define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0)
  100. /* Core Control Register */
  101. #define IX_ETH_ACC_CORE_RESET BIT(0)
  102. #define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1)
  103. #define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2)
  104. #define IX_ETH_ACC_CORE_SEND_JAM BIT(3)
  105. #define IX_ETH_ACC_CORE_MDC_EN BIT(4)
  106. /* 1st bit of 1st MAC octet */
  107. #define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1)
  108. /*
  109. *
  110. * Default values
  111. *
  112. */
  113. #define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \
  114. IX_ETH_ACC_TX_CNTRL1_RETRY | \
  115. IX_ETH_ACC_TX_CNTRL1_FCS_EN | \
  116. IX_ETH_ACC_TX_CNTRL1_2DEFER | \
  117. IX_ETH_ACC_TX_CNTRL1_PAD_EN)
  118. #define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f
  119. #define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \
  120. | IX_ETH_ACC_RX_CNTRL1_RX_EN)
  121. #define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0
  122. /* Thresholds determined by NPE firmware FS */
  123. #define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12
  124. #define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30
  125. /* Number of bytes that must be in the tx fifo before
  126. transmission commences*/
  127. #define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8
  128. /* One-part deferral values */
  129. #define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15
  130. #define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16
  131. /* Two-part deferral values... */
  132. #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08
  133. #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07
  134. /* This value applies to MII */
  135. #define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80
  136. /* This value applies to RMII */
  137. #define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
  138. #define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF
  139. #define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1
  140. /*The following is a value chosen at random*/
  141. #define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8
  142. /*By default we must configure the MAC to generate the
  143. MDC clock*/
  144. #define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN)
  145. #define IXP425_ETH_ACC_MAX_PHY 2
  146. #define IXP425_ETH_ACC_MAX_AN_ENTRIES 20
  147. #define IX_ETH_ACC_MAC_RESET_DELAY 1
  148. #define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF
  149. #define IX_ETH_ACC_MAC_MSGID_SHL 24
  150. #define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20
  151. #define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */
  152. #define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3
  153. #define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */
  154. /*Register access macros*/
  155. #if (CPU == SIMSPARCSOLARIS)
  156. extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val);
  157. extern UINT32 registerReadStub (UINT32 base, UINT32 offset);
  158. #define REG_WRITE(b,o,v) registerWriteStub(b, o, v)
  159. #define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0)
  160. #else
  161. #define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v)
  162. #define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o)))
  163. #endif
  164. void ixEthAccMacUnload(void);
  165. IxEthAccStatus ixEthAccMacMemInit(void);
  166. /* MAC core loopback */
  167. IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId);
  168. IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId);
  169. /* MAC core traffic control */
  170. IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId);
  171. IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId);
  172. IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId);
  173. IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId);
  174. IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId);
  175. /* NPE software loopback */
  176. IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId);
  177. IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId);
  178. #endif /*IxEthAccMac_p_H*/