IxEthAccMii.c 8.7 KB

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  1. /**
  2. * @file IxEthAccMii.c
  3. *
  4. * @author Intel Corporation
  5. * @date
  6. *
  7. * @brief MII control functions
  8. *
  9. * Design Notes:
  10. *
  11. * IXP400 SW Release version 2.0
  12. *
  13. * -- Copyright Notice --
  14. *
  15. * @par
  16. * Copyright 2001-2005, Intel Corporation.
  17. * All rights reserved.
  18. *
  19. * @par
  20. * SPDX-License-Identifier: BSD-3-Clause
  21. * @par
  22. * -- End of Copyright Notice --
  23. */
  24. #include "IxOsal.h"
  25. #include "IxEthAcc.h"
  26. #include "IxEthAcc_p.h"
  27. #include "IxEthAccMac_p.h"
  28. #include "IxEthAccMii_p.h"
  29. PRIVATE UINT32 miiBaseAddressVirt;
  30. PRIVATE IxOsalMutex miiAccessLock;
  31. PUBLIC UINT32 ixEthAccMiiRetryCount = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
  32. PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
  33. /* -----------------------------------
  34. * private function prototypes
  35. */
  36. PRIVATE void
  37. ixEthAccMdioCmdWrite(UINT32 mdioCommand);
  38. PRIVATE void
  39. ixEthAccMdioCmdRead(UINT32 *data);
  40. PRIVATE void
  41. ixEthAccMdioStatusRead(UINT32 *data);
  42. PRIVATE void
  43. ixEthAccMdioCmdWrite(UINT32 mdioCommand)
  44. {
  45. REG_WRITE(miiBaseAddressVirt,
  46. IX_ETH_ACC_MAC_MDIO_CMD_1,
  47. mdioCommand & 0xff);
  48. REG_WRITE(miiBaseAddressVirt,
  49. IX_ETH_ACC_MAC_MDIO_CMD_2,
  50. (mdioCommand >> 8) & 0xff);
  51. REG_WRITE(miiBaseAddressVirt,
  52. IX_ETH_ACC_MAC_MDIO_CMD_3,
  53. (mdioCommand >> 16) & 0xff);
  54. REG_WRITE(miiBaseAddressVirt,
  55. IX_ETH_ACC_MAC_MDIO_CMD_4,
  56. (mdioCommand >> 24) & 0xff);
  57. }
  58. PRIVATE void
  59. ixEthAccMdioCmdRead(UINT32 *data)
  60. {
  61. UINT32 regval;
  62. REG_READ(miiBaseAddressVirt,
  63. IX_ETH_ACC_MAC_MDIO_CMD_1,
  64. regval);
  65. *data = regval & 0xff;
  66. REG_READ(miiBaseAddressVirt,
  67. IX_ETH_ACC_MAC_MDIO_CMD_2,
  68. regval);
  69. *data |= (regval & 0xff) << 8;
  70. REG_READ(miiBaseAddressVirt,
  71. IX_ETH_ACC_MAC_MDIO_CMD_3,
  72. regval);
  73. *data |= (regval & 0xff) << 16;
  74. REG_READ(miiBaseAddressVirt,
  75. IX_ETH_ACC_MAC_MDIO_CMD_4,
  76. regval);
  77. *data |= (regval & 0xff) << 24;
  78. }
  79. PRIVATE void
  80. ixEthAccMdioStatusRead(UINT32 *data)
  81. {
  82. UINT32 regval;
  83. REG_READ(miiBaseAddressVirt,
  84. IX_ETH_ACC_MAC_MDIO_STS_1,
  85. regval);
  86. *data = regval & 0xff;
  87. REG_READ(miiBaseAddressVirt,
  88. IX_ETH_ACC_MAC_MDIO_STS_2,
  89. regval);
  90. *data |= (regval & 0xff) << 8;
  91. REG_READ(miiBaseAddressVirt,
  92. IX_ETH_ACC_MAC_MDIO_STS_3,
  93. regval);
  94. *data |= (regval & 0xff) << 16;
  95. REG_READ(miiBaseAddressVirt,
  96. IX_ETH_ACC_MAC_MDIO_STS_4,
  97. regval);
  98. *data |= (regval & 0xff) << 24;
  99. }
  100. /********************************************************************
  101. * ixEthAccMiiInit
  102. */
  103. IxEthAccStatus
  104. ixEthAccMiiInit()
  105. {
  106. if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
  107. {
  108. return IX_ETH_ACC_FAIL;
  109. }
  110. miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
  111. if (miiBaseAddressVirt == 0)
  112. {
  113. ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
  114. IX_OSAL_LOG_DEV_STDOUT,
  115. "EthAcc: Could not map MII I/O mapped memory\n",
  116. 0, 0, 0, 0, 0, 0);
  117. return IX_ETH_ACC_FAIL;
  118. }
  119. return IX_ETH_ACC_SUCCESS;
  120. }
  121. void
  122. ixEthAccMiiUnload(void)
  123. {
  124. IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
  125. miiBaseAddressVirt = 0;
  126. }
  127. PUBLIC IxEthAccStatus
  128. ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
  129. {
  130. if (retryCount < 1) return IX_ETH_ACC_FAIL;
  131. ixEthAccMiiRetryCount = retryCount;
  132. ixEthAccMiiAccessTimeout = timeout;
  133. return IX_ETH_ACC_SUCCESS;
  134. }
  135. /*********************************************************************
  136. * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
  137. */
  138. IxEthAccStatus
  139. ixEthAccMiiReadRtn (UINT8 phyAddr,
  140. UINT8 phyReg,
  141. UINT16 *value)
  142. {
  143. UINT32 mdioCommand;
  144. UINT32 regval;
  145. UINT32 miiTimeout;
  146. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  147. {
  148. return (IX_ETH_ACC_FAIL);
  149. }
  150. if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
  151. || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
  152. {
  153. return (IX_ETH_ACC_FAIL);
  154. }
  155. if (value == NULL)
  156. {
  157. return (IX_ETH_ACC_FAIL);
  158. }
  159. ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
  160. mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
  161. | phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
  162. mdioCommand |= IX_ETH_ACC_MII_GO;
  163. ixEthAccMdioCmdWrite(mdioCommand);
  164. miiTimeout = ixEthAccMiiRetryCount;
  165. while(miiTimeout)
  166. {
  167. ixEthAccMdioCmdRead(&regval);
  168. if((regval & IX_ETH_ACC_MII_GO) == 0x0)
  169. {
  170. break;
  171. }
  172. /* Sleep for a while */
  173. ixOsalSleep(ixEthAccMiiAccessTimeout);
  174. miiTimeout--;
  175. }
  176. if(miiTimeout == 0)
  177. {
  178. ixOsalMutexUnlock(&miiAccessLock);
  179. *value = 0xffff;
  180. return IX_ETH_ACC_FAIL;
  181. }
  182. ixEthAccMdioStatusRead(&regval);
  183. if(regval & IX_ETH_ACC_MII_READ_FAIL)
  184. {
  185. ixOsalMutexUnlock(&miiAccessLock);
  186. *value = 0xffff;
  187. return IX_ETH_ACC_FAIL;
  188. }
  189. *value = regval & 0xffff;
  190. ixOsalMutexUnlock(&miiAccessLock);
  191. return IX_ETH_ACC_SUCCESS;
  192. }
  193. /*********************************************************************
  194. * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
  195. */
  196. IxEthAccStatus
  197. ixEthAccMiiWriteRtn (UINT8 phyAddr,
  198. UINT8 phyReg,
  199. UINT16 value)
  200. {
  201. UINT32 mdioCommand;
  202. UINT32 regval;
  203. UINT16 readVal;
  204. UINT32 miiTimeout;
  205. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  206. {
  207. return (IX_ETH_ACC_FAIL);
  208. }
  209. if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
  210. || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
  211. {
  212. return (IX_ETH_ACC_FAIL);
  213. }
  214. /* ensure that a PHY is present at this address */
  215. if(ixEthAccMiiReadRtn(phyAddr,
  216. IX_ETH_ACC_MII_CTRL_REG,
  217. &readVal) != IX_ETH_ACC_SUCCESS)
  218. {
  219. return (IX_ETH_ACC_FAIL);
  220. }
  221. ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
  222. mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
  223. | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
  224. mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
  225. ixEthAccMdioCmdWrite(mdioCommand);
  226. miiTimeout = ixEthAccMiiRetryCount;
  227. while(miiTimeout)
  228. {
  229. ixEthAccMdioCmdRead(&regval);
  230. /*The "GO" bit is reset to 0 when the write completes*/
  231. if((regval & IX_ETH_ACC_MII_GO) == 0x0)
  232. {
  233. break;
  234. }
  235. /* Sleep for a while */
  236. ixOsalSleep(ixEthAccMiiAccessTimeout);
  237. miiTimeout--;
  238. }
  239. ixOsalMutexUnlock(&miiAccessLock);
  240. if(miiTimeout == 0)
  241. {
  242. return IX_ETH_ACC_FAIL;
  243. }
  244. return IX_ETH_ACC_SUCCESS;
  245. }
  246. /*****************************************************************
  247. *
  248. * Phy query functions
  249. *
  250. */
  251. IxEthAccStatus
  252. ixEthAccMiiStatsShow (UINT32 phyAddr)
  253. {
  254. UINT16 regval;
  255. printf("Regisers on PHY at address 0x%x\n", phyAddr);
  256. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);
  257. printf(" Control Register : 0x%4.4x\n", regval);
  258. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, &regval);
  259. printf(" Status Register : 0x%4.4x\n", regval);
  260. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, &regval);
  261. printf(" PHY ID1 Register : 0x%4.4x\n", regval);
  262. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, &regval);
  263. printf(" PHY ID2 Register : 0x%4.4x\n", regval);
  264. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, &regval);
  265. printf(" Auto Neg ADS Register : 0x%4.4x\n", regval);
  266. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, &regval);
  267. printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval);
  268. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, &regval);
  269. printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval);
  270. ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, &regval);
  271. printf(" Auto Neg Next Register : 0x%4.4x\n", regval);
  272. return IX_ETH_ACC_SUCCESS;
  273. }
  274. /*****************************************************************
  275. *
  276. * Interface query functions
  277. *
  278. */
  279. IxEthAccStatus
  280. ixEthAccMdioShow (void)
  281. {
  282. UINT32 regval;
  283. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  284. {
  285. return (IX_ETH_ACC_FAIL);
  286. }
  287. ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
  288. ixEthAccMdioCmdRead(&regval);
  289. ixOsalMutexUnlock(&miiAccessLock);
  290. printf("MDIO command register\n");
  291. printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31);
  292. printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26);
  293. printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f);
  294. printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f);
  295. ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
  296. ixEthAccMdioStatusRead(&regval);
  297. ixOsalMutexUnlock(&miiAccessLock);
  298. printf("MDIO status register\n");
  299. printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31);
  300. printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff);
  301. return IX_ETH_ACC_SUCCESS;
  302. }