IxEthAccDataPlane.c 67 KB

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  1. /**
  2. * @file IxEthDataPlane.c
  3. *
  4. * @author Intel Corporation
  5. * @date 12-Feb-2002
  6. *
  7. * @brief This file contains the implementation of the IXPxxx
  8. * Ethernet Access Data plane component
  9. *
  10. * Design Notes:
  11. *
  12. * @par
  13. * IXP400 SW Release version 2.0
  14. *
  15. * -- Copyright Notice --
  16. *
  17. * @par
  18. * Copyright 2001-2005, Intel Corporation.
  19. * All rights reserved.
  20. *
  21. * @par
  22. * SPDX-License-Identifier: BSD-3-Clause
  23. * @par
  24. * -- End of Copyright Notice --
  25. */
  26. #include "IxNpeMh.h"
  27. #include "IxEthAcc.h"
  28. #include "IxEthDB.h"
  29. #include "IxOsal.h"
  30. #include "IxEthDBPortDefs.h"
  31. #include "IxFeatureCtrl.h"
  32. #include "IxEthAcc_p.h"
  33. #include "IxEthAccQueueAssign_p.h"
  34. extern PUBLIC IxEthAccMacState ixEthAccMacState[];
  35. extern PUBLIC UINT32 ixEthAccNewSrcMask;
  36. /**
  37. * private functions prototype
  38. */
  39. PRIVATE IX_OSAL_MBUF *
  40. ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
  41. PRIVATE UINT32
  42. ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
  43. PRIVATE UINT32
  44. ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
  45. PRIVATE IxEthAccStatus
  46. ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
  47. IxEthAccTxPriority *priorityPtr);
  48. PRIVATE IxEthAccStatus
  49. ixEthAccTxFromSwQ(IxEthAccPortId portId,
  50. IxEthAccTxPriority priority);
  51. PRIVATE IxEthAccStatus
  52. ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
  53. PRIVATE void
  54. ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
  55. PRIVATE void
  56. ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
  57. PRIVATE IX_STATUS
  58. ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
  59. UINT32 qBuffer);
  60. PRIVATE IX_STATUS
  61. ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
  62. UINT32 qBuffer);
  63. PRIVATE IX_STATUS
  64. ixEthAccQmgrTxWrite(IxEthAccPortId portId,
  65. UINT32 qBuffer,
  66. UINT32 priority);
  67. /**
  68. * @addtogroup IxEthAccPri
  69. *@{
  70. */
  71. /* increment a counter only when stats are enabled */
  72. #define TX_STATS_INC(port,field) \
  73. IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
  74. #define RX_STATS_INC(port,field) \
  75. IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
  76. /* always increment the counter (mainly used for unexpected errors) */
  77. #define TX_INC(port,field) \
  78. ixEthAccPortData[port].ixEthAccTxData.stats.field++
  79. #define RX_INC(port,field) \
  80. ixEthAccPortData[port].ixEthAccRxData.stats.field++
  81. PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats;
  82. extern IxEthAccPortDataInfo ixEthAccPortData[];
  83. extern IxEthAccInfo ixEthAccDataInfo;
  84. PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
  85. PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
  86. /**
  87. *
  88. * @brief Mbuf header conversion macros : they implement the
  89. * different conversions using a temporary value. They also double-check
  90. * that the parameters can be converted to/from NPE format.
  91. *
  92. */
  93. #if defined(__wince) && !defined(IN_KERNEL)
  94. #define PTR_VIRT2NPE(ptrSrc,dst) \
  95. do { UINT32 temp; \
  96. IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
  97. IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
  98. temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
  99. (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
  100. while(0)
  101. #define PTR_NPE2VIRT(type,src,ptrDst) \
  102. do { void *temp; \
  103. IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
  104. IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
  105. IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
  106. temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
  107. (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
  108. while(0)
  109. #else
  110. #define PTR_VIRT2NPE(ptrSrc,dst) \
  111. do { UINT32 temp; \
  112. IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
  113. IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
  114. temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
  115. (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
  116. while(0)
  117. #define PTR_NPE2VIRT(type,src,ptrDst) \
  118. do { void *temp; \
  119. IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
  120. IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
  121. IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
  122. temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
  123. (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
  124. while(0)
  125. #endif
  126. /**
  127. *
  128. * @brief Mbuf payload pointer conversion macros : Wince has its own
  129. * method to convert the buffer pointers
  130. */
  131. #if defined(__wince) && !defined(IN_KERNEL)
  132. #define DATAPTR_VIRT2NPE(ptrSrc,dst) \
  133. do { UINT32 temp; \
  134. temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
  135. (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
  136. while(0)
  137. #else
  138. #define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
  139. #endif
  140. /* Flush the shared part of the mbuf header */
  141. #define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
  142. do { \
  143. IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
  144. sizeof(IxEthAccNe)); \
  145. } \
  146. while(0)
  147. /* Invalidate the shared part of the mbuf header */
  148. #define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
  149. do { \
  150. IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
  151. sizeof(IxEthAccNe)); \
  152. } \
  153. while(0)
  154. /* Preload one cache line (shared mbuf headers are aligned
  155. * and their size is 1 cache line)
  156. *
  157. * IX_OSAL_CACHED is defined when the mbuf headers are
  158. * allocated from cached memory.
  159. *
  160. * Other processor on emulation environment may not implement
  161. * preload function
  162. */
  163. #ifdef IX_OSAL_CACHED
  164. #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
  165. #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
  166. do { /* preload a cache line (Xscale Processor) */ \
  167. __asm__ (" pld [%0]\n": : "r" (ptr)); \
  168. } \
  169. while(0)
  170. #else
  171. /* preload not implemented on different processor */
  172. #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
  173. do { /* nothing */ } while (0)
  174. #endif
  175. #else
  176. /* preload not needed if cache is not enabled */
  177. #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
  178. do { /* nothing */ } while (0)
  179. #endif
  180. /**
  181. *
  182. * @brief function to retrieve the correct pointer from
  183. * a queue entry posted by the NPE
  184. *
  185. * @param qEntry : entry from qmgr queue
  186. * mask : applicable mask for this queue
  187. * (4 most significant bits are used for additional informations)
  188. *
  189. * @return IX_OSAL_MBUF * pointer to mbuf header
  190. *
  191. * @internal
  192. */
  193. PRIVATE IX_OSAL_MBUF *
  194. ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
  195. {
  196. IX_OSAL_MBUF *mbufPtr;
  197. if (qEntry != 0)
  198. {
  199. /* mask NPE bits (e.g. priority, port ...) */
  200. qEntry &= mask;
  201. #if IX_ACC_DRAM_PHYS_OFFSET != 0
  202. /* restore the original address pointer (if PHYS_OFFSET is not 0) */
  203. qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
  204. #endif
  205. /* get the mbuf pointer address from the npe-shared address */
  206. qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
  207. /* phys2virt mbuf */
  208. mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
  209. /* preload the cacheline shared with NPE */
  210. IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
  211. /* preload the cacheline used by xscale */
  212. IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
  213. }
  214. else
  215. {
  216. mbufPtr = NULL;
  217. }
  218. return mbufPtr;
  219. }
  220. /* Convert the mbuf header for NPE transmission */
  221. PRIVATE UINT32
  222. ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
  223. {
  224. UINT32 qbuf;
  225. UINT32 len;
  226. /* endianess swap for tci and flags
  227. note: this is done only once, even for chained buffers */
  228. IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
  229. IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
  230. /* test for unchained mbufs */
  231. if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
  232. {
  233. /* "best case" scenario : unchained mbufs */
  234. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
  235. /* payload pointer conversion */
  236. DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
  237. /* unchained mbufs : the frame length is the mbuf length
  238. * and the 2 identical lengths are stored in the same
  239. * word.
  240. */
  241. len = IX_OSAL_MBUF_MLEN(mbuf);
  242. /* set the length in both length and pktLen 16-bits fields */
  243. len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
  244. IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
  245. /* unchained mbufs : next contains 0 */
  246. IX_ETHACC_NE_NEXT(mbuf) = 0;
  247. /* flush shared header after all address conversions */
  248. IX_ETHACC_NE_CACHE_FLUSH(mbuf);
  249. }
  250. else
  251. {
  252. /* chained mbufs */
  253. IX_OSAL_MBUF *ptr = mbuf;
  254. IX_OSAL_MBUF *nextPtr;
  255. UINT32 frmLen;
  256. /* get the frame length from the header of the first buffer */
  257. frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
  258. do
  259. {
  260. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
  261. /* payload pointer */
  262. DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
  263. /* Buffer length and frame length are stored in the same word */
  264. len = IX_OSAL_MBUF_MLEN(ptr);
  265. len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
  266. IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
  267. /* get the virtual next chain pointer */
  268. nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
  269. if (nextPtr != NULL)
  270. {
  271. /* shared pointer of the next buffer is chained */
  272. PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
  273. IX_ETHACC_NE_NEXT(ptr));
  274. }
  275. else
  276. {
  277. IX_ETHACC_NE_NEXT(ptr) = 0;
  278. }
  279. /* flush shared header after all address conversions */
  280. IX_ETHACC_NE_CACHE_FLUSH(ptr);
  281. /* move to next buffer */
  282. ptr = nextPtr;
  283. /* the frame length field is set only in the first buffer
  284. * and is zeroed in the next buffers
  285. */
  286. frmLen = 0;
  287. }
  288. while(ptr != NULL);
  289. }
  290. /* virt2phys mbuf itself */
  291. qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
  292. IX_ETHACC_NE_SHARED(mbuf));
  293. /* Ensure the bits which are reserved to exchange information with
  294. * the NPE are cleared
  295. *
  296. * If the mbuf address is not correctly aligned, or from an
  297. * incompatible memory range, there is no point to continue
  298. */
  299. IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
  300. "Invalid address range");
  301. return qbuf;
  302. }
  303. /* Convert the mbuf header for NPE reception */
  304. PRIVATE UINT32
  305. ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
  306. {
  307. UINT32 len;
  308. UINT32 qbuf;
  309. if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
  310. {
  311. /* "best case" scenario : unchained mbufs */
  312. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
  313. /* unchained mbufs : payload pointer */
  314. DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
  315. /* unchained mbufs : set the buffer length
  316. * and the frame length field is zeroed
  317. */
  318. len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
  319. IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
  320. /* unchained mbufs : next pointer is null */
  321. IX_ETHACC_NE_NEXT(mbuf) = 0;
  322. /* flush shared header after all address conversions */
  323. IX_ETHACC_NE_CACHE_FLUSH(mbuf);
  324. /* remove shared header cache line */
  325. IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
  326. }
  327. else
  328. {
  329. /* chained mbufs */
  330. IX_OSAL_MBUF *ptr = mbuf;
  331. IX_OSAL_MBUF *nextPtr;
  332. do
  333. {
  334. /* chained mbufs */
  335. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
  336. /* we must save virtual next chain pointer */
  337. nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
  338. if (nextPtr != NULL)
  339. {
  340. /* chaining pointer for NPE */
  341. PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
  342. IX_ETHACC_NE_NEXT(ptr));
  343. }
  344. else
  345. {
  346. IX_ETHACC_NE_NEXT(ptr) = 0;
  347. }
  348. /* payload pointer */
  349. DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
  350. /* buffer length */
  351. len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
  352. IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
  353. /* flush shared header after all address conversions */
  354. IX_ETHACC_NE_CACHE_FLUSH(ptr);
  355. /* remove shared header cache line */
  356. IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
  357. /* next mbuf in the chain */
  358. ptr = nextPtr;
  359. }
  360. while(ptr != NULL);
  361. }
  362. /* virt2phys mbuf itself */
  363. qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
  364. IX_ETHACC_NE_SHARED(mbuf));
  365. /* Ensure the bits which are reserved to exchange information with
  366. * the NPE are cleared
  367. *
  368. * If the mbuf address is not correctly aligned, or from an
  369. * incompatible memory range, there is no point to continue
  370. */
  371. IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
  372. "Invalid address range");
  373. return qbuf;
  374. }
  375. /* Convert the mbuf header after NPE transmission
  376. * Since there is nothing changed by the NPE, there is no need
  377. * to process anything but the update of internal stats
  378. * when they are enabled
  379. */
  380. PRIVATE void
  381. ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
  382. {
  383. #ifndef NDEBUG
  384. /* test for unchained mbufs */
  385. if (IX_ETHACC_NE_NEXT(mbuf) == 0)
  386. {
  387. /* unchained mbufs : update the stats */
  388. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
  389. }
  390. else
  391. {
  392. /* chained mbufs : walk the chain and update the stats */
  393. IX_OSAL_MBUF *ptr = mbuf;
  394. do
  395. {
  396. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
  397. ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
  398. }
  399. while (ptr != NULL);
  400. }
  401. #endif
  402. }
  403. /* Convert the mbuf header after NPE reception */
  404. PRIVATE void
  405. ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
  406. {
  407. UINT32 len;
  408. /* endianess swap for tci and flags
  409. note: this is done only once, even for chained buffers */
  410. IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
  411. IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
  412. /* test for unchained mbufs */
  413. if (IX_ETHACC_NE_NEXT(mbuf) == 0)
  414. {
  415. /* unchained mbufs */
  416. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
  417. /* get the frame length. it is the same than the buffer length */
  418. len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
  419. len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
  420. IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
  421. /* clears the next packet field */
  422. IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
  423. }
  424. else
  425. {
  426. IX_OSAL_MBUF *ptr = mbuf;
  427. IX_OSAL_MBUF *nextPtr;
  428. UINT32 frmLen;
  429. /* convert the frame length */
  430. frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
  431. IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
  432. /* chained mbufs */
  433. do
  434. {
  435. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
  436. /* convert the length */
  437. len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
  438. IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
  439. /* get the next pointer */
  440. PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
  441. if (nextPtr != NULL)
  442. {
  443. nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
  444. }
  445. /* set the next pointer */
  446. IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
  447. /* move to the next buffer */
  448. ptr = nextPtr;
  449. }
  450. while (ptr != NULL);
  451. }
  452. }
  453. /* write to qmgr if possible and report an overflow if not possible
  454. * Use a fast lock to protect the queue write.
  455. * This way, the tx feature is reentrant.
  456. */
  457. PRIVATE IX_STATUS
  458. ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
  459. {
  460. IX_STATUS qStatus;
  461. if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
  462. {
  463. qStatus = ixQMgrQWrite(
  464. IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
  465. &qBuffer);
  466. #ifndef NDEBUG
  467. if (qStatus != IX_SUCCESS)
  468. {
  469. TX_STATS_INC(portId, txOverflow);
  470. }
  471. #endif
  472. ixOsalFastMutexUnlock(&txWriteMutex[portId]);
  473. }
  474. else
  475. {
  476. TX_STATS_INC(portId, txLock);
  477. qStatus = IX_QMGR_Q_OVERFLOW;
  478. }
  479. return qStatus;
  480. }
  481. /* write to qmgr if possible and report an overflow if not possible
  482. * Use a fast lock to protect the queue write.
  483. * This way, the Rx feature is reentrant.
  484. */
  485. PRIVATE IX_STATUS
  486. ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
  487. {
  488. IX_STATUS qStatus;
  489. if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
  490. {
  491. qStatus = ixQMgrQWrite(
  492. IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
  493. &qBuffer);
  494. #ifndef NDEBUG
  495. if (qStatus != IX_SUCCESS)
  496. {
  497. RX_STATS_INC(portId, rxFreeOverflow);
  498. }
  499. #endif
  500. ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
  501. }
  502. else
  503. {
  504. RX_STATS_INC(portId, rxFreeLock);
  505. qStatus = IX_QMGR_Q_OVERFLOW;
  506. }
  507. return qStatus;
  508. }
  509. /*
  510. * Set the priority and write to a qmgr queue.
  511. */
  512. PRIVATE IX_STATUS
  513. ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
  514. {
  515. /* fill the priority field */
  516. qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
  517. return ixEthAccQmgrLockTxWrite(portId, qBuffer);
  518. }
  519. /**
  520. *
  521. * @brief This function will discover the highest priority S/W Tx Q that
  522. * has entries in it
  523. *
  524. * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
  525. * priorityPtr - (out) the priority of the highest priority occupied q will be written
  526. * here
  527. *
  528. * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
  529. * IX_ETH_ACC_FAIL if no Q has entries
  530. *
  531. * @internal
  532. */
  533. PRIVATE IxEthAccStatus
  534. ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
  535. IxEthAccTxPriority *priorityPtr)
  536. {
  537. if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
  538. == FIFO_NO_PRIORITY)
  539. {
  540. if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
  541. ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
  542. {
  543. return IX_ETH_ACC_FAIL;
  544. }
  545. else
  546. {
  547. *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
  548. TX_STATS_INC(portId,txPriority[*priorityPtr]);
  549. return IX_ETH_ACC_SUCCESS;
  550. }
  551. }
  552. else
  553. {
  554. IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
  555. while(1)
  556. {
  557. if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
  558. ixEthAccTxData.txQ[highestPriority]))
  559. {
  560. *priorityPtr = highestPriority;
  561. TX_STATS_INC(portId,txPriority[highestPriority]);
  562. return IX_ETH_ACC_SUCCESS;
  563. }
  564. if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
  565. {
  566. return IX_ETH_ACC_FAIL;
  567. }
  568. highestPriority--;
  569. }
  570. }
  571. }
  572. /**
  573. *
  574. * @brief This function will take a buffer from a TX S/W Q and attempt
  575. * to add it to the relevant TX H/W Q
  576. *
  577. * @param portId - the port whose TX queue is to be written to
  578. * priority - identifies the queue from which the entry is to be read
  579. *
  580. * @internal
  581. */
  582. PRIVATE IxEthAccStatus
  583. ixEthAccTxFromSwQ(IxEthAccPortId portId,
  584. IxEthAccTxPriority priority)
  585. {
  586. IX_OSAL_MBUF *mbuf;
  587. IX_STATUS qStatus;
  588. IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
  589. IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
  590. ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
  591. mbuf);
  592. if (mbuf != NULL)
  593. {
  594. /*
  595. * Add the Tx buffer to the H/W Tx Q
  596. * We do not need to flush here as it is already done
  597. * in TxFrameSubmit().
  598. */
  599. qStatus = ixEthAccQmgrTxWrite(
  600. portId,
  601. IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
  602. priority);
  603. if (qStatus == IX_SUCCESS)
  604. {
  605. TX_STATS_INC(portId,txFromSwQOK);
  606. return IX_SUCCESS;
  607. }
  608. else if (qStatus == IX_QMGR_Q_OVERFLOW)
  609. {
  610. /*
  611. * H/W Q overflow, need to save the buffer
  612. * back on the s/w Q.
  613. * we must put it back on the head of the q to avoid
  614. * reordering packet tx
  615. */
  616. TX_STATS_INC(portId,txFromSwQDelayed);
  617. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
  618. ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
  619. mbuf);
  620. /*enable Q notification*/
  621. qStatus = ixQMgrNotificationEnable(
  622. IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
  623. IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
  624. if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
  625. {
  626. TX_INC(portId,txUnexpectedError);
  627. IX_ETH_ACC_FATAL_LOG(
  628. "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
  629. qStatus, 0, 0, 0, 0, 0);
  630. }
  631. }
  632. else
  633. {
  634. TX_INC(portId,txUnexpectedError);
  635. /* recovery attempt */
  636. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
  637. ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
  638. mbuf);
  639. IX_ETH_ACC_FATAL_LOG(
  640. "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
  641. qStatus, 0, 0, 0, 0, 0);
  642. }
  643. }
  644. else
  645. {
  646. /* sw queue is empty */
  647. }
  648. return IX_ETH_ACC_FAIL;
  649. }
  650. /**
  651. *
  652. * @brief This function will take a buffer from a RXfree S/W Q and attempt
  653. * to add it to the relevant RxFree H/W Q
  654. *
  655. * @param portId - the port whose RXFree queue is to be written to
  656. *
  657. * @internal
  658. */
  659. PRIVATE IxEthAccStatus
  660. ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
  661. {
  662. IX_OSAL_MBUF *mbuf;
  663. IX_STATUS qStatus = IX_SUCCESS;
  664. IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
  665. ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
  666. mbuf);
  667. if (mbuf != NULL)
  668. {
  669. /*
  670. * Add The Rx Buffer to the H/W Free buffer Q if possible
  671. */
  672. qStatus = ixEthAccQmgrLockRxWrite(portId,
  673. IX_OSAL_MMU_VIRT_TO_PHYS(
  674. (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
  675. if (qStatus == IX_SUCCESS)
  676. {
  677. RX_STATS_INC(portId,rxFreeRepFromSwQOK);
  678. /*
  679. * Buffer added to h/w Q.
  680. */
  681. return IX_SUCCESS;
  682. }
  683. else if (qStatus == IX_QMGR_Q_OVERFLOW)
  684. {
  685. /*
  686. * H/W Q overflow, need to save the buffer back on the s/w Q.
  687. */
  688. RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
  689. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
  690. ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
  691. mbuf);
  692. }
  693. else
  694. {
  695. /* unexpected qmgr error */
  696. RX_INC(portId,rxUnexpectedError);
  697. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
  698. ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
  699. mbuf);
  700. IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
  701. qStatus, 0, 0, 0, 0, 0);
  702. }
  703. }
  704. else
  705. {
  706. /* sw queue is empty */
  707. }
  708. return IX_ETH_ACC_FAIL;
  709. }
  710. IX_ETH_ACC_PUBLIC
  711. IxEthAccStatus ixEthAccInitDataPlane()
  712. {
  713. UINT32 portId;
  714. /*
  715. * Initialize the service and register callback to other services.
  716. */
  717. IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
  718. 0,
  719. sizeof(ixEthAccDataStats));
  720. for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  721. {
  722. ixOsalFastMutexInit(&txWriteMutex[portId]);
  723. ixOsalFastMutexInit(&rxWriteMutex[portId]);
  724. IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
  725. 0,
  726. sizeof(ixEthAccPortData[portId]));
  727. ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
  728. }
  729. return (IX_ETH_ACC_SUCCESS);
  730. }
  731. IX_ETH_ACC_PUBLIC
  732. IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
  733. IxEthAccPortTxDoneCallback
  734. txCallbackFn,
  735. UINT32 callbackTag)
  736. {
  737. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  738. {
  739. return (IX_ETH_ACC_FAIL);
  740. }
  741. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  742. {
  743. return (IX_ETH_ACC_INVALID_PORT);
  744. }
  745. /* HACK: removing this code to enable NPE-A preliminary testing
  746. * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  747. * {
  748. * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
  749. * return IX_ETH_ACC_SUCCESS ;
  750. * }
  751. */
  752. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  753. {
  754. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  755. }
  756. if (txCallbackFn == 0)
  757. /* Check for null function pointer here. */
  758. {
  759. return (IX_ETH_ACC_INVALID_ARG);
  760. }
  761. ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
  762. ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
  763. return (IX_ETH_ACC_SUCCESS);
  764. }
  765. IX_ETH_ACC_PUBLIC
  766. IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
  767. IxEthAccPortRxCallback
  768. rxCallbackFn,
  769. UINT32 callbackTag)
  770. {
  771. IxEthAccPortId port;
  772. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  773. {
  774. return (IX_ETH_ACC_FAIL);
  775. }
  776. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  777. {
  778. return (IX_ETH_ACC_INVALID_PORT);
  779. }
  780. if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  781. {
  782. IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
  783. return IX_ETH_ACC_SUCCESS ;
  784. }
  785. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  786. {
  787. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  788. }
  789. /* Check for null function pointer here. */
  790. if (rxCallbackFn == NULL)
  791. {
  792. return (IX_ETH_ACC_INVALID_ARG);
  793. }
  794. /* Check the user is not changing the callback type
  795. * when the port is enabled.
  796. */
  797. if (ixEthAccMacState[portId].portDisableState == ACTIVE)
  798. {
  799. for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
  800. {
  801. if ((ixEthAccMacState[port].portDisableState == ACTIVE)
  802. && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
  803. {
  804. /* one of the active ports has a different rx callback type.
  805. * Changing the callback type when the port is enabled
  806. * is not safe
  807. */
  808. return (IX_ETH_ACC_INVALID_ARG);
  809. }
  810. }
  811. }
  812. /* update the callback pointer : this is done before
  813. * registering the new qmgr callback
  814. */
  815. ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
  816. ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
  817. /* update the qmgr callback for rx queues */
  818. if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
  819. != IX_ETH_ACC_SUCCESS)
  820. {
  821. /* unexpected qmgr error */
  822. IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
  823. "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
  824. RX_INC(portId,rxUnexpectedError);
  825. return (IX_ETH_ACC_INVALID_ARG);
  826. }
  827. ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
  828. return (IX_ETH_ACC_SUCCESS);
  829. }
  830. IX_ETH_ACC_PUBLIC
  831. IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
  832. IxEthAccPortId portId,
  833. IxEthAccPortMultiBufferRxCallback
  834. rxCallbackFn,
  835. UINT32 callbackTag)
  836. {
  837. IxEthAccPortId port;
  838. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  839. {
  840. return (IX_ETH_ACC_FAIL);
  841. }
  842. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  843. {
  844. return (IX_ETH_ACC_INVALID_PORT);
  845. }
  846. if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  847. {
  848. IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
  849. return IX_ETH_ACC_SUCCESS ;
  850. }
  851. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  852. {
  853. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  854. }
  855. /* Check for null function pointer here. */
  856. if (rxCallbackFn == NULL)
  857. {
  858. return (IX_ETH_ACC_INVALID_ARG);
  859. }
  860. /* Check the user is not changing the callback type
  861. * when the port is enabled.
  862. */
  863. if (ixEthAccMacState[portId].portDisableState == ACTIVE)
  864. {
  865. for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
  866. {
  867. if ((ixEthAccMacState[port].portDisableState == ACTIVE)
  868. && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
  869. {
  870. /* one of the active ports has a different rx callback type.
  871. * Changing the callback type when the port is enabled
  872. * is not safe
  873. */
  874. return (IX_ETH_ACC_INVALID_ARG);
  875. }
  876. }
  877. }
  878. /* update the callback pointer : this is done before
  879. * registering the new qmgr callback
  880. */
  881. ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
  882. ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
  883. /* update the qmgr callback for rx queues */
  884. if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
  885. != IX_ETH_ACC_SUCCESS)
  886. {
  887. /* unexpected qmgr error */
  888. RX_INC(portId,rxUnexpectedError);
  889. IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
  890. "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
  891. return (IX_ETH_ACC_INVALID_ARG);
  892. }
  893. ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
  894. return (IX_ETH_ACC_SUCCESS);
  895. }
  896. IX_ETH_ACC_PUBLIC
  897. IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
  898. IX_OSAL_MBUF *buffer,
  899. IxEthAccTxPriority priority)
  900. {
  901. IX_STATUS qStatus = IX_SUCCESS;
  902. UINT32 qBuffer;
  903. IxEthAccTxPriority highestPriority;
  904. IxQMgrQStatus txQStatus;
  905. #ifndef NDEBUG
  906. if (buffer == NULL)
  907. {
  908. return (IX_ETH_ACC_FAIL);
  909. }
  910. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  911. {
  912. return (IX_ETH_ACC_FAIL);
  913. }
  914. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  915. {
  916. return (IX_ETH_ACC_INVALID_PORT);
  917. }
  918. if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  919. {
  920. IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
  921. (INT32)portId,0,0,0,0,0);
  922. return IX_ETH_ACC_PORT_UNINITIALIZED ;
  923. }
  924. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  925. {
  926. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  927. }
  928. if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
  929. {
  930. return (IX_ETH_ACC_INVALID_ARG);
  931. }
  932. #endif
  933. /*
  934. * Need to Flush the MBUF and its contents (data) as it may be
  935. * read from the NPE. Convert virtual addresses to physical addresses also.
  936. */
  937. qBuffer = ixEthAccMbufTxQPrepare(buffer);
  938. /*
  939. * If no fifo priority set on Xscale ...
  940. */
  941. if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
  942. FIFO_NO_PRIORITY)
  943. {
  944. /*
  945. * Add The Tx Buffer to the H/W Tx Q if possible
  946. * (the priority is passed to the NPE, because
  947. * the NPE is able to reorder the frames
  948. * before transmission to the underlying hardware)
  949. */
  950. qStatus = ixEthAccQmgrTxWrite(portId,
  951. qBuffer,
  952. IX_ETH_ACC_TX_DEFAULT_PRIORITY);
  953. if (qStatus == IX_SUCCESS)
  954. {
  955. TX_STATS_INC(portId,txQOK);
  956. /*
  957. * "best case" scenario : Buffer added to h/w Q.
  958. */
  959. return (IX_SUCCESS);
  960. }
  961. else if (qStatus == IX_QMGR_Q_OVERFLOW)
  962. {
  963. /*
  964. * We were unable to write the buffer to the
  965. * appropriate H/W Q, Save it in the sw Q.
  966. * (use the default priority queue regardless of
  967. * input parameter)
  968. */
  969. priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
  970. }
  971. else
  972. {
  973. /* unexpected qmgr error */
  974. TX_INC(portId,txUnexpectedError);
  975. IX_ETH_ACC_FATAL_LOG(
  976. "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
  977. (UINT32)qStatus, 0, 0, 0, 0, 0);
  978. return (IX_ETH_ACC_FAIL);
  979. }
  980. }
  981. else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
  982. FIFO_PRIORITY)
  983. {
  984. /*
  985. * For priority transmission, put the frame directly on the H/W queue
  986. * if the H/W queue is empty, otherwise, put it in a S/W Q
  987. */
  988. ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
  989. if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
  990. {
  991. /*The tx queue is empty, check whether there are buffers on the s/w queues*/
  992. if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
  993. !=IX_ETH_ACC_FAIL)
  994. {
  995. /*there are buffers on the s/w queues, submit them*/
  996. ixEthAccTxFromSwQ(portId, highestPriority);
  997. /* the queue was empty, 1 buffer is already supplied
  998. * but is likely to be immediately transmitted and the
  999. * hw queue is likely to be empty again, so submit
  1000. * more from the sw queues
  1001. */
  1002. if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
  1003. !=IX_ETH_ACC_FAIL)
  1004. {
  1005. ixEthAccTxFromSwQ(portId, highestPriority);
  1006. /*
  1007. * and force the buffer supplied to be placed
  1008. * on a priority queue
  1009. */
  1010. qStatus = IX_QMGR_Q_OVERFLOW;
  1011. }
  1012. else
  1013. {
  1014. /*there are no buffers in the s/w queues, submit directly*/
  1015. qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
  1016. }
  1017. }
  1018. else
  1019. {
  1020. /*there are no buffers in the s/w queues, submit directly*/
  1021. qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
  1022. }
  1023. }
  1024. else
  1025. {
  1026. qStatus = IX_QMGR_Q_OVERFLOW;
  1027. }
  1028. }
  1029. else
  1030. {
  1031. TX_INC(portId,txUnexpectedError);
  1032. IX_ETH_ACC_FATAL_LOG(
  1033. "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
  1034. 0, 0, 0, 0, 0, 0);
  1035. return (IX_ETH_ACC_FAIL);
  1036. }
  1037. if(qStatus == IX_SUCCESS )
  1038. {
  1039. TX_STATS_INC(portId,txQOK);
  1040. return IX_ETH_ACC_SUCCESS;
  1041. }
  1042. else if(qStatus == IX_QMGR_Q_OVERFLOW)
  1043. {
  1044. TX_STATS_INC(portId,txQDelayed);
  1045. /*
  1046. * We were unable to write the buffer to the
  1047. * appropriate H/W Q, Save it in a s/w Q.
  1048. */
  1049. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
  1050. ixEthAccPortData[portId].
  1051. ixEthAccTxData.txQ[priority],
  1052. buffer);
  1053. qStatus = ixQMgrNotificationEnable(
  1054. IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
  1055. IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
  1056. if (qStatus != IX_SUCCESS)
  1057. {
  1058. if (qStatus == IX_QMGR_WARNING)
  1059. {
  1060. /* notification is enabled for a queue
  1061. * which is already empty (the condition is already met)
  1062. * and there will be no more queue event to drain the sw queue
  1063. */
  1064. TX_STATS_INC(portId,txLateNotificationEnabled);
  1065. /* pull a buffer from the sw queue */
  1066. if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
  1067. !=IX_ETH_ACC_FAIL)
  1068. {
  1069. /*there are buffers on the s/w queues, submit from them*/
  1070. ixEthAccTxFromSwQ(portId, highestPriority);
  1071. }
  1072. }
  1073. else
  1074. {
  1075. TX_INC(portId,txUnexpectedError);
  1076. IX_ETH_ACC_FATAL_LOG(
  1077. "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
  1078. qStatus, 0, 0, 0, 0, 0);
  1079. }
  1080. }
  1081. }
  1082. else
  1083. {
  1084. TX_INC(portId,txUnexpectedError);
  1085. IX_ETH_ACC_FATAL_LOG(
  1086. "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
  1087. qStatus, 0, 0, 0, 0, 0);
  1088. return (IX_ETH_ACC_FAIL);
  1089. }
  1090. return (IX_ETH_ACC_SUCCESS);
  1091. }
  1092. /**
  1093. *
  1094. * @brief replenish: convert a chain of mbufs to the format
  1095. * expected by the NPE
  1096. *
  1097. */
  1098. IX_ETH_ACC_PUBLIC
  1099. IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
  1100. IX_OSAL_MBUF *buffer)
  1101. {
  1102. IX_STATUS qStatus = IX_SUCCESS;
  1103. UINT32 qBuffer;
  1104. /*
  1105. * Check buffer is valid.
  1106. */
  1107. #ifndef NDEBUG
  1108. /* check parameter value */
  1109. if (buffer == 0)
  1110. {
  1111. return (IX_ETH_ACC_FAIL);
  1112. }
  1113. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  1114. {
  1115. return (IX_ETH_ACC_FAIL);
  1116. }
  1117. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  1118. {
  1119. return (IX_ETH_ACC_INVALID_PORT);
  1120. }
  1121. /* check initialisation is done */
  1122. if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  1123. {
  1124. IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
  1125. return IX_ETH_ACC_PORT_UNINITIALIZED ;
  1126. }
  1127. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  1128. {
  1129. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  1130. }
  1131. /* check boundaries and constraints */
  1132. if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
  1133. {
  1134. return (IX_ETH_ACC_FAIL);
  1135. }
  1136. #endif
  1137. qBuffer = ixEthAccMbufRxQPrepare(buffer);
  1138. /*
  1139. * Add The Rx Buffer to the H/W Free buffer Q if possible
  1140. */
  1141. qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
  1142. if (qStatus == IX_SUCCESS)
  1143. {
  1144. RX_STATS_INC(portId,rxFreeRepOK);
  1145. /*
  1146. * Buffer added to h/w Q.
  1147. */
  1148. return (IX_SUCCESS);
  1149. }
  1150. else if (qStatus == IX_QMGR_Q_OVERFLOW)
  1151. {
  1152. RX_STATS_INC(portId,rxFreeRepDelayed);
  1153. /*
  1154. * We were unable to write the buffer to the approprate H/W Q,
  1155. * Save it in a s/w Q.
  1156. */
  1157. IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
  1158. ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
  1159. buffer);
  1160. qStatus = ixQMgrNotificationEnable(
  1161. IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
  1162. IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
  1163. if (qStatus != IX_SUCCESS)
  1164. {
  1165. if (qStatus == IX_QMGR_WARNING)
  1166. {
  1167. /* notification is enabled for a queue
  1168. * which is already empty (the condition is already met)
  1169. * and there will be no more queue event to drain the sw queue
  1170. * move an entry from the sw queue to the hw queue */
  1171. RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
  1172. ixEthAccRxFreeFromSwQ(portId);
  1173. }
  1174. else
  1175. {
  1176. RX_INC(portId,rxUnexpectedError);
  1177. IX_ETH_ACC_FATAL_LOG(
  1178. "ixEthAccRxPortFreeReplenish:Error: %u\n",
  1179. qStatus, 0, 0, 0, 0, 0);
  1180. }
  1181. }
  1182. }
  1183. else
  1184. {
  1185. RX_INC(portId,rxUnexpectedError);
  1186. IX_ETH_ACC_FATAL_LOG(
  1187. "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
  1188. (UINT32)qStatus, 0, 0, 0, 0, 0);
  1189. return(IX_ETH_ACC_FAIL);
  1190. }
  1191. return (IX_ETH_ACC_SUCCESS);
  1192. }
  1193. IX_ETH_ACC_PUBLIC
  1194. IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
  1195. IxEthAccSchedulerDiscipline
  1196. sched)
  1197. {
  1198. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  1199. {
  1200. return (IX_ETH_ACC_INVALID_PORT);
  1201. }
  1202. if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
  1203. {
  1204. IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
  1205. return IX_ETH_ACC_SUCCESS ;
  1206. }
  1207. if (!IX_ETH_IS_PORT_INITIALIZED(portId))
  1208. {
  1209. return (IX_ETH_ACC_PORT_UNINITIALIZED);
  1210. }
  1211. if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
  1212. {
  1213. return (IX_ETH_ACC_INVALID_ARG);
  1214. }
  1215. ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
  1216. return (IX_ETH_ACC_SUCCESS);
  1217. }
  1218. IX_ETH_ACC_PUBLIC
  1219. IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
  1220. sched)
  1221. {
  1222. if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
  1223. {
  1224. return (IX_ETH_ACC_INVALID_ARG);
  1225. }
  1226. ixEthAccDataInfo.schDiscipline = sched;
  1227. return (IX_ETH_ACC_SUCCESS);
  1228. }
  1229. /**
  1230. * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
  1231. *
  1232. * @brief process incoming frame :
  1233. *
  1234. * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
  1235. *
  1236. * @return none
  1237. *
  1238. * @internal
  1239. *
  1240. */
  1241. IX_ETH_ACC_PRIVATE BOOL
  1242. ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
  1243. {
  1244. UINT32 flags;
  1245. IxEthDBStatus result;
  1246. #ifndef NDEBUG
  1247. /* Prudent to at least check the port is within range */
  1248. if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
  1249. {
  1250. ixEthAccDataStats.unexpectedError++;
  1251. IX_ETH_ACC_FATAL_LOG(
  1252. "ixEthRxFrameProcess: Illegal port: %u\n",
  1253. (UINT32)portId, 0, 0, 0, 0, 0);
  1254. return false;
  1255. }
  1256. #endif
  1257. /* convert fields from mbuf header */
  1258. ixEthAccMbufFromRxQ(mbufPtr);
  1259. /* check about any special processing for this frame */
  1260. flags = IX_ETHACC_NE_FLAGS(mbufPtr);
  1261. if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
  1262. {
  1263. /* "best case" scenario : nothing special to do for this frame */
  1264. return true;
  1265. }
  1266. #ifdef CONFIG_IXP425_COMPONENT_ETHDB
  1267. /* if a new source MAC address is detected by the NPE,
  1268. * update IxEthDB with the portId and the MAC address.
  1269. */
  1270. if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
  1271. {
  1272. result = ixEthDBFilteringDynamicEntryProvision(portId,
  1273. (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
  1274. if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
  1275. {
  1276. if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
  1277. {
  1278. RX_STATS_INC(portId, rxUnexpectedError);
  1279. IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
  1280. to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
  1281. }
  1282. else
  1283. {
  1284. /* we expect this to fail during PortDisable, as EthDB is disabled for
  1285. * that port and will refuse to learn new addresses
  1286. */
  1287. }
  1288. }
  1289. else
  1290. {
  1291. RX_STATS_INC(portId, rxUnlearnedMacAddress);
  1292. }
  1293. }
  1294. #endif
  1295. /* check if this frame should have been filtered
  1296. * by the NPE and take the appropriate action
  1297. */
  1298. if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
  1299. && (ixEthAccMacState[portId].portDisableState == ACTIVE))
  1300. {
  1301. /* If the mbuf was allocated with a small data size, or the current data pointer is not
  1302. * within the allocated data area, then the buffer is non-standard and has to be
  1303. * replenished with the minimum size only
  1304. */
  1305. if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
  1306. || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
  1307. || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
  1308. IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
  1309. < IX_OSAL_MBUF_MDATA(mbufPtr)) )
  1310. {
  1311. /* set to minimum length */
  1312. IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
  1313. IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
  1314. }
  1315. else
  1316. {
  1317. /* restore original length */
  1318. IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
  1319. ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
  1320. (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
  1321. }
  1322. /* replenish from here */
  1323. if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
  1324. {
  1325. IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
  1326. on port %d\n", portId, 0, 0, 0, 0, 0);
  1327. }
  1328. RX_STATS_INC(portId, rxFiltered);
  1329. /* indicate that frame should not be subjected to further processing */
  1330. return false;
  1331. }
  1332. return true;
  1333. }
  1334. /**
  1335. * @fn ixEthRxFrameQMCallback
  1336. *
  1337. * @brief receive callback for Frame receive Q from NPE
  1338. *
  1339. * Frames are passed one-at-a-time to the user
  1340. *
  1341. * @param @ref IxQMgrCallback
  1342. *
  1343. * @return none
  1344. *
  1345. * @internal
  1346. *
  1347. * Design note : while processing the entry X, entry X+1 is preloaded
  1348. * into memory to reduce the number of stall cycles
  1349. *
  1350. */
  1351. void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
  1352. {
  1353. IX_OSAL_MBUF *mbufPtr;
  1354. IX_OSAL_MBUF *nextMbufPtr;
  1355. UINT32 qEntry;
  1356. UINT32 nextQEntry;
  1357. UINT32 *qEntryPtr;
  1358. UINT32 portId;
  1359. UINT32 destPortId;
  1360. UINT32 npeId;
  1361. UINT32 rxQReadStatus;
  1362. /*
  1363. * Design note : entries are read in a buffer, This buffer contains
  1364. * an extra zeroed entry so the loop will
  1365. * always terminate on a null entry, whatever the result of Burst read is.
  1366. */
  1367. UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
  1368. /*
  1369. * Indication of the number of times the callback is used.
  1370. */
  1371. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
  1372. do
  1373. {
  1374. /*
  1375. * Indication of the number of times the queue is drained
  1376. */
  1377. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
  1378. /* ensure the last entry of the array contains a zeroed value */
  1379. qEntryPtr = rxQEntry;
  1380. qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
  1381. rxQReadStatus = ixQMgrQBurstRead(qId,
  1382. IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
  1383. qEntryPtr);
  1384. #ifndef NDEBUG
  1385. if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
  1386. && (rxQReadStatus != IX_SUCCESS))
  1387. {
  1388. ixEthAccDataStats.unexpectedError++;
  1389. /*major error*/
  1390. IX_ETH_ACC_FATAL_LOG(
  1391. "ixEthRxFrameQMCallback:Error: %u\n",
  1392. (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
  1393. return;
  1394. }
  1395. #endif
  1396. /* convert and preload the next entry
  1397. * (the conversion function takes care about null pointers which
  1398. * are used to mark the end of the loop)
  1399. */
  1400. nextQEntry = *qEntryPtr;
  1401. nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
  1402. IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
  1403. while(nextQEntry != 0)
  1404. {
  1405. /* get the next entry */
  1406. qEntry = nextQEntry;
  1407. mbufPtr = nextMbufPtr;
  1408. #ifndef NDEBUG
  1409. if (mbufPtr == NULL)
  1410. {
  1411. ixEthAccDataStats.unexpectedError++;
  1412. IX_ETH_ACC_FATAL_LOG(
  1413. "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
  1414. 0, 0, 0, 0, 0, 0);
  1415. return;
  1416. }
  1417. #endif
  1418. /* convert the next entry
  1419. * (the conversion function takes care about null pointers which
  1420. * are used to mark the end of the loop)
  1421. */
  1422. nextQEntry = *(++qEntryPtr);
  1423. nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
  1424. IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
  1425. /*
  1426. * Get Port and Npe ID from message.
  1427. */
  1428. npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
  1429. qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
  1430. portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
  1431. /* process frame, check the return code and skip the remaining of
  1432. * the loop if the frame is to be filtered out
  1433. */
  1434. if (ixEthRxFrameProcess(portId, mbufPtr))
  1435. {
  1436. /* destination portId for this packet */
  1437. destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
  1438. if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
  1439. {
  1440. destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
  1441. }
  1442. /* test if QoS is enabled in ethAcc
  1443. */
  1444. if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
  1445. {
  1446. /* check if there is a higher priority queue
  1447. * which may require processing and then process it.
  1448. */
  1449. if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
  1450. {
  1451. ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
  1452. callbackId);
  1453. }
  1454. }
  1455. /*
  1456. * increment priority stats
  1457. */
  1458. RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
  1459. /*
  1460. * increment callback count stats
  1461. */
  1462. RX_STATS_INC(portId,rxFrameClientCallback);
  1463. /*
  1464. * Call user level callback.
  1465. */
  1466. ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
  1467. ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
  1468. mbufPtr,
  1469. destPortId);
  1470. }
  1471. }
  1472. } while (rxQReadStatus == IX_SUCCESS);
  1473. }
  1474. /**
  1475. * @fn ixEthRxMultiBufferQMCallback
  1476. *
  1477. * @brief receive callback for Frame receive Q from NPE
  1478. *
  1479. * Frames are passed as an array to the user
  1480. *
  1481. * @param @ref IxQMgrCallback
  1482. *
  1483. * @return none
  1484. *
  1485. * @internal
  1486. *
  1487. * Design note : while processing the entry X, entry X+1 is preloaded
  1488. * into memory to reduce the number of stall cycles
  1489. *
  1490. */
  1491. void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
  1492. {
  1493. IX_OSAL_MBUF *mbufPtr;
  1494. IX_OSAL_MBUF *nextMbufPtr;
  1495. UINT32 qEntry;
  1496. UINT32 nextQEntry;
  1497. UINT32 *qEntryPtr;
  1498. UINT32 portId;
  1499. UINT32 npeId;
  1500. UINT32 rxQReadStatus;
  1501. /*
  1502. * Design note : entries are read in a static buffer, This buffer contains
  1503. * an extra zeroed entry so the loop will
  1504. * always terminate on a null entry, whatever the result of Burst read is.
  1505. */
  1506. static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
  1507. static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
  1508. IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
  1509. for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  1510. {
  1511. rxMbufPtr[portId] = rxMbufPortArray[portId];
  1512. }
  1513. /*
  1514. * Indication of the number of times the callback is used.
  1515. */
  1516. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
  1517. do
  1518. {
  1519. /*
  1520. * Indication of the number of times the queue is drained
  1521. */
  1522. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
  1523. /* ensure the last entry of the array contains a zeroed value */
  1524. qEntryPtr = rxQEntry;
  1525. qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
  1526. rxQReadStatus = ixQMgrQBurstRead(qId,
  1527. IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
  1528. qEntryPtr);
  1529. #ifndef NDEBUG
  1530. if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
  1531. && (rxQReadStatus != IX_SUCCESS))
  1532. {
  1533. ixEthAccDataStats.unexpectedError++;
  1534. /*major error*/
  1535. IX_ETH_ACC_FATAL_LOG(
  1536. "ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
  1537. (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
  1538. return;
  1539. }
  1540. #endif
  1541. /* convert and preload the next entry
  1542. * (the conversion function takes care about null pointers which
  1543. * are used to mark the end of the loop)
  1544. */
  1545. nextQEntry = *qEntryPtr;
  1546. nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
  1547. IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
  1548. while(nextQEntry != 0)
  1549. {
  1550. /* get the next entry */
  1551. qEntry = nextQEntry;
  1552. mbufPtr = nextMbufPtr;
  1553. #ifndef NDEBUG
  1554. if (mbufPtr == NULL)
  1555. {
  1556. ixEthAccDataStats.unexpectedError++;
  1557. IX_ETH_ACC_FATAL_LOG(
  1558. "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
  1559. 0, 0, 0, 0, 0, 0);
  1560. return;
  1561. }
  1562. #endif
  1563. /* convert the next entry
  1564. * (the conversion function takes care about null pointers which
  1565. * are used to mark the end of the loop)
  1566. */
  1567. nextQEntry = *(++qEntryPtr);
  1568. nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
  1569. IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
  1570. /*
  1571. * Get Port and Npe ID from message.
  1572. */
  1573. npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
  1574. qEntry) >>
  1575. IX_ETHNPE_QM_Q_FIELD_NPEID_R);
  1576. portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
  1577. /* skip the remaining of the loop if the frame is
  1578. * to be filtered out
  1579. */
  1580. if (ixEthRxFrameProcess(portId, mbufPtr))
  1581. {
  1582. /* store a mbuf pointer in an array */
  1583. *rxMbufPtr[portId]++ = mbufPtr;
  1584. /*
  1585. * increment priority stats
  1586. */
  1587. RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
  1588. }
  1589. /* test for QoS enabled in ethAcc */
  1590. if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
  1591. {
  1592. /* check if there is a higher priority queue
  1593. * which may require processing and then process it.
  1594. */
  1595. if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
  1596. {
  1597. ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
  1598. callbackId);
  1599. }
  1600. }
  1601. }
  1602. /* check if any of the the arrays contains any entry */
  1603. for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  1604. {
  1605. if (rxMbufPtr[portId] != rxMbufPortArray[portId])
  1606. {
  1607. /* add a last NULL pointer at the end of the
  1608. * array of mbuf pointers
  1609. */
  1610. *rxMbufPtr[portId] = NULL;
  1611. /*
  1612. * increment callback count stats
  1613. */
  1614. RX_STATS_INC(portId,rxFrameClientCallback);
  1615. /*
  1616. * Call user level callback with an array of
  1617. * buffers (NULL terminated)
  1618. */
  1619. ixEthAccPortData[portId].ixEthAccRxData.
  1620. rxMultiBufferCallbackFn(
  1621. ixEthAccPortData[portId].ixEthAccRxData.
  1622. rxMultiBufferCallbackTag,
  1623. rxMbufPortArray[portId]);
  1624. /* reset the buffer pointer to the beginning of
  1625. * the array
  1626. */
  1627. rxMbufPtr[portId] = rxMbufPortArray[portId];
  1628. }
  1629. }
  1630. } while (rxQReadStatus == IX_SUCCESS);
  1631. }
  1632. /**
  1633. * @brief rxFree low event handler
  1634. *
  1635. */
  1636. void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
  1637. {
  1638. IxEthAccPortId portId = (IxEthAccPortId) callbackId;
  1639. int lockVal;
  1640. UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
  1641. IX_STATUS qStatus = IX_SUCCESS;
  1642. /*
  1643. * We have reached a low threshold on one of the Rx Free Qs
  1644. */
  1645. /*note that due to the fact that we are working off an Empty threshold, this callback
  1646. need only write a single entry to the Rx Free queue in order to re-arm the notification
  1647. */
  1648. RX_STATS_INC(portId,rxFreeLowCallback);
  1649. /*
  1650. * Get buffers from approprite S/W Rx freeBufferList Q.
  1651. */
  1652. #ifndef NDEBUG
  1653. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  1654. {
  1655. ixEthAccDataStats.unexpectedError++;
  1656. IX_ETH_ACC_FATAL_LOG(
  1657. "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
  1658. portId, 0, 0, 0, 0, 0);
  1659. return;
  1660. }
  1661. #endif
  1662. IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
  1663. if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
  1664. ixEthAccRxData.freeBufferList))
  1665. {
  1666. /*
  1667. * Turn off Q callback notification for Q in Question.
  1668. */
  1669. qStatus = ixQMgrNotificationDisable(
  1670. IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
  1671. IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
  1672. if (qStatus != IX_SUCCESS)
  1673. {
  1674. RX_INC(portId,rxUnexpectedError);
  1675. IX_ETH_ACC_FATAL_LOG(
  1676. "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
  1677. qStatus, 0, 0, 0, 0, 0);
  1678. return;
  1679. }
  1680. }
  1681. else
  1682. {
  1683. IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
  1684. /*
  1685. * Load the H/W Q with buffers from the s/w Q.
  1686. */
  1687. do
  1688. {
  1689. /*
  1690. * Consume Q entries. - Note Q contains Physical addresss,
  1691. * and have already been flushed to memory,
  1692. * And endianess converted if required.
  1693. */
  1694. if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
  1695. {
  1696. /*
  1697. * No more entries in s/w Q.
  1698. * Turn off Q callback indication
  1699. */
  1700. IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
  1701. if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
  1702. ixEthAccRxData.freeBufferList))
  1703. {
  1704. qStatus = ixQMgrNotificationDisable(
  1705. IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
  1706. }
  1707. IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
  1708. break;
  1709. }
  1710. }
  1711. while (--maxQWritesToPerform);
  1712. }
  1713. }
  1714. /**
  1715. * @fn Tx queue low event handler
  1716. *
  1717. */
  1718. void
  1719. ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
  1720. {
  1721. IxEthAccPortId portId = (IxEthAccPortId) callbackId;
  1722. int lockVal;
  1723. UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
  1724. IX_STATUS qStatus = IX_SUCCESS;
  1725. IxEthAccTxPriority highestPriority;
  1726. /*
  1727. * We have reached a low threshold on the Tx Q, and are being asked to
  1728. * supply a buffer for transmission from our S/W TX queues
  1729. */
  1730. TX_STATS_INC(portId,txLowThreshCallback);
  1731. /*
  1732. * Get buffers from approprite Q.
  1733. */
  1734. #ifndef NDEBUG
  1735. if (!IX_ETH_ACC_IS_PORT_VALID(portId))
  1736. {
  1737. ixEthAccDataStats.unexpectedError++;
  1738. IX_ETH_ACC_FATAL_LOG(
  1739. "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
  1740. portId, 0, 0, 0, 0, 0);
  1741. return;
  1742. }
  1743. #endif
  1744. do
  1745. {
  1746. /*
  1747. * Consume Q entries. - Note Q contains Physical addresss,
  1748. * and have already been flushed to memory,
  1749. * and endianess already sone if required.
  1750. */
  1751. IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
  1752. if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
  1753. IX_ETH_ACC_FAIL)
  1754. {
  1755. /*
  1756. * No more entries in s/w Q.
  1757. * Turn off Q callback indication
  1758. */
  1759. qStatus = ixQMgrNotificationDisable(
  1760. IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
  1761. IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
  1762. if (qStatus != IX_SUCCESS)
  1763. {
  1764. ixEthAccDataStats.unexpectedError++;
  1765. IX_ETH_ACC_FATAL_LOG(
  1766. "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
  1767. qStatus, 0, 0, 0, 0, 0);
  1768. }
  1769. return;
  1770. }
  1771. else
  1772. {
  1773. IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
  1774. if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
  1775. {
  1776. /* nothing left in the sw queue or the hw queues are
  1777. * full. There is no point to continue to drain the
  1778. * sw queues
  1779. */
  1780. return;
  1781. }
  1782. }
  1783. }
  1784. while (--maxQWritesToPerform);
  1785. }
  1786. /**
  1787. * @brief TxDone event handler
  1788. *
  1789. * Design note : while processing the entry X, entry X+1 is preloaded
  1790. * into memory to reduce the number of stall cycles
  1791. *
  1792. */
  1793. void
  1794. ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
  1795. {
  1796. IX_OSAL_MBUF *mbufPtr;
  1797. UINT32 qEntry;
  1798. UINT32 *qEntryPtr;
  1799. UINT32 txDoneQReadStatus;
  1800. UINT32 portId;
  1801. UINT32 npeId;
  1802. /*
  1803. * Design note : entries are read in a static buffer, This buffer contains
  1804. * an extra entyry (which is zeroed by the compiler), so the loop will
  1805. * always terminate on a null entry, whatever the result of Burst read is.
  1806. */
  1807. static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
  1808. /*
  1809. * Indication that Tx frames have been transmitted from the NPE.
  1810. */
  1811. IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
  1812. do{
  1813. qEntryPtr = txDoneQEntry;
  1814. txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
  1815. IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
  1816. qEntryPtr);
  1817. #ifndef NDEBUG
  1818. if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
  1819. && (txDoneQReadStatus != IX_SUCCESS))
  1820. {
  1821. /*major error*/
  1822. ixEthAccDataStats.unexpectedError++;
  1823. IX_ETH_ACC_FATAL_LOG(
  1824. "ixEthTxFrameDoneQMCallback:Error: %u\n",
  1825. (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
  1826. return;
  1827. }
  1828. #endif
  1829. qEntry = *qEntryPtr;
  1830. while(qEntry != 0)
  1831. {
  1832. mbufPtr = ixEthAccEntryFromQConvert(qEntry,
  1833. IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
  1834. #ifndef NDEBUG
  1835. if (mbufPtr == NULL)
  1836. {
  1837. ixEthAccDataStats.unexpectedError++;
  1838. IX_ETH_ACC_FATAL_LOG(
  1839. "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
  1840. 0, 0, 0, 0, 0, 0);
  1841. return;
  1842. }
  1843. #endif
  1844. /* endianness conversions and stats updates */
  1845. ixEthAccMbufFromTxQ(mbufPtr);
  1846. /*
  1847. * Get NPE id from message, then convert to portId.
  1848. */
  1849. npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
  1850. qEntry) >>
  1851. IX_ETHNPE_QM_Q_FIELD_NPEID_R);
  1852. portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
  1853. #ifndef NDEBUG
  1854. /* Prudent to at least check the port is within range */
  1855. if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
  1856. {
  1857. ixEthAccDataStats.unexpectedError++;
  1858. IX_ETH_ACC_FATAL_LOG(
  1859. "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
  1860. (UINT32)portId, 0, 0, 0, 0, 0);
  1861. return;
  1862. }
  1863. #endif
  1864. TX_STATS_INC(portId,txDoneClientCallback);
  1865. /*
  1866. * Call user level callback.
  1867. */
  1868. ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
  1869. ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
  1870. mbufPtr);
  1871. /* move to next queue entry */
  1872. qEntry = *(++qEntryPtr);
  1873. }
  1874. } while( txDoneQReadStatus == IX_SUCCESS );
  1875. }
  1876. IX_ETH_ACC_PUBLIC
  1877. void ixEthAccDataPlaneShow(void)
  1878. {
  1879. UINT32 numTx0Entries;
  1880. UINT32 numTx1Entries;
  1881. UINT32 numTxDoneEntries;
  1882. UINT32 numRxEntries;
  1883. UINT32 numRxFree0Entries;
  1884. UINT32 numRxFree1Entries;
  1885. UINT32 portId;
  1886. #ifdef __ixp46X
  1887. UINT32 numTx2Entries;
  1888. UINT32 numRxFree2Entries;
  1889. #endif
  1890. #ifndef NDEBUG
  1891. UINT32 priority;
  1892. UINT32 numBuffersInRx=0;
  1893. UINT32 numBuffersInTx=0;
  1894. UINT32 numBuffersInSwQ=0;
  1895. UINT32 totalBuffers=0;
  1896. UINT32 rxFreeCallbackCounter = 0;
  1897. UINT32 txCallbackCounter = 0;
  1898. #endif
  1899. UINT32 key;
  1900. /* snapshot of stats */
  1901. IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
  1902. IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
  1903. IxEthAccDataPlaneStats stats;
  1904. if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
  1905. {
  1906. return;
  1907. }
  1908. /* get a reliable snapshot */
  1909. key = ixOsalIrqLock();
  1910. numTx0Entries = 0;
  1911. ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
  1912. numTx1Entries = 0;
  1913. ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
  1914. numTxDoneEntries = 0;
  1915. ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
  1916. numRxEntries = 0;
  1917. ixEthAccQMgrRxQEntryGet(&numRxEntries);
  1918. numRxFree0Entries = 0;
  1919. ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
  1920. numRxFree1Entries = 0;
  1921. ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
  1922. #ifdef __ixp46X
  1923. numTx2Entries = 0;
  1924. ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
  1925. numRxFree2Entries = 0;
  1926. ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
  1927. #endif
  1928. for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  1929. {
  1930. memcpy(&tx[portId],
  1931. &ixEthAccPortData[portId].ixEthAccTxData.stats,
  1932. sizeof(tx[portId]));
  1933. memcpy(&rx[portId],
  1934. &ixEthAccPortData[portId].ixEthAccRxData.stats,
  1935. sizeof(rx[portId]));
  1936. }
  1937. memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
  1938. ixOsalIrqUnlock(key);
  1939. #ifdef NDEBUG
  1940. printf("Detailed statistics collection not supported in this load\n");
  1941. #endif
  1942. /* print snapshot */
  1943. for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  1944. {
  1945. /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
  1946. if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
  1947. (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
  1948. || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
  1949. {
  1950. if ((IX_ETH_PORT_1 == portId) &&
  1951. (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
  1952. IX_FEATURE_CTRL_COMPONENT_DISABLED))
  1953. {
  1954. continue ;
  1955. }
  1956. if ((IX_ETH_PORT_2 == portId) &&
  1957. (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
  1958. IX_FEATURE_CTRL_COMPONENT_DISABLED))
  1959. {
  1960. continue ;
  1961. }
  1962. if ((IX_ETH_PORT_3 == portId) &&
  1963. (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
  1964. IX_FEATURE_CTRL_COMPONENT_DISABLED))
  1965. {
  1966. continue ;
  1967. }
  1968. }
  1969. printf("PORT %u --------------------------------\n",
  1970. portId);
  1971. #ifndef NDEBUG
  1972. printf("Tx Done Frames : %u\n",
  1973. tx[portId].txDoneClientCallback +
  1974. tx[portId].txDoneSwQDuringDisable +
  1975. tx[portId].txDoneDuringDisable);
  1976. printf("Tx Frames : %u\n",
  1977. tx[portId].txQOK + tx[portId].txQDelayed);
  1978. printf("Tx H/W Q Added OK : %u\n",
  1979. tx[portId].txQOK);
  1980. printf("Tx H/W Q Delayed : %u\n",
  1981. tx[portId].txQDelayed);
  1982. printf("Tx From S/W Q Added OK : %u\n",
  1983. tx[portId].txFromSwQOK);
  1984. printf("Tx From S/W Q Delayed : %u\n",
  1985. tx[portId].txFromSwQDelayed);
  1986. printf("Tx Overflow : %u\n",
  1987. tx[portId].txOverflow);
  1988. printf("Tx Mutual Lock : %u\n",
  1989. tx[portId].txLock);
  1990. printf("Tx Late Ntf Enabled : %u\n",
  1991. tx[portId].txLateNotificationEnabled);
  1992. printf("Tx Low Thresh CB : %u\n",
  1993. tx[portId].txLowThreshCallback);
  1994. printf("Tx Done from H/W Q (Disable) : %u\n",
  1995. tx[portId].txDoneDuringDisable);
  1996. printf("Tx Done from S/W Q (Disable) : %u\n",
  1997. tx[portId].txDoneSwQDuringDisable);
  1998. for (priority = IX_ETH_ACC_TX_PRIORITY_0;
  1999. priority <= IX_ETH_ACC_TX_PRIORITY_7;
  2000. priority++)
  2001. {
  2002. if (tx[portId].txPriority[priority])
  2003. {
  2004. printf("Tx Priority %u : %u\n",
  2005. priority,
  2006. tx[portId].txPriority[priority]);
  2007. }
  2008. }
  2009. #endif
  2010. printf("Tx unexpected errors : %u (should be 0)\n",
  2011. tx[portId].txUnexpectedError);
  2012. #ifndef NDEBUG
  2013. printf("Rx Frames : %u\n",
  2014. rx[portId].rxFrameClientCallback +
  2015. rx[portId].rxSwQDuringDisable+
  2016. rx[portId].rxDuringDisable);
  2017. printf("Rx Free Replenish : %u\n",
  2018. rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
  2019. printf("Rx Free H/W Q Added OK : %u\n",
  2020. rx[portId].rxFreeRepOK);
  2021. printf("Rx Free H/W Q Delayed : %u\n",
  2022. rx[portId].rxFreeRepDelayed);
  2023. printf("Rx Free From S/W Q Added OK : %u\n",
  2024. rx[portId].rxFreeRepFromSwQOK);
  2025. printf("Rx Free From S/W Q Delayed : %u\n",
  2026. rx[portId].rxFreeRepFromSwQDelayed);
  2027. printf("Rx Free Overflow : %u\n",
  2028. rx[portId].rxFreeOverflow);
  2029. printf("Rx Free Mutual Lock : %u\n",
  2030. rx[portId].rxFreeLock);
  2031. printf("Rx Free Late Ntf Enabled : %u\n",
  2032. rx[portId].rxFreeLateNotificationEnabled);
  2033. printf("Rx Free Low CB : %u\n",
  2034. rx[portId].rxFreeLowCallback);
  2035. printf("Rx From H/W Q (Disable) : %u\n",
  2036. rx[portId].rxDuringDisable);
  2037. printf("Rx From S/W Q (Disable) : %u\n",
  2038. rx[portId].rxSwQDuringDisable);
  2039. printf("Rx unlearned Mac Address : %u\n",
  2040. rx[portId].rxUnlearnedMacAddress);
  2041. printf("Rx Filtered (Rx => RxFree) : %u\n",
  2042. rx[portId].rxFiltered);
  2043. for (priority = IX_ETH_ACC_TX_PRIORITY_0;
  2044. priority <= IX_ETH_ACC_TX_PRIORITY_7;
  2045. priority++)
  2046. {
  2047. if (rx[portId].rxPriority[priority])
  2048. {
  2049. printf("Rx Priority %u : %u\n",
  2050. priority,
  2051. rx[portId].rxPriority[priority]);
  2052. }
  2053. }
  2054. #endif
  2055. printf("Rx unexpected errors : %u (should be 0)\n",
  2056. rx[portId].rxUnexpectedError);
  2057. #ifndef NDEBUG
  2058. numBuffersInTx = tx[portId].txQOK +
  2059. tx[portId].txQDelayed -
  2060. tx[portId].txDoneClientCallback -
  2061. tx[portId].txDoneSwQDuringDisable -
  2062. tx[portId].txDoneDuringDisable;
  2063. printf("# Tx Buffers currently for transmission : %u\n",
  2064. numBuffersInTx);
  2065. numBuffersInRx = rx[portId].rxFreeRepOK +
  2066. rx[portId].rxFreeRepDelayed -
  2067. rx[portId].rxFrameClientCallback -
  2068. rx[portId].rxSwQDuringDisable -
  2069. rx[portId].rxDuringDisable;
  2070. printf("# Rx Buffers currently for reception : %u\n",
  2071. numBuffersInRx);
  2072. totalBuffers += numBuffersInRx + numBuffersInTx;
  2073. #endif
  2074. }
  2075. printf("---------------------------------------\n");
  2076. #ifndef NDEBUG
  2077. printf("\n");
  2078. printf("Mbufs :\n");
  2079. printf("Tx Unchained mbufs : %u\n",
  2080. stats.unchainedTxMBufs);
  2081. printf("Tx Chained bufs : %u\n",
  2082. stats.chainedTxMBufs);
  2083. printf("TxDone Unchained mbufs : %u\n",
  2084. stats.unchainedTxDoneMBufs);
  2085. printf("TxDone Chained bufs : %u\n",
  2086. stats.chainedTxDoneMBufs);
  2087. printf("RxFree Unchained mbufs : %u\n",
  2088. stats.unchainedRxFreeMBufs);
  2089. printf("RxFree Chained bufs : %u\n",
  2090. stats.chainedRxFreeMBufs);
  2091. printf("Rx Unchained mbufs : %u\n",
  2092. stats.unchainedRxMBufs);
  2093. printf("Rx Chained bufs : %u\n",
  2094. stats.chainedRxMBufs);
  2095. printf("\n");
  2096. printf("Software queue usage :\n");
  2097. printf("Buffers added to S/W Q : %u\n",
  2098. stats.addToSwQ);
  2099. printf("Buffers removed from S/W Q : %u\n",
  2100. stats.removeFromSwQ);
  2101. printf("\n");
  2102. printf("Hardware queues callbacks :\n");
  2103. for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  2104. {
  2105. rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
  2106. txCallbackCounter += tx[portId].txLowThreshCallback;
  2107. }
  2108. printf("Tx Done QM Callback invoked : %u\n",
  2109. stats.txDoneCallbackCounter);
  2110. printf("Tx QM Callback invoked : %u\n",
  2111. txCallbackCounter);
  2112. printf("Rx QM Callback invoked : %u\n",
  2113. stats.rxCallbackCounter);
  2114. printf("Rx QM Callback burst read : %u\n",
  2115. stats.rxCallbackBurstRead);
  2116. printf("Rx Free QM Callback invoked : %u\n",
  2117. rxFreeCallbackCounter);
  2118. #endif
  2119. printf("Unexpected errors in CB : %u (should be 0)\n",
  2120. stats.unexpectedError);
  2121. printf("\n");
  2122. printf("Hardware queues levels :\n");
  2123. printf("Transmit Port 1 Q : %u \n",numTx0Entries);
  2124. printf("Transmit Port 2 Q : %u \n",numTx1Entries);
  2125. #ifdef __ixp46X
  2126. printf("Transmit Port 3 Q : %u \n",numTx2Entries);
  2127. #endif
  2128. printf("Transmit Done Q : %u \n",numTxDoneEntries);
  2129. printf("Receive Q : %u \n",numRxEntries);
  2130. printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries);
  2131. printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries);
  2132. #ifdef __ixp46X
  2133. printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries);
  2134. #endif
  2135. #ifndef NDEBUG
  2136. printf("\n");
  2137. printf("# Total Buffers accounted for : %u\n",
  2138. totalBuffers);
  2139. numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
  2140. ixEthAccDataStats.removeFromSwQ;
  2141. printf(" Buffers in S/W Qs : %u\n",
  2142. numBuffersInSwQ);
  2143. printf(" Buffers in H/W Qs or NPEs : %u\n",
  2144. totalBuffers - numBuffersInSwQ);
  2145. #endif
  2146. printf("Rx QoS Discipline : %s\n",
  2147. (ixEthAccDataInfo.schDiscipline ==
  2148. FIFO_PRIORITY ) ? "Enabled" : "Disabled");
  2149. for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
  2150. {
  2151. printf("Tx QoS Discipline port %u : %s\n",
  2152. portId,
  2153. (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
  2154. FIFO_PRIORITY ) ? "Enabled" : "Disabled");
  2155. }
  2156. printf("\n");
  2157. }