clk_ccf.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <asm/clk.h>
  10. #include <dm/test.h>
  11. #include <dm/uclass.h>
  12. #include <linux/err.h>
  13. #include <test/test.h>
  14. #include <test/ut.h>
  15. #include <sandbox-clk.h>
  16. /* Tests for Common Clock Framework driver */
  17. static int dm_test_clk_ccf(struct unit_test_state *uts)
  18. {
  19. struct clk *clk, *pclk;
  20. struct udevice *dev;
  21. long long rate;
  22. int ret;
  23. #if CONFIG_IS_ENABLED(CLK_CCF)
  24. const char *clkname;
  25. int clkid, i;
  26. #endif
  27. /* Get the device using the clk device */
  28. ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
  29. /* Test for clk_get_by_id() */
  30. ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
  31. ut_assertok(ret);
  32. ut_asserteq_str("ecspi_root", clk->dev->name);
  33. ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  34. /* Test for clk_get_parent_rate() */
  35. ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
  36. ut_assertok(ret);
  37. ut_asserteq_str("ecspi1", clk->dev->name);
  38. ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  39. rate = clk_get_parent_rate(clk);
  40. ut_asserteq(rate, 20000000);
  41. /* test the gate of CCF */
  42. ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
  43. ut_assertok(ret);
  44. ut_asserteq_str("ecspi0", clk->dev->name);
  45. ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
  46. rate = clk_get_parent_rate(clk);
  47. ut_asserteq(rate, 20000000);
  48. /* Test the mux of CCF */
  49. ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  50. ut_assertok(ret);
  51. ut_asserteq_str("usdhc1_sel", clk->dev->name);
  52. ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
  53. rate = clk_get_parent_rate(clk);
  54. ut_asserteq(rate, 60000000);
  55. rate = clk_get_rate(clk);
  56. ut_asserteq(rate, 60000000);
  57. ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
  58. ut_assertok(ret);
  59. ret = clk_set_parent(clk, pclk);
  60. ut_assertok(ret);
  61. rate = clk_get_rate(clk);
  62. ut_asserteq(rate, 80000000);
  63. ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
  64. ut_assertok(ret);
  65. ut_asserteq_str("usdhc2_sel", clk->dev->name);
  66. ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
  67. rate = clk_get_parent_rate(clk);
  68. ut_asserteq(rate, 80000000);
  69. pclk = clk_get_parent(clk);
  70. ut_asserteq_str("pll3_80m", pclk->dev->name);
  71. ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
  72. rate = clk_get_rate(clk);
  73. ut_asserteq(rate, 80000000);
  74. ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
  75. ut_assertok(ret);
  76. ret = clk_set_parent(clk, pclk);
  77. ut_assertok(ret);
  78. rate = clk_get_rate(clk);
  79. ut_asserteq(rate, 60000000);
  80. /* Test the composite of CCF */
  81. ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
  82. ut_assertok(ret);
  83. ut_asserteq_str("i2c", clk->dev->name);
  84. ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
  85. rate = clk_get_rate(clk);
  86. ut_asserteq(rate, 60000000);
  87. #if CONFIG_IS_ENABLED(CLK_CCF)
  88. /* Test clk tree enable/disable */
  89. ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
  90. ut_assertok(ret);
  91. ut_asserteq_str("i2c_root", clk->dev->name);
  92. ret = clk_enable(clk);
  93. ut_assertok(ret);
  94. ret = sandbox_clk_enable_count(clk);
  95. ut_asserteq(ret, 1);
  96. ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
  97. ut_assertok(ret);
  98. ret = sandbox_clk_enable_count(pclk);
  99. ut_asserteq(ret, 1);
  100. ret = clk_disable(clk);
  101. ut_assertok(ret);
  102. ret = sandbox_clk_enable_count(clk);
  103. ut_asserteq(ret, 0);
  104. ret = sandbox_clk_enable_count(pclk);
  105. ut_asserteq(ret, 0);
  106. /* Test clock re-parenting. */
  107. ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
  108. ut_assertok(ret);
  109. ut_asserteq_str("usdhc1_sel", clk->dev->name);
  110. pclk = clk_get_parent(clk);
  111. ut_assertok_ptr(pclk);
  112. if (!strcmp(pclk->dev->name, "pll3_60m")) {
  113. clkname = "pll3_80m";
  114. clkid = SANDBOX_CLK_PLL3_80M;
  115. } else {
  116. clkname = "pll3_60m";
  117. clkid = SANDBOX_CLK_PLL3_60M;
  118. }
  119. ret = clk_get_by_id(clkid, &pclk);
  120. ut_assertok(ret);
  121. ret = clk_set_parent(clk, pclk);
  122. ut_assertok(ret);
  123. pclk = clk_get_parent(clk);
  124. ut_assertok_ptr(pclk);
  125. ut_asserteq_str(clkname, pclk->dev->name);
  126. /* Test disabling critical clock. */
  127. ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
  128. ut_assertok(ret);
  129. ut_asserteq_str("i2c_root", clk->dev->name);
  130. /* Disable it, if any. */
  131. ret = sandbox_clk_enable_count(clk);
  132. for (i = 0; i < ret; i++) {
  133. ret = clk_disable(clk);
  134. ut_assertok(ret);
  135. }
  136. ret = sandbox_clk_enable_count(clk);
  137. ut_asserteq(ret, 0);
  138. clk->flags = CLK_IS_CRITICAL;
  139. ret = clk_enable(clk);
  140. ut_assertok(ret);
  141. ret = clk_disable(clk);
  142. ut_assertok(ret);
  143. ret = sandbox_clk_enable_count(clk);
  144. ut_asserteq(ret, 1);
  145. clk->flags &= ~CLK_IS_CRITICAL;
  146. ret = clk_disable(clk);
  147. ut_assertok(ret);
  148. ret = sandbox_clk_enable_count(clk);
  149. ut_asserteq(ret, 0);
  150. #endif
  151. return 1;
  152. }
  153. DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);