analogbits-wrpll-cln28hpc.h 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018-2019 SiFive, Inc.
  4. * Wesley Terpstra
  5. * Paul Walmsley
  6. */
  7. #ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
  8. #define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
  9. #include <linux/types.h>
  10. /* DIVQ_VALUES: number of valid DIVQ values */
  11. #define DIVQ_VALUES 6
  12. /*
  13. * Bit definitions for struct wrpll_cfg.flags
  14. *
  15. * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
  16. * programmed to enter bypass
  17. * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
  18. * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
  19. * feedback mode
  20. * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
  21. * feedback mode (not yet supported by this driver)
  22. */
  23. #define WRPLL_FLAGS_BYPASS_SHIFT 0
  24. #define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
  25. #define WRPLL_FLAGS_RESET_SHIFT 1
  26. #define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
  27. #define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
  28. #define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
  29. #define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
  30. #define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
  31. /**
  32. * struct wrpll_cfg - WRPLL configuration values
  33. * @divr: reference divider value (6 bits), as presented to the PLL signals
  34. * @divf: feedback divider value (9 bits), as presented to the PLL signals
  35. * @divq: output divider value (3 bits), as presented to the PLL signals
  36. * @flags: PLL configuration flags. See above for more information
  37. * @range: PLL loop filter range. See below for more information
  38. * @output_rate_cache: cached output rates, swept across DIVQ
  39. * @parent_rate: PLL refclk rate for which values are valid
  40. * @max_r: maximum possible R divider value, given @parent_rate
  41. * @init_r: initial R divider value to start the search from
  42. *
  43. * @divr, @divq, @divq, @range represent what the PLL expects to see
  44. * on its input signals. Thus @divr and @divf are the actual divisors
  45. * minus one. @divq is a power-of-two divider; for example, 1 =
  46. * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
  47. *
  48. * When initially passing a struct wrpll_cfg record, the
  49. * record should be zero-initialized with the exception of the @flags
  50. * field. The only flag bits that need to be set are either
  51. * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
  52. */
  53. struct wrpll_cfg {
  54. u8 divr;
  55. u8 divq;
  56. u8 range;
  57. u8 flags;
  58. u16 divf;
  59. /* private: */
  60. u32 output_rate_cache[DIVQ_VALUES];
  61. unsigned long parent_rate;
  62. u8 max_r;
  63. u8 init_r;
  64. };
  65. int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
  66. unsigned long parent_rate);
  67. unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
  68. unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
  69. unsigned long parent_rate);
  70. #endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */