mchp-pit64b-timer.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * 64-bit Periodic Interval Timer driver
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <timer.h>
  13. #include <asm/io.h>
  14. #define MCHP_PIT64B_CR 0x00 /* Control Register */
  15. #define MCHP_PIT64B_CR_START BIT(0)
  16. #define MCHP_PIT64B_CR_SWRST BIT(8)
  17. #define MCHP_PIT64B_MR 0x04 /* Mode Register */
  18. #define MCHP_PIT64B_MR_CONT BIT(0)
  19. #define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
  20. #define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
  21. #define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
  22. #define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
  23. struct mchp_pit64b_priv {
  24. void __iomem *base;
  25. };
  26. static int mchp_pit64b_get_count(struct udevice *dev, u64 *count)
  27. {
  28. struct mchp_pit64b_priv *priv = dev_get_priv(dev);
  29. u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
  30. u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
  31. *count = ((u64)msb << 32) | lsb;
  32. return 0;
  33. }
  34. static int mchp_pit64b_probe(struct udevice *dev)
  35. {
  36. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  37. struct mchp_pit64b_priv *priv = dev_get_priv(dev);
  38. struct clk clk;
  39. ulong rate;
  40. int ret;
  41. priv->base = dev_read_addr_ptr(dev);
  42. if (IS_ERR(priv->base))
  43. return PTR_ERR(priv->base);
  44. ret = clk_get_by_index(dev, 0, &clk);
  45. if (ret)
  46. return ret;
  47. ret = clk_enable(&clk);
  48. if (ret)
  49. return ret;
  50. rate = clk_get_rate(&clk);
  51. if (!rate) {
  52. clk_disable(&clk);
  53. return -ENOTSUPP;
  54. }
  55. /* Reset the timer in case it was used by previous bootloaders. */
  56. writel(MCHP_PIT64B_CR_SWRST, priv->base + MCHP_PIT64B_CR);
  57. /*
  58. * Use highest prescaller (for a peripheral clock running at 200MHz
  59. * this will lead to the timer running at 12.5MHz) and continuous mode.
  60. */
  61. writel((15 << 8) | MCHP_PIT64B_MR_CONT, priv->base + MCHP_PIT64B_MR);
  62. uc_priv->clock_rate = rate / 16;
  63. /*
  64. * Simulate free running counter by setting max values to period
  65. * registers.
  66. */
  67. writel(~0UL, priv->base + MCHP_PIT64B_MSB_PR);
  68. writel(~0UL, priv->base + MCHP_PIT64B_LSB_PR);
  69. /* Start the timer. */
  70. writel(MCHP_PIT64B_CR_START, priv->base + MCHP_PIT64B_CR);
  71. return 0;
  72. }
  73. static const struct timer_ops mchp_pit64b_ops = {
  74. .get_count = mchp_pit64b_get_count,
  75. };
  76. static const struct udevice_id mchp_pit64b_ids[] = {
  77. { .compatible = "microchip,sam9x60-pit64b", },
  78. { .compatible = "microchip,sama7g5-pit64b", },
  79. { }
  80. };
  81. U_BOOT_DRIVER(mchp_pit64b) = {
  82. .name = "mchp-pit64b",
  83. .id = UCLASS_TIMER,
  84. .of_match = mchp_pit64b_ids,
  85. .priv_auto_alloc_size = sizeof(struct mchp_pit64b_priv),
  86. .probe = mchp_pit64b_probe,
  87. .ops = &mchp_pit64b_ops,
  88. .flags = DM_FLAG_PRE_RELOC,
  89. };