pinctrl_pic32.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Pinctrl driver for Microchip PIC32 SoCs
  4. * Copyright (c) 2015 Microchip Technology Inc.
  5. * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <dm/pinctrl.h>
  13. #include <linux/bitops.h>
  14. #include <mach/pic32.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* PIC32 has 10 peripheral ports with 16 pins each.
  17. * Ports are marked PORTA-PORTK or PORT0-PORT9.
  18. */
  19. enum {
  20. PIC32_PORT_A = 0,
  21. PIC32_PORT_B = 1,
  22. PIC32_PORT_C = 2,
  23. PIC32_PORT_D = 3,
  24. PIC32_PORT_E = 4,
  25. PIC32_PORT_F = 5,
  26. PIC32_PORT_G = 6,
  27. PIC32_PORT_H = 7,
  28. PIC32_PORT_J = 8, /* no PORT_I */
  29. PIC32_PORT_K = 9,
  30. PIC32_PINS_PER_PORT = 16,
  31. };
  32. #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
  33. #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
  34. /* pin configuration descriptor */
  35. struct pic32_pin_config {
  36. u16 port; /* port number */
  37. u16 pin; /* pin number in the port */
  38. u32 config; /* one of PIN_CONFIG_* */
  39. };
  40. #define PIN_CONFIG(_prt, _pin, _cfg) \
  41. {.port = (_prt), .pin = (_pin), .config = (_cfg), }
  42. /* In PIC32 muxing is performed at pin-level through two
  43. * different set of registers - one set for input functions,
  44. * and other for output functions.
  45. * Pin configuration is handled through port register.
  46. */
  47. /* Port control registers */
  48. struct pic32_reg_port {
  49. struct pic32_reg_atomic ansel;
  50. struct pic32_reg_atomic tris;
  51. struct pic32_reg_atomic port;
  52. struct pic32_reg_atomic lat;
  53. struct pic32_reg_atomic odc;
  54. struct pic32_reg_atomic cnpu;
  55. struct pic32_reg_atomic cnpd;
  56. struct pic32_reg_atomic cncon;
  57. struct pic32_reg_atomic unused[8];
  58. };
  59. /* Input function mux registers */
  60. struct pic32_reg_in_mux {
  61. u32 unused0;
  62. u32 int1[4];
  63. u32 unused1;
  64. u32 t2ck[8];
  65. u32 ic1[9];
  66. u32 unused2;
  67. u32 ocfar;
  68. u32 unused3;
  69. u32 u1rx;
  70. u32 u1cts;
  71. u32 u2rx;
  72. u32 u2cts;
  73. u32 u3rx;
  74. u32 u3cts;
  75. u32 u4rx;
  76. u32 u4cts;
  77. u32 u5rx;
  78. u32 u5cts;
  79. u32 u6rx;
  80. u32 u6cts;
  81. u32 unused4;
  82. u32 sdi1;
  83. u32 ss1;
  84. u32 unused5;
  85. u32 sdi2;
  86. u32 ss2;
  87. u32 unused6;
  88. u32 sdi3;
  89. u32 ss3;
  90. u32 unused7;
  91. u32 sdi4;
  92. u32 ss4;
  93. u32 unused8;
  94. u32 sdi5;
  95. u32 ss5;
  96. u32 unused9;
  97. u32 sdi6;
  98. u32 ss6;
  99. u32 c1rx;
  100. u32 c2rx;
  101. u32 refclki1;
  102. u32 refclki2;
  103. u32 refclki3;
  104. u32 refclki4;
  105. };
  106. /* output mux register offset */
  107. #define PPS_OUT(__port, __pin) \
  108. (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
  109. struct pic32_pinctrl_priv {
  110. struct pic32_reg_in_mux *mux_in; /* mux input function */
  111. struct pic32_reg_port *pinconf; /* pin configuration*/
  112. void __iomem *mux_out; /* mux output function */
  113. };
  114. enum {
  115. PERIPH_ID_UART1,
  116. PERIPH_ID_UART2,
  117. PERIPH_ID_ETH,
  118. PERIPH_ID_USB,
  119. PERIPH_ID_SDHCI,
  120. PERIPH_ID_I2C1,
  121. PERIPH_ID_I2C2,
  122. PERIPH_ID_SPI1,
  123. PERIPH_ID_SPI2,
  124. PERIPH_ID_SQI,
  125. };
  126. static int pic32_pinconfig_one(struct pic32_pinctrl_priv *priv,
  127. u32 port_nr, u32 pin, u32 param)
  128. {
  129. struct pic32_reg_port *port;
  130. port = &priv->pinconf[port_nr];
  131. switch (param) {
  132. case PIN_CONFIG_PIC32_DIGITAL:
  133. writel(BIT(pin), &port->ansel.clr);
  134. break;
  135. case PIN_CONFIG_PIC32_ANALOG:
  136. writel(BIT(pin), &port->ansel.set);
  137. break;
  138. case PIN_CONFIG_INPUT_ENABLE:
  139. writel(BIT(pin), &port->tris.set);
  140. break;
  141. case PIN_CONFIG_OUTPUT:
  142. writel(BIT(pin), &port->tris.clr);
  143. break;
  144. case PIN_CONFIG_BIAS_PULL_UP:
  145. writel(BIT(pin), &port->cnpu.set);
  146. break;
  147. case PIN_CONFIG_BIAS_PULL_DOWN:
  148. writel(BIT(pin), &port->cnpd.set);
  149. break;
  150. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  151. writel(BIT(pin), &port->odc.set);
  152. break;
  153. default:
  154. break;
  155. }
  156. return 0;
  157. }
  158. static int pic32_pinconfig_set(struct pic32_pinctrl_priv *priv,
  159. const struct pic32_pin_config *list, int count)
  160. {
  161. int i;
  162. for (i = 0 ; i < count; i++)
  163. pic32_pinconfig_one(priv, list[i].port,
  164. list[i].pin, list[i].config);
  165. return 0;
  166. }
  167. static void pic32_eth_pin_config(struct udevice *dev)
  168. {
  169. struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
  170. const struct pic32_pin_config configs[] = {
  171. /* EMDC - D11 */
  172. PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_PIC32_DIGITAL),
  173. PIN_CONFIG(PIC32_PORT_D, 11, PIN_CONFIG_OUTPUT),
  174. /* ETXEN */
  175. PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_PIC32_DIGITAL),
  176. PIN_CONFIG(PIC32_PORT_D, 6, PIN_CONFIG_OUTPUT),
  177. /* ECRSDV */
  178. PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_PIC32_DIGITAL),
  179. PIN_CONFIG(PIC32_PORT_H, 13, PIN_CONFIG_INPUT_ENABLE),
  180. /* ERXD0 */
  181. PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_PIC32_DIGITAL),
  182. PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_INPUT_ENABLE),
  183. PIN_CONFIG(PIC32_PORT_H, 8, PIN_CONFIG_BIAS_PULL_DOWN),
  184. /* ERXD1 */
  185. PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_PIC32_DIGITAL),
  186. PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_INPUT_ENABLE),
  187. PIN_CONFIG(PIC32_PORT_H, 5, PIN_CONFIG_BIAS_PULL_DOWN),
  188. /* EREFCLK */
  189. PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_PIC32_DIGITAL),
  190. PIN_CONFIG(PIC32_PORT_J, 11, PIN_CONFIG_INPUT_ENABLE),
  191. /* ETXD1 */
  192. PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_PIC32_DIGITAL),
  193. PIN_CONFIG(PIC32_PORT_J, 9, PIN_CONFIG_OUTPUT),
  194. /* ETXD0 */
  195. PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_PIC32_DIGITAL),
  196. PIN_CONFIG(PIC32_PORT_J, 8, PIN_CONFIG_OUTPUT),
  197. /* EMDIO */
  198. PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_PIC32_DIGITAL),
  199. PIN_CONFIG(PIC32_PORT_J, 1, PIN_CONFIG_INPUT_ENABLE),
  200. /* ERXERR */
  201. PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_PIC32_DIGITAL),
  202. PIN_CONFIG(PIC32_PORT_F, 3, PIN_CONFIG_INPUT_ENABLE),
  203. };
  204. pic32_pinconfig_set(priv, configs, ARRAY_SIZE(configs));
  205. }
  206. static int pic32_pinctrl_request(struct udevice *dev, int func, int flags)
  207. {
  208. struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
  209. switch (func) {
  210. case PERIPH_ID_UART2:
  211. /* PPS for U2 RX/TX */
  212. writel(0x02, priv->mux_out + PPS_OUT(PIC32_PORT_G, 9));
  213. writel(0x05, &priv->mux_in->u2rx); /* B0 */
  214. /* set digital mode */
  215. pic32_pinconfig_one(priv, PIC32_PORT_G, 9,
  216. PIN_CONFIG_PIC32_DIGITAL);
  217. pic32_pinconfig_one(priv, PIC32_PORT_B, 0,
  218. PIN_CONFIG_PIC32_DIGITAL);
  219. break;
  220. case PERIPH_ID_ETH:
  221. pic32_eth_pin_config(dev);
  222. break;
  223. default:
  224. debug("%s: unknown-unhandled case\n", __func__);
  225. break;
  226. }
  227. return 0;
  228. }
  229. static int pic32_pinctrl_get_periph_id(struct udevice *dev,
  230. struct udevice *periph)
  231. {
  232. int ret;
  233. u32 cell[2];
  234. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
  235. "interrupts", cell, ARRAY_SIZE(cell));
  236. if (ret < 0)
  237. return -EINVAL;
  238. /* interrupt number */
  239. switch (cell[0]) {
  240. case 112 ... 114:
  241. return PERIPH_ID_UART1;
  242. case 145 ... 147:
  243. return PERIPH_ID_UART2;
  244. case 109 ... 111:
  245. return PERIPH_ID_SPI1;
  246. case 142 ... 144:
  247. return PERIPH_ID_SPI2;
  248. case 115 ... 117:
  249. return PERIPH_ID_I2C1;
  250. case 148 ... 150:
  251. return PERIPH_ID_I2C2;
  252. case 132 ... 133:
  253. return PERIPH_ID_USB;
  254. case 169:
  255. return PERIPH_ID_SQI;
  256. case 191:
  257. return PERIPH_ID_SDHCI;
  258. case 153:
  259. return PERIPH_ID_ETH;
  260. default:
  261. break;
  262. }
  263. return -ENOENT;
  264. }
  265. static int pic32_pinctrl_set_state_simple(struct udevice *dev,
  266. struct udevice *periph)
  267. {
  268. int func;
  269. debug("%s: periph %s\n", __func__, periph->name);
  270. func = pic32_pinctrl_get_periph_id(dev, periph);
  271. if (func < 0)
  272. return func;
  273. return pic32_pinctrl_request(dev, func, 0);
  274. }
  275. static struct pinctrl_ops pic32_pinctrl_ops = {
  276. .set_state_simple = pic32_pinctrl_set_state_simple,
  277. .request = pic32_pinctrl_request,
  278. .get_periph_id = pic32_pinctrl_get_periph_id,
  279. };
  280. static int pic32_pinctrl_probe(struct udevice *dev)
  281. {
  282. struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
  283. struct fdt_resource res;
  284. void *fdt = (void *)gd->fdt_blob;
  285. int node = dev_of_offset(dev);
  286. int ret;
  287. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  288. "ppsin", &res);
  289. if (ret < 0) {
  290. printf("pinctrl: resource \"ppsin\" not found\n");
  291. return ret;
  292. }
  293. priv->mux_in = ioremap(res.start, fdt_resource_size(&res));
  294. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  295. "ppsout", &res);
  296. if (ret < 0) {
  297. printf("pinctrl: resource \"ppsout\" not found\n");
  298. return ret;
  299. }
  300. priv->mux_out = ioremap(res.start, fdt_resource_size(&res));
  301. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  302. "port", &res);
  303. if (ret < 0) {
  304. printf("pinctrl: resource \"port\" not found\n");
  305. return ret;
  306. }
  307. priv->pinconf = ioremap(res.start, fdt_resource_size(&res));
  308. return 0;
  309. }
  310. static const struct udevice_id pic32_pinctrl_ids[] = {
  311. { .compatible = "microchip,pic32mzda-pinctrl" },
  312. { }
  313. };
  314. U_BOOT_DRIVER(pinctrl_pic32) = {
  315. .name = "pinctrl_pic32",
  316. .id = UCLASS_PINCTRL,
  317. .of_match = pic32_pinctrl_ids,
  318. .ops = &pic32_pinctrl_ops,
  319. .probe = pic32_pinctrl_probe,
  320. .bind = dm_scan_fdt_dev,
  321. .priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv),
  322. };