pinctrl-at91-pio4.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel PIO4 pinctrl driver
  4. *
  5. * Copyright (C) 2016 Atmel Corporation
  6. * Wenyou.Yang <wenyou.yang@atmel.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/pinctrl.h>
  11. #include <linux/bitops.h>
  12. #include <linux/io.h>
  13. #include <linux/err.h>
  14. #include <mach/atmel_pio4.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /*
  17. * Warning:
  18. * In order to not introduce confusion between Atmel PIO groups and pinctrl
  19. * framework groups, Atmel PIO groups will be called banks.
  20. */
  21. struct atmel_pio4_platdata {
  22. struct atmel_pio4_port *reg_base;
  23. };
  24. static const struct pinconf_param conf_params[] = {
  25. { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
  26. { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
  27. { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
  28. { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
  29. { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
  30. { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
  31. { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
  32. };
  33. static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
  34. {
  35. const struct pinconf_param *params;
  36. u32 param, arg, conf = 0;
  37. u32 i;
  38. for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
  39. params = &conf_params[i];
  40. if (!fdt_get_property(blob, node, params->property, NULL))
  41. continue;
  42. param = params->param;
  43. arg = params->default_value;
  44. switch (param) {
  45. case PIN_CONFIG_BIAS_DISABLE:
  46. conf &= (~ATMEL_PIO_PUEN_MASK);
  47. conf &= (~ATMEL_PIO_PDEN_MASK);
  48. break;
  49. case PIN_CONFIG_BIAS_PULL_UP:
  50. conf |= ATMEL_PIO_PUEN_MASK;
  51. break;
  52. case PIN_CONFIG_BIAS_PULL_DOWN:
  53. conf |= ATMEL_PIO_PDEN_MASK;
  54. break;
  55. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  56. if (arg == 0)
  57. conf &= (~ATMEL_PIO_OPD_MASK);
  58. else
  59. conf |= ATMEL_PIO_OPD_MASK;
  60. break;
  61. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  62. if (arg == 0)
  63. conf |= ATMEL_PIO_SCHMITT_MASK;
  64. else
  65. conf &= (~ATMEL_PIO_SCHMITT_MASK);
  66. break;
  67. case PIN_CONFIG_INPUT_DEBOUNCE:
  68. if (arg == 0) {
  69. conf &= (~ATMEL_PIO_IFEN_MASK);
  70. conf &= (~ATMEL_PIO_IFSCEN_MASK);
  71. } else {
  72. conf |= ATMEL_PIO_IFEN_MASK;
  73. conf |= ATMEL_PIO_IFSCEN_MASK;
  74. }
  75. break;
  76. default:
  77. printf("%s: Unsupported configuration parameter: %u\n",
  78. __func__, param);
  79. break;
  80. }
  81. }
  82. return conf;
  83. }
  84. static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
  85. u32 bank)
  86. {
  87. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  88. struct atmel_pio4_port *bank_base =
  89. (struct atmel_pio4_port *)((u32)plat->reg_base +
  90. ATMEL_PIO_BANK_OFFSET * bank);
  91. return bank_base;
  92. }
  93. #define MAX_PINMUX_ENTRIES 40
  94. static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  95. {
  96. struct atmel_pio4_port *bank_base;
  97. const void *blob = gd->fdt_blob;
  98. int node = dev_of_offset(config);
  99. u32 offset, func, bank, line;
  100. u32 cells[MAX_PINMUX_ENTRIES];
  101. u32 i, conf;
  102. int count;
  103. conf = atmel_pinctrl_get_pinconf(blob, node);
  104. count = fdtdec_get_int_array_count(blob, node, "pinmux",
  105. cells, ARRAY_SIZE(cells));
  106. if (count < 0) {
  107. printf("%s: bad pinmux array %d\n", __func__, count);
  108. return -EINVAL;
  109. }
  110. if (count > MAX_PINMUX_ENTRIES) {
  111. printf("%s: unsupported pinmux array count %d\n",
  112. __func__, count);
  113. return -EINVAL;
  114. }
  115. for (i = 0 ; i < count; i++) {
  116. offset = ATMEL_GET_PIN_NO(cells[i]);
  117. func = ATMEL_GET_PIN_FUNC(cells[i]);
  118. bank = ATMEL_PIO_BANK(offset);
  119. line = ATMEL_PIO_LINE(offset);
  120. bank_base = atmel_pio4_bank_base(dev, bank);
  121. writel(BIT(line), &bank_base->mskr);
  122. conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
  123. conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
  124. writel(conf, &bank_base->cfgr);
  125. }
  126. return 0;
  127. }
  128. const struct pinctrl_ops atmel_pinctrl_ops = {
  129. .set_state = atmel_pinctrl_set_state,
  130. };
  131. static int atmel_pinctrl_probe(struct udevice *dev)
  132. {
  133. struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
  134. fdt_addr_t addr_base;
  135. dev = dev_get_parent(dev);
  136. addr_base = dev_read_addr(dev);
  137. if (addr_base == FDT_ADDR_T_NONE)
  138. return -EINVAL;
  139. plat->reg_base = (struct atmel_pio4_port *)addr_base;
  140. return 0;
  141. }
  142. static const struct udevice_id atmel_pinctrl_match[] = {
  143. { .compatible = "atmel,sama5d2-pinctrl" },
  144. { .compatible = "microchip,sama7g5-pinctrl" },
  145. {}
  146. };
  147. U_BOOT_DRIVER(atmel_pinctrl) = {
  148. .name = "pinctrl_atmel_pio4",
  149. .id = UCLASS_PINCTRL,
  150. .of_match = atmel_pinctrl_match,
  151. .probe = atmel_pinctrl_probe,
  152. .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
  153. .ops = &atmel_pinctrl_ops,
  154. };