sdhci.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <mmc.h>
  16. #include <sdhci.h>
  17. #include <asm/cache.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <linux/dma-mapping.h>
  21. #include <phys2bus.h>
  22. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  23. {
  24. unsigned long timeout;
  25. /* Wait max 100 ms */
  26. timeout = 100;
  27. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  28. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  29. if (timeout == 0) {
  30. printf("%s: Reset 0x%x never completed.\n",
  31. __func__, (int)mask);
  32. return;
  33. }
  34. timeout--;
  35. udelay(1000);
  36. }
  37. }
  38. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  39. {
  40. int i;
  41. if (cmd->resp_type & MMC_RSP_136) {
  42. /* CRC is stripped so we need to do some shifting. */
  43. for (i = 0; i < 4; i++) {
  44. cmd->response[i] = sdhci_readl(host,
  45. SDHCI_RESPONSE + (3-i)*4) << 8;
  46. if (i != 3)
  47. cmd->response[i] |= sdhci_readb(host,
  48. SDHCI_RESPONSE + (3-i)*4-1);
  49. }
  50. } else {
  51. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  52. }
  53. }
  54. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  55. {
  56. int i;
  57. char *offs;
  58. for (i = 0; i < data->blocksize; i += 4) {
  59. offs = data->dest + i;
  60. if (data->flags == MMC_DATA_READ)
  61. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  62. else
  63. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  64. }
  65. }
  66. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  67. static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  68. u16 len, bool end)
  69. {
  70. struct sdhci_adma_desc *desc;
  71. u8 attr;
  72. desc = &host->adma_desc_table[host->desc_slot];
  73. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  74. if (!end)
  75. host->desc_slot++;
  76. else
  77. attr |= ADMA_DESC_ATTR_END;
  78. desc->attr = attr;
  79. desc->len = len;
  80. desc->reserved = 0;
  81. desc->addr_lo = lower_32_bits(dma_addr);
  82. #ifdef CONFIG_DMA_ADDR_T_64BIT
  83. desc->addr_hi = upper_32_bits(dma_addr);
  84. #endif
  85. }
  86. static void sdhci_prepare_adma_table(struct sdhci_host *host,
  87. struct mmc_data *data)
  88. {
  89. uint trans_bytes = data->blocksize * data->blocks;
  90. uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  91. int i = desc_count;
  92. dma_addr_t dma_addr = host->start_addr;
  93. host->desc_slot = 0;
  94. while (--i) {
  95. sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
  96. dma_addr += ADMA_MAX_LEN;
  97. trans_bytes -= ADMA_MAX_LEN;
  98. }
  99. sdhci_adma_desc(host, dma_addr, trans_bytes, true);
  100. flush_cache((dma_addr_t)host->adma_desc_table,
  101. ROUND(desc_count * sizeof(struct sdhci_adma_desc),
  102. ARCH_DMA_MINALIGN));
  103. }
  104. #elif defined(CONFIG_MMC_SDHCI_SDMA)
  105. static void sdhci_prepare_adma_table(struct sdhci_host *host,
  106. struct mmc_data *data)
  107. {}
  108. #endif
  109. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  110. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  111. int *is_aligned, int trans_bytes)
  112. {
  113. unsigned char ctrl;
  114. void *buf;
  115. if (data->flags == MMC_DATA_READ)
  116. buf = data->dest;
  117. else
  118. buf = (void *)data->src;
  119. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  120. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  121. if (host->flags & USE_ADMA64)
  122. ctrl |= SDHCI_CTRL_ADMA64;
  123. else if (host->flags & USE_ADMA)
  124. ctrl |= SDHCI_CTRL_ADMA32;
  125. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  126. if (host->flags & USE_SDMA &&
  127. (host->force_align_buffer ||
  128. (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  129. ((unsigned long)buf & 0x7) != 0x0))) {
  130. *is_aligned = 0;
  131. if (data->flags != MMC_DATA_READ)
  132. memcpy(host->align_buffer, buf, trans_bytes);
  133. buf = host->align_buffer;
  134. }
  135. host->start_addr = dma_map_single(buf, trans_bytes,
  136. mmc_get_dma_dir(data));
  137. if (host->flags & USE_SDMA) {
  138. sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
  139. SDHCI_DMA_ADDRESS);
  140. } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
  141. sdhci_prepare_adma_table(host, data);
  142. sdhci_writel(host, lower_32_bits(host->adma_addr),
  143. SDHCI_ADMA_ADDRESS);
  144. if (host->flags & USE_ADMA64)
  145. sdhci_writel(host, upper_32_bits(host->adma_addr),
  146. SDHCI_ADMA_ADDRESS_HI);
  147. }
  148. }
  149. #else
  150. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  151. int *is_aligned, int trans_bytes)
  152. {}
  153. #endif
  154. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
  155. {
  156. dma_addr_t start_addr = host->start_addr;
  157. unsigned int stat, rdy, mask, timeout, block = 0;
  158. bool transfer_done = false;
  159. timeout = 1000000;
  160. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  161. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  162. do {
  163. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  164. if (stat & SDHCI_INT_ERROR) {
  165. pr_debug("%s: Error detected in status(0x%X)!\n",
  166. __func__, stat);
  167. return -EIO;
  168. }
  169. if (!transfer_done && (stat & rdy)) {
  170. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  171. continue;
  172. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  173. sdhci_transfer_pio(host, data);
  174. data->dest += data->blocksize;
  175. if (++block >= data->blocks) {
  176. /* Keep looping until the SDHCI_INT_DATA_END is
  177. * cleared, even if we finished sending all the
  178. * blocks.
  179. */
  180. transfer_done = true;
  181. continue;
  182. }
  183. }
  184. if ((host->flags & USE_DMA) && !transfer_done &&
  185. (stat & SDHCI_INT_DMA_END)) {
  186. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  187. if (host->flags & USE_SDMA) {
  188. start_addr &=
  189. ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  190. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  191. sdhci_writel(host, phys_to_bus((ulong)start_addr),
  192. SDHCI_DMA_ADDRESS);
  193. }
  194. }
  195. if (timeout-- > 0)
  196. udelay(10);
  197. else {
  198. printf("%s: Transfer data timeout\n", __func__);
  199. return -ETIMEDOUT;
  200. }
  201. } while (!(stat & SDHCI_INT_DATA_END));
  202. dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
  203. mmc_get_dma_dir(data));
  204. return 0;
  205. }
  206. /*
  207. * No command will be sent by driver if card is busy, so driver must wait
  208. * for card ready state.
  209. * Every time when card is busy after timeout then (last) timeout value will be
  210. * increased twice but only if it doesn't exceed global defined maximum.
  211. * Each function call will use last timeout value.
  212. */
  213. #define SDHCI_CMD_MAX_TIMEOUT 3200
  214. #define SDHCI_CMD_DEFAULT_TIMEOUT 100
  215. #define SDHCI_READ_STATUS_TIMEOUT 1000
  216. #ifdef CONFIG_DM_MMC
  217. static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
  218. struct mmc_data *data)
  219. {
  220. struct mmc *mmc = mmc_get_mmc_dev(dev);
  221. #else
  222. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  223. struct mmc_data *data)
  224. {
  225. #endif
  226. struct sdhci_host *host = mmc->priv;
  227. unsigned int stat = 0;
  228. int ret = 0;
  229. int trans_bytes = 0, is_aligned = 1;
  230. u32 mask, flags, mode;
  231. unsigned int time = 0;
  232. int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
  233. ulong start = get_timer(0);
  234. host->start_addr = 0;
  235. /* Timeout unit - ms */
  236. static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
  237. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  238. /* We shouldn't wait for data inihibit for stop commands, even
  239. though they might use busy signaling */
  240. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  241. ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  242. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
  243. mask &= ~SDHCI_DATA_INHIBIT;
  244. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  245. if (time >= cmd_timeout) {
  246. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  247. if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
  248. cmd_timeout += cmd_timeout;
  249. printf("timeout increasing to: %u ms.\n",
  250. cmd_timeout);
  251. } else {
  252. puts("timeout.\n");
  253. return -ECOMM;
  254. }
  255. }
  256. time++;
  257. udelay(1000);
  258. }
  259. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  260. mask = SDHCI_INT_RESPONSE;
  261. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  262. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
  263. mask = SDHCI_INT_DATA_AVAIL;
  264. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  265. flags = SDHCI_CMD_RESP_NONE;
  266. else if (cmd->resp_type & MMC_RSP_136)
  267. flags = SDHCI_CMD_RESP_LONG;
  268. else if (cmd->resp_type & MMC_RSP_BUSY) {
  269. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  270. if (data)
  271. mask |= SDHCI_INT_DATA_END;
  272. } else
  273. flags = SDHCI_CMD_RESP_SHORT;
  274. if (cmd->resp_type & MMC_RSP_CRC)
  275. flags |= SDHCI_CMD_CRC;
  276. if (cmd->resp_type & MMC_RSP_OPCODE)
  277. flags |= SDHCI_CMD_INDEX;
  278. if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  279. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  280. flags |= SDHCI_CMD_DATA;
  281. /* Set Transfer mode regarding to data flag */
  282. if (data) {
  283. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  284. mode = SDHCI_TRNS_BLK_CNT_EN;
  285. trans_bytes = data->blocks * data->blocksize;
  286. if (data->blocks > 1)
  287. mode |= SDHCI_TRNS_MULTI;
  288. if (data->flags == MMC_DATA_READ)
  289. mode |= SDHCI_TRNS_READ;
  290. if (host->flags & USE_DMA) {
  291. mode |= SDHCI_TRNS_DMA;
  292. sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
  293. }
  294. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  295. data->blocksize),
  296. SDHCI_BLOCK_SIZE);
  297. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  298. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  299. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  300. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  301. }
  302. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  303. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  304. start = get_timer(0);
  305. do {
  306. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  307. if (stat & SDHCI_INT_ERROR)
  308. break;
  309. if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
  310. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
  311. return 0;
  312. } else {
  313. printf("%s: Timeout for status update!\n",
  314. __func__);
  315. return -ETIMEDOUT;
  316. }
  317. }
  318. } while ((stat & mask) != mask);
  319. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  320. sdhci_cmd_done(host, cmd);
  321. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  322. } else
  323. ret = -1;
  324. if (!ret && data)
  325. ret = sdhci_transfer_data(host, data);
  326. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  327. udelay(1000);
  328. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  329. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  330. if (!ret) {
  331. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  332. !is_aligned && (data->flags == MMC_DATA_READ))
  333. memcpy(data->dest, host->align_buffer, trans_bytes);
  334. return 0;
  335. }
  336. sdhci_reset(host, SDHCI_RESET_CMD);
  337. sdhci_reset(host, SDHCI_RESET_DATA);
  338. if (stat & SDHCI_INT_TIMEOUT)
  339. return -ETIMEDOUT;
  340. else
  341. return -ECOMM;
  342. }
  343. #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  344. static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  345. {
  346. int err;
  347. struct mmc *mmc = mmc_get_mmc_dev(dev);
  348. struct sdhci_host *host = mmc->priv;
  349. debug("%s\n", __func__);
  350. if (host->ops && host->ops->platform_execute_tuning) {
  351. err = host->ops->platform_execute_tuning(mmc, opcode);
  352. if (err)
  353. return err;
  354. return 0;
  355. }
  356. return 0;
  357. }
  358. #endif
  359. int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  360. {
  361. struct sdhci_host *host = mmc->priv;
  362. unsigned int div, clk = 0, timeout;
  363. /* Wait max 20 ms */
  364. timeout = 200;
  365. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  366. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  367. if (timeout == 0) {
  368. printf("%s: Timeout to wait cmd & data inhibit\n",
  369. __func__);
  370. return -EBUSY;
  371. }
  372. timeout--;
  373. udelay(100);
  374. }
  375. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  376. if (clock == 0)
  377. return 0;
  378. if (host->ops && host->ops->set_delay)
  379. host->ops->set_delay(host);
  380. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  381. /*
  382. * Check if the Host Controller supports Programmable Clock
  383. * Mode.
  384. */
  385. if (host->clk_mul) {
  386. for (div = 1; div <= 1024; div++) {
  387. if ((host->max_clk / div) <= clock)
  388. break;
  389. }
  390. /*
  391. * Set Programmable Clock Mode in the Clock
  392. * Control register.
  393. */
  394. clk = SDHCI_PROG_CLOCK_MODE;
  395. div--;
  396. } else {
  397. /* Version 3.00 divisors must be a multiple of 2. */
  398. if (host->max_clk <= clock) {
  399. div = 1;
  400. } else {
  401. for (div = 2;
  402. div < SDHCI_MAX_DIV_SPEC_300;
  403. div += 2) {
  404. if ((host->max_clk / div) <= clock)
  405. break;
  406. }
  407. }
  408. div >>= 1;
  409. }
  410. } else {
  411. /* Version 2.00 divisors must be a power of 2. */
  412. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  413. if ((host->max_clk / div) <= clock)
  414. break;
  415. }
  416. div >>= 1;
  417. }
  418. if (host->ops && host->ops->set_clock)
  419. host->ops->set_clock(host, div);
  420. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  421. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  422. << SDHCI_DIVIDER_HI_SHIFT;
  423. clk |= SDHCI_CLOCK_INT_EN;
  424. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  425. /* Wait max 20 ms */
  426. timeout = 20;
  427. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  428. & SDHCI_CLOCK_INT_STABLE)) {
  429. if (timeout == 0) {
  430. printf("%s: Internal clock never stabilised.\n",
  431. __func__);
  432. return -EBUSY;
  433. }
  434. timeout--;
  435. udelay(1000);
  436. }
  437. clk |= SDHCI_CLOCK_CARD_EN;
  438. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  439. return 0;
  440. }
  441. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  442. {
  443. u8 pwr = 0;
  444. if (power != (unsigned short)-1) {
  445. switch (1 << power) {
  446. case MMC_VDD_165_195:
  447. pwr = SDHCI_POWER_180;
  448. break;
  449. case MMC_VDD_29_30:
  450. case MMC_VDD_30_31:
  451. pwr = SDHCI_POWER_300;
  452. break;
  453. case MMC_VDD_32_33:
  454. case MMC_VDD_33_34:
  455. pwr = SDHCI_POWER_330;
  456. break;
  457. }
  458. }
  459. if (pwr == 0) {
  460. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  461. return;
  462. }
  463. pwr |= SDHCI_POWER_ON;
  464. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  465. }
  466. void sdhci_set_uhs_timing(struct sdhci_host *host)
  467. {
  468. struct mmc *mmc = host->mmc;
  469. u32 reg;
  470. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  471. reg &= ~SDHCI_CTRL_UHS_MASK;
  472. switch (mmc->selected_mode) {
  473. case UHS_SDR50:
  474. case MMC_HS_52:
  475. reg |= SDHCI_CTRL_UHS_SDR50;
  476. break;
  477. case UHS_DDR50:
  478. case MMC_DDR_52:
  479. reg |= SDHCI_CTRL_UHS_DDR50;
  480. break;
  481. case UHS_SDR104:
  482. case MMC_HS_200:
  483. reg |= SDHCI_CTRL_UHS_SDR104;
  484. break;
  485. default:
  486. reg |= SDHCI_CTRL_UHS_SDR12;
  487. }
  488. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  489. }
  490. #ifdef CONFIG_DM_MMC
  491. static int sdhci_set_ios(struct udevice *dev)
  492. {
  493. struct mmc *mmc = mmc_get_mmc_dev(dev);
  494. #else
  495. static int sdhci_set_ios(struct mmc *mmc)
  496. {
  497. #endif
  498. u32 ctrl;
  499. struct sdhci_host *host = mmc->priv;
  500. bool no_hispd_bit = false;
  501. if (host->ops && host->ops->set_control_reg)
  502. host->ops->set_control_reg(host);
  503. if (mmc->clock != host->clock)
  504. sdhci_set_clock(mmc, mmc->clock);
  505. if (mmc->clk_disable)
  506. sdhci_set_clock(mmc, 0);
  507. /* Set bus width */
  508. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  509. if (mmc->bus_width == 8) {
  510. ctrl &= ~SDHCI_CTRL_4BITBUS;
  511. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  512. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  513. ctrl |= SDHCI_CTRL_8BITBUS;
  514. } else {
  515. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  516. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  517. ctrl &= ~SDHCI_CTRL_8BITBUS;
  518. if (mmc->bus_width == 4)
  519. ctrl |= SDHCI_CTRL_4BITBUS;
  520. else
  521. ctrl &= ~SDHCI_CTRL_4BITBUS;
  522. }
  523. if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
  524. (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
  525. ctrl &= ~SDHCI_CTRL_HISPD;
  526. no_hispd_bit = true;
  527. }
  528. if (!no_hispd_bit) {
  529. if (mmc->selected_mode == MMC_HS ||
  530. mmc->selected_mode == SD_HS ||
  531. mmc->selected_mode == MMC_DDR_52 ||
  532. mmc->selected_mode == MMC_HS_200 ||
  533. mmc->selected_mode == MMC_HS_400 ||
  534. mmc->selected_mode == UHS_SDR25 ||
  535. mmc->selected_mode == UHS_SDR50 ||
  536. mmc->selected_mode == UHS_SDR104 ||
  537. mmc->selected_mode == UHS_DDR50)
  538. ctrl |= SDHCI_CTRL_HISPD;
  539. else
  540. ctrl &= ~SDHCI_CTRL_HISPD;
  541. }
  542. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  543. /* If available, call the driver specific "post" set_ios() function */
  544. if (host->ops && host->ops->set_ios_post)
  545. return host->ops->set_ios_post(host);
  546. return 0;
  547. }
  548. static int sdhci_init(struct mmc *mmc)
  549. {
  550. struct sdhci_host *host = mmc->priv;
  551. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
  552. struct udevice *dev = mmc->dev;
  553. gpio_request_by_name(dev, "cd-gpios", 0,
  554. &host->cd_gpio, GPIOD_IS_IN);
  555. #endif
  556. sdhci_reset(host, SDHCI_RESET_ALL);
  557. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  558. host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  559. /*
  560. * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
  561. * is defined.
  562. */
  563. host->force_align_buffer = true;
  564. #else
  565. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
  566. host->align_buffer = memalign(8, 512 * 1024);
  567. if (!host->align_buffer) {
  568. printf("%s: Aligned buffer alloc failed!!!\n",
  569. __func__);
  570. return -ENOMEM;
  571. }
  572. }
  573. #endif
  574. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  575. if (host->ops && host->ops->get_cd)
  576. host->ops->get_cd(host);
  577. /* Enable only interrupts served by the SD controller */
  578. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  579. SDHCI_INT_ENABLE);
  580. /* Mask all sdhci interrupt sources */
  581. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  582. return 0;
  583. }
  584. #ifdef CONFIG_DM_MMC
  585. int sdhci_probe(struct udevice *dev)
  586. {
  587. struct mmc *mmc = mmc_get_mmc_dev(dev);
  588. return sdhci_init(mmc);
  589. }
  590. static int sdhci_deferred_probe(struct udevice *dev)
  591. {
  592. int err;
  593. struct mmc *mmc = mmc_get_mmc_dev(dev);
  594. struct sdhci_host *host = mmc->priv;
  595. if (host->ops && host->ops->deferred_probe) {
  596. err = host->ops->deferred_probe(host);
  597. if (err)
  598. return err;
  599. }
  600. return 0;
  601. }
  602. static int sdhci_get_cd(struct udevice *dev)
  603. {
  604. struct mmc *mmc = mmc_get_mmc_dev(dev);
  605. struct sdhci_host *host = mmc->priv;
  606. int value;
  607. /* If nonremovable, assume that the card is always present. */
  608. if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
  609. return 1;
  610. /* If polling, assume that the card is always present. */
  611. if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
  612. return 1;
  613. #if CONFIG_IS_ENABLED(DM_GPIO)
  614. value = dm_gpio_get_value(&host->cd_gpio);
  615. if (value >= 0) {
  616. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  617. return !value;
  618. else
  619. return value;
  620. }
  621. #endif
  622. value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
  623. SDHCI_CARD_PRESENT);
  624. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  625. return !value;
  626. else
  627. return value;
  628. }
  629. const struct dm_mmc_ops sdhci_ops = {
  630. .send_cmd = sdhci_send_command,
  631. .set_ios = sdhci_set_ios,
  632. .get_cd = sdhci_get_cd,
  633. .deferred_probe = sdhci_deferred_probe,
  634. #ifdef MMC_SUPPORTS_TUNING
  635. .execute_tuning = sdhci_execute_tuning,
  636. #endif
  637. };
  638. #else
  639. static const struct mmc_ops sdhci_ops = {
  640. .send_cmd = sdhci_send_command,
  641. .set_ios = sdhci_set_ios,
  642. .init = sdhci_init,
  643. };
  644. #endif
  645. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  646. u32 f_max, u32 f_min)
  647. {
  648. u32 caps, caps_1 = 0;
  649. #if CONFIG_IS_ENABLED(DM_MMC)
  650. u64 dt_caps, dt_caps_mask;
  651. dt_caps_mask = dev_read_u64_default(host->mmc->dev,
  652. "sdhci-caps-mask", 0);
  653. dt_caps = dev_read_u64_default(host->mmc->dev,
  654. "sdhci-caps", 0);
  655. caps = ~lower_32_bits(dt_caps_mask) &
  656. sdhci_readl(host, SDHCI_CAPABILITIES);
  657. caps |= lower_32_bits(dt_caps);
  658. #else
  659. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  660. #endif
  661. debug("%s, caps: 0x%x\n", __func__, caps);
  662. #ifdef CONFIG_MMC_SDHCI_SDMA
  663. if ((caps & SDHCI_CAN_DO_SDMA)) {
  664. host->flags |= USE_SDMA;
  665. } else {
  666. debug("%s: Your controller doesn't support SDMA!!\n",
  667. __func__);
  668. }
  669. #endif
  670. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  671. if (!(caps & SDHCI_CAN_DO_ADMA2)) {
  672. printf("%s: Your controller doesn't support SDMA!!\n",
  673. __func__);
  674. return -EINVAL;
  675. }
  676. host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
  677. host->adma_addr = (dma_addr_t)host->adma_desc_table;
  678. #ifdef CONFIG_DMA_ADDR_T_64BIT
  679. host->flags |= USE_ADMA64;
  680. #else
  681. host->flags |= USE_ADMA;
  682. #endif
  683. #endif
  684. if (host->quirks & SDHCI_QUIRK_REG32_RW)
  685. host->version =
  686. sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
  687. else
  688. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  689. cfg->name = host->name;
  690. #ifndef CONFIG_DM_MMC
  691. cfg->ops = &sdhci_ops;
  692. #endif
  693. /* Check whether the clock multiplier is supported or not */
  694. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  695. #if CONFIG_IS_ENABLED(DM_MMC)
  696. caps_1 = ~upper_32_bits(dt_caps_mask) &
  697. sdhci_readl(host, SDHCI_CAPABILITIES_1);
  698. caps_1 |= upper_32_bits(dt_caps);
  699. #else
  700. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  701. #endif
  702. debug("%s, caps_1: 0x%x\n", __func__, caps_1);
  703. host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
  704. SDHCI_CLOCK_MUL_SHIFT;
  705. }
  706. if (host->max_clk == 0) {
  707. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  708. host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
  709. SDHCI_CLOCK_BASE_SHIFT;
  710. else
  711. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
  712. SDHCI_CLOCK_BASE_SHIFT;
  713. host->max_clk *= 1000000;
  714. if (host->clk_mul)
  715. host->max_clk *= host->clk_mul;
  716. }
  717. if (host->max_clk == 0) {
  718. printf("%s: Hardware doesn't specify base clock frequency\n",
  719. __func__);
  720. return -EINVAL;
  721. }
  722. if (f_max && (f_max < host->max_clk))
  723. cfg->f_max = f_max;
  724. else
  725. cfg->f_max = host->max_clk;
  726. if (f_min)
  727. cfg->f_min = f_min;
  728. else {
  729. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  730. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
  731. else
  732. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
  733. }
  734. cfg->voltages = 0;
  735. if (caps & SDHCI_CAN_VDD_330)
  736. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  737. if (caps & SDHCI_CAN_VDD_300)
  738. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  739. if (caps & SDHCI_CAN_VDD_180)
  740. cfg->voltages |= MMC_VDD_165_195;
  741. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  742. cfg->voltages |= host->voltages;
  743. if (caps & SDHCI_CAN_DO_HISPD)
  744. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  745. cfg->host_caps |= MMC_MODE_4BIT;
  746. /* Since Host Controller Version3.0 */
  747. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  748. if (!(caps & SDHCI_CAN_DO_8BIT))
  749. cfg->host_caps &= ~MMC_MODE_8BIT;
  750. }
  751. if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
  752. cfg->host_caps &= ~MMC_MODE_HS;
  753. cfg->host_caps &= ~MMC_MODE_HS_52MHz;
  754. }
  755. if (!(cfg->voltages & MMC_VDD_165_195))
  756. caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  757. SDHCI_SUPPORT_DDR50);
  758. if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  759. SDHCI_SUPPORT_DDR50))
  760. cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  761. if (caps_1 & SDHCI_SUPPORT_SDR104) {
  762. cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  763. /*
  764. * SD3.0: SDR104 is supported so (for eMMC) the caps2
  765. * field can be promoted to support HS200.
  766. */
  767. cfg->host_caps |= MMC_CAP(MMC_HS_200);
  768. } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  769. cfg->host_caps |= MMC_CAP(UHS_SDR50);
  770. }
  771. if (caps_1 & SDHCI_SUPPORT_DDR50)
  772. cfg->host_caps |= MMC_CAP(UHS_DDR50);
  773. if (host->host_caps)
  774. cfg->host_caps |= host->host_caps;
  775. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  776. return 0;
  777. }
  778. #ifdef CONFIG_BLK
  779. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  780. {
  781. return mmc_bind(dev, mmc, cfg);
  782. }
  783. #else
  784. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
  785. {
  786. int ret;
  787. ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
  788. if (ret)
  789. return ret;
  790. host->mmc = mmc_create(&host->cfg, host);
  791. if (host->mmc == NULL) {
  792. printf("%s: mmc create fail!\n", __func__);
  793. return -ENOMEM;
  794. }
  795. return 0;
  796. }
  797. #endif