mtk-sd.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek SD/MMC Card Interface driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Weijie Gao <weijie.gao@mediatek.com>
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <mmc.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <stdbool.h>
  16. #include <asm/gpio.h>
  17. #include <dm/device_compat.h>
  18. #include <dm/pinctrl.h>
  19. #include <linux/bitops.h>
  20. #include <linux/io.h>
  21. #include <linux/iopoll.h>
  22. /* MSDC_CFG */
  23. #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
  24. #define MSDC_CFG_CKMOD_EXT_M 0x300000
  25. #define MSDC_CFG_CKMOD_EXT_S 20
  26. #define MSDC_CFG_CKDIV_EXT_M 0xfff00
  27. #define MSDC_CFG_CKDIV_EXT_S 8
  28. #define MSDC_CFG_HS400_CK_MODE BIT(18)
  29. #define MSDC_CFG_CKMOD_M 0x30000
  30. #define MSDC_CFG_CKMOD_S 16
  31. #define MSDC_CFG_CKDIV_M 0xff00
  32. #define MSDC_CFG_CKDIV_S 8
  33. #define MSDC_CFG_CKSTB BIT(7)
  34. #define MSDC_CFG_PIO BIT(3)
  35. #define MSDC_CFG_RST BIT(2)
  36. #define MSDC_CFG_CKPDN BIT(1)
  37. #define MSDC_CFG_MODE BIT(0)
  38. /* MSDC_IOCON */
  39. #define MSDC_IOCON_W_DSPL BIT(8)
  40. #define MSDC_IOCON_DSPL BIT(2)
  41. #define MSDC_IOCON_RSPL BIT(1)
  42. /* MSDC_PS */
  43. #define MSDC_PS_DAT0 BIT(16)
  44. #define MSDC_PS_CDDBCE_M 0xf000
  45. #define MSDC_PS_CDDBCE_S 12
  46. #define MSDC_PS_CDSTS BIT(1)
  47. #define MSDC_PS_CDEN BIT(0)
  48. /* #define MSDC_INT(EN) */
  49. #define MSDC_INT_ACMDRDY BIT(3)
  50. #define MSDC_INT_ACMDTMO BIT(4)
  51. #define MSDC_INT_ACMDCRCERR BIT(5)
  52. #define MSDC_INT_CMDRDY BIT(8)
  53. #define MSDC_INT_CMDTMO BIT(9)
  54. #define MSDC_INT_RSPCRCERR BIT(10)
  55. #define MSDC_INT_XFER_COMPL BIT(12)
  56. #define MSDC_INT_DATTMO BIT(14)
  57. #define MSDC_INT_DATCRCERR BIT(15)
  58. /* MSDC_FIFOCS */
  59. #define MSDC_FIFOCS_CLR BIT(31)
  60. #define MSDC_FIFOCS_TXCNT_M 0xff0000
  61. #define MSDC_FIFOCS_TXCNT_S 16
  62. #define MSDC_FIFOCS_RXCNT_M 0xff
  63. #define MSDC_FIFOCS_RXCNT_S 0
  64. /* #define SDC_CFG */
  65. #define SDC_CFG_DTOC_M 0xff000000
  66. #define SDC_CFG_DTOC_S 24
  67. #define SDC_CFG_SDIOIDE BIT(20)
  68. #define SDC_CFG_SDIO BIT(19)
  69. #define SDC_CFG_BUSWIDTH_M 0x30000
  70. #define SDC_CFG_BUSWIDTH_S 16
  71. /* SDC_CMD */
  72. #define SDC_CMD_BLK_LEN_M 0xfff0000
  73. #define SDC_CMD_BLK_LEN_S 16
  74. #define SDC_CMD_STOP BIT(14)
  75. #define SDC_CMD_WR BIT(13)
  76. #define SDC_CMD_DTYPE_M 0x1800
  77. #define SDC_CMD_DTYPE_S 11
  78. #define SDC_CMD_RSPTYP_M 0x380
  79. #define SDC_CMD_RSPTYP_S 7
  80. #define SDC_CMD_CMD_M 0x3f
  81. #define SDC_CMD_CMD_S 0
  82. /* SDC_STS */
  83. #define SDC_STS_CMDBUSY BIT(1)
  84. #define SDC_STS_SDCBUSY BIT(0)
  85. /* SDC_ADV_CFG0 */
  86. #define SDC_RX_ENHANCE_EN BIT(20)
  87. /* PATCH_BIT0 */
  88. #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
  89. #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
  90. /* PATCH_BIT1 */
  91. #define MSDC_PB1_STOP_DLY_M 0xf00
  92. #define MSDC_PB1_STOP_DLY_S 8
  93. /* PATCH_BIT2 */
  94. #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
  95. #define MSDC_PB2_CRCSTSENSEL_S 29
  96. #define MSDC_PB2_CFGCRCSTS BIT(28)
  97. #define MSDC_PB2_RESPSTSENSEL_M 0x70000
  98. #define MSDC_PB2_RESPSTSENSEL_S 16
  99. #define MSDC_PB2_CFGRESP BIT(15)
  100. #define MSDC_PB2_RESPWAIT_M 0x0c
  101. #define MSDC_PB2_RESPWAIT_S 2
  102. /* PAD_TUNE */
  103. #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
  104. #define MSDC_PAD_TUNE_CMDRRDLY_S 22
  105. #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
  106. #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
  107. #define MSDC_PAD_TUNE_CMDRDLY_S 16
  108. #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
  109. #define MSDC_PAD_TUNE_RD_SEL BIT(13)
  110. #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
  111. #define MSDC_PAD_TUNE_DATRRDLY_S 8
  112. #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
  113. #define MSDC_PAD_TUNE_DATWRDLY_S 0
  114. #define PAD_CMD_TUNE_RX_DLY3 0x3E
  115. #define PAD_CMD_TUNE_RX_DLY3_S 1
  116. /* EMMC50_CFG0 */
  117. #define EMMC50_CFG_CFCSTS_SEL BIT(4)
  118. /* SDC_FIFO_CFG */
  119. #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
  120. #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
  121. /* EMMC_TOP_CONTROL mask */
  122. #define PAD_RXDLY_SEL BIT(0)
  123. #define DELAY_EN BIT(1)
  124. #define PAD_DAT_RD_RXDLY2 (0x1f << 2)
  125. #define PAD_DAT_RD_RXDLY (0x1f << 7)
  126. #define PAD_DAT_RD_RXDLY_S 7
  127. #define PAD_DAT_RD_RXDLY2_SEL BIT(12)
  128. #define PAD_DAT_RD_RXDLY_SEL BIT(13)
  129. #define DATA_K_VALUE_SEL BIT(14)
  130. #define SDC_RX_ENH_EN BIT(15)
  131. /* EMMC_TOP_CMD mask */
  132. #define PAD_CMD_RXDLY2 (0x1f << 0)
  133. #define PAD_CMD_RXDLY (0x1f << 5)
  134. #define PAD_CMD_RXDLY_S 5
  135. #define PAD_CMD_RD_RXDLY2_SEL BIT(10)
  136. #define PAD_CMD_RD_RXDLY_SEL BIT(11)
  137. #define PAD_CMD_TX_DLY (0x1f << 12)
  138. /* SDC_CFG_BUSWIDTH */
  139. #define MSDC_BUS_1BITS 0x0
  140. #define MSDC_BUS_4BITS 0x1
  141. #define MSDC_BUS_8BITS 0x2
  142. #define MSDC_FIFO_SIZE 128
  143. #define PAD_DELAY_MAX 32
  144. #define DEFAULT_CD_DEBOUNCE 8
  145. #define CMD_INTS_MASK \
  146. (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
  147. #define DATA_INTS_MASK \
  148. (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
  149. /* Register offset */
  150. struct mtk_sd_regs {
  151. u32 msdc_cfg;
  152. u32 msdc_iocon;
  153. u32 msdc_ps;
  154. u32 msdc_int;
  155. u32 msdc_inten;
  156. u32 msdc_fifocs;
  157. u32 msdc_txdata;
  158. u32 msdc_rxdata;
  159. u32 reserved0[4];
  160. u32 sdc_cfg;
  161. u32 sdc_cmd;
  162. u32 sdc_arg;
  163. u32 sdc_sts;
  164. u32 sdc_resp[4];
  165. u32 sdc_blk_num;
  166. u32 sdc_vol_chg;
  167. u32 sdc_csts;
  168. u32 sdc_csts_en;
  169. u32 sdc_datcrc_sts;
  170. u32 sdc_adv_cfg0;
  171. u32 reserved1[2];
  172. u32 emmc_cfg0;
  173. u32 emmc_cfg1;
  174. u32 emmc_sts;
  175. u32 emmc_iocon;
  176. u32 sd_acmd_resp;
  177. u32 sd_acmd19_trg;
  178. u32 sd_acmd19_sts;
  179. u32 dma_sa_high4bit;
  180. u32 dma_sa;
  181. u32 dma_ca;
  182. u32 dma_ctrl;
  183. u32 dma_cfg;
  184. u32 sw_dbg_sel;
  185. u32 sw_dbg_out;
  186. u32 dma_length;
  187. u32 reserved2;
  188. u32 patch_bit0;
  189. u32 patch_bit1;
  190. u32 patch_bit2;
  191. u32 reserved3;
  192. u32 dat0_tune_crc;
  193. u32 dat1_tune_crc;
  194. u32 dat2_tune_crc;
  195. u32 dat3_tune_crc;
  196. u32 cmd_tune_crc;
  197. u32 sdio_tune_wind;
  198. u32 reserved4[5];
  199. u32 pad_tune;
  200. u32 pad_tune0;
  201. u32 pad_tune1;
  202. u32 dat_rd_dly[4];
  203. u32 reserved5[2];
  204. u32 hw_dbg_sel;
  205. u32 main_ver;
  206. u32 eco_ver;
  207. u32 reserved6[27];
  208. u32 pad_ds_tune;
  209. u32 pad_cmd_tune;
  210. u32 reserved7[30];
  211. u32 emmc50_cfg0;
  212. u32 reserved8[7];
  213. u32 sdc_fifo_cfg;
  214. };
  215. struct msdc_top_regs {
  216. u32 emmc_top_control;
  217. u32 emmc_top_cmd;
  218. u32 emmc50_pad_ctl0;
  219. u32 emmc50_pad_ds_tune;
  220. u32 emmc50_pad_dat0_tune;
  221. u32 emmc50_pad_dat1_tune;
  222. u32 emmc50_pad_dat2_tune;
  223. u32 emmc50_pad_dat3_tune;
  224. u32 emmc50_pad_dat4_tune;
  225. u32 emmc50_pad_dat5_tune;
  226. u32 emmc50_pad_dat6_tune;
  227. u32 emmc50_pad_dat7_tune;
  228. };
  229. struct msdc_compatible {
  230. u8 clk_div_bits;
  231. u8 sclk_cycle_shift;
  232. bool pad_tune0;
  233. bool async_fifo;
  234. bool data_tune;
  235. bool busy_check;
  236. bool stop_clk_fix;
  237. bool enhance_rx;
  238. };
  239. struct msdc_delay_phase {
  240. u8 maxlen;
  241. u8 start;
  242. u8 final_phase;
  243. };
  244. struct msdc_plat {
  245. struct mmc_config cfg;
  246. struct mmc mmc;
  247. };
  248. struct msdc_tune_para {
  249. u32 iocon;
  250. u32 pad_tune;
  251. u32 pad_cmd_tune;
  252. };
  253. struct msdc_host {
  254. struct mtk_sd_regs *base;
  255. struct msdc_top_regs *top_base;
  256. struct mmc *mmc;
  257. struct msdc_compatible *dev_comp;
  258. struct clk src_clk; /* for SD/MMC bus clock */
  259. struct clk src_clk_cg; /* optional, MSDC source clock control gate */
  260. struct clk h_clk; /* MSDC core clock */
  261. u32 src_clk_freq; /* source clock */
  262. u32 mclk; /* mmc framework required bus clock */
  263. u32 sclk; /* actual calculated bus clock */
  264. /* operation timeout clocks */
  265. u32 timeout_ns;
  266. u32 timeout_clks;
  267. /* tuning options */
  268. u32 hs400_ds_delay;
  269. u32 hs200_cmd_int_delay;
  270. u32 hs200_write_int_delay;
  271. u32 latch_ck;
  272. u32 r_smpl; /* sample edge */
  273. bool hs400_mode;
  274. /* whether to use gpio detection or built-in hw detection */
  275. bool builtin_cd;
  276. bool cd_active_high;
  277. /* card detection / write protection GPIOs */
  278. #if CONFIG_IS_ENABLED(DM_GPIO)
  279. struct gpio_desc gpio_wp;
  280. struct gpio_desc gpio_cd;
  281. #endif
  282. uint last_resp_type;
  283. uint last_data_write;
  284. enum bus_mode timing;
  285. struct msdc_tune_para def_tune_para;
  286. struct msdc_tune_para saved_tune_para;
  287. };
  288. static void msdc_reset_hw(struct msdc_host *host)
  289. {
  290. u32 reg;
  291. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
  292. readl_poll_timeout(&host->base->msdc_cfg, reg,
  293. !(reg & MSDC_CFG_RST), 1000000);
  294. }
  295. static void msdc_fifo_clr(struct msdc_host *host)
  296. {
  297. u32 reg;
  298. setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
  299. readl_poll_timeout(&host->base->msdc_fifocs, reg,
  300. !(reg & MSDC_FIFOCS_CLR), 1000000);
  301. }
  302. static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
  303. {
  304. return (readl(&host->base->msdc_fifocs) &
  305. MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
  306. }
  307. static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
  308. {
  309. return (readl(&host->base->msdc_fifocs) &
  310. MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
  311. }
  312. static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
  313. {
  314. u32 resp;
  315. switch (cmd->resp_type) {
  316. /* Actually, R1, R5, R6, R7 are the same */
  317. case MMC_RSP_R1:
  318. resp = 0x1;
  319. break;
  320. case MMC_RSP_R1b:
  321. resp = 0x7;
  322. break;
  323. case MMC_RSP_R2:
  324. resp = 0x2;
  325. break;
  326. case MMC_RSP_R3:
  327. resp = 0x3;
  328. break;
  329. case MMC_RSP_NONE:
  330. default:
  331. resp = 0x0;
  332. break;
  333. }
  334. return resp;
  335. }
  336. static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
  337. struct mmc_cmd *cmd,
  338. struct mmc_data *data)
  339. {
  340. u32 opcode = cmd->cmdidx;
  341. u32 resp_type = msdc_cmd_find_resp(host, cmd);
  342. uint blocksize = 0;
  343. u32 dtype = 0;
  344. u32 rawcmd = 0;
  345. switch (opcode) {
  346. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  347. case MMC_CMD_READ_MULTIPLE_BLOCK:
  348. dtype = 2;
  349. break;
  350. case MMC_CMD_WRITE_SINGLE_BLOCK:
  351. case MMC_CMD_READ_SINGLE_BLOCK:
  352. case SD_CMD_APP_SEND_SCR:
  353. case MMC_CMD_SEND_TUNING_BLOCK:
  354. case MMC_CMD_SEND_TUNING_BLOCK_HS200:
  355. dtype = 1;
  356. break;
  357. case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
  358. case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
  359. case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
  360. if (data)
  361. dtype = 1;
  362. }
  363. if (data) {
  364. if (data->flags == MMC_DATA_WRITE)
  365. rawcmd |= SDC_CMD_WR;
  366. if (data->blocks > 1)
  367. dtype = 2;
  368. blocksize = data->blocksize;
  369. }
  370. rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
  371. ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
  372. ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
  373. ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
  374. if (opcode == MMC_CMD_STOP_TRANSMISSION)
  375. rawcmd |= SDC_CMD_STOP;
  376. return rawcmd;
  377. }
  378. static int msdc_cmd_done(struct msdc_host *host, int events,
  379. struct mmc_cmd *cmd)
  380. {
  381. u32 *rsp = cmd->response;
  382. int ret = 0;
  383. if (cmd->resp_type & MMC_RSP_PRESENT) {
  384. if (cmd->resp_type & MMC_RSP_136) {
  385. rsp[0] = readl(&host->base->sdc_resp[3]);
  386. rsp[1] = readl(&host->base->sdc_resp[2]);
  387. rsp[2] = readl(&host->base->sdc_resp[1]);
  388. rsp[3] = readl(&host->base->sdc_resp[0]);
  389. } else {
  390. rsp[0] = readl(&host->base->sdc_resp[0]);
  391. }
  392. }
  393. if (!(events & MSDC_INT_CMDRDY)) {
  394. if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
  395. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
  396. /*
  397. * should not clear fifo/interrupt as the tune data
  398. * may have alreay come.
  399. */
  400. msdc_reset_hw(host);
  401. if (events & MSDC_INT_CMDTMO)
  402. ret = -ETIMEDOUT;
  403. else
  404. ret = -EIO;
  405. }
  406. return ret;
  407. }
  408. static bool msdc_cmd_is_ready(struct msdc_host *host)
  409. {
  410. int ret;
  411. u32 reg;
  412. /* The max busy time we can endure is 20ms */
  413. ret = readl_poll_timeout(&host->base->sdc_sts, reg,
  414. !(reg & SDC_STS_CMDBUSY), 20000);
  415. if (ret) {
  416. pr_err("CMD bus busy detected\n");
  417. msdc_reset_hw(host);
  418. return false;
  419. }
  420. if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
  421. ret = readl_poll_timeout(&host->base->msdc_ps, reg,
  422. reg & MSDC_PS_DAT0, 1000000);
  423. if (ret) {
  424. pr_err("Card stuck in programming state!\n");
  425. msdc_reset_hw(host);
  426. return false;
  427. }
  428. }
  429. return true;
  430. }
  431. static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
  432. struct mmc_data *data)
  433. {
  434. u32 rawcmd;
  435. u32 status;
  436. u32 blocks = 0;
  437. int ret;
  438. if (!msdc_cmd_is_ready(host))
  439. return -EIO;
  440. if ((readl(&host->base->msdc_fifocs) &
  441. MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
  442. (readl(&host->base->msdc_fifocs) &
  443. MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
  444. pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
  445. msdc_reset_hw(host);
  446. }
  447. msdc_fifo_clr(host);
  448. host->last_resp_type = cmd->resp_type;
  449. host->last_data_write = 0;
  450. rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
  451. if (data)
  452. blocks = data->blocks;
  453. writel(CMD_INTS_MASK, &host->base->msdc_int);
  454. writel(DATA_INTS_MASK, &host->base->msdc_int);
  455. writel(blocks, &host->base->sdc_blk_num);
  456. writel(cmd->cmdarg, &host->base->sdc_arg);
  457. writel(rawcmd, &host->base->sdc_cmd);
  458. ret = readl_poll_timeout(&host->base->msdc_int, status,
  459. status & CMD_INTS_MASK, 1000000);
  460. if (ret)
  461. status = MSDC_INT_CMDTMO;
  462. return msdc_cmd_done(host, status, cmd);
  463. }
  464. static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
  465. {
  466. u32 *wbuf;
  467. while ((size_t)buf % 4) {
  468. *buf++ = readb(&host->base->msdc_rxdata);
  469. size--;
  470. }
  471. wbuf = (u32 *)buf;
  472. while (size >= 4) {
  473. *wbuf++ = readl(&host->base->msdc_rxdata);
  474. size -= 4;
  475. }
  476. buf = (u8 *)wbuf;
  477. while (size) {
  478. *buf++ = readb(&host->base->msdc_rxdata);
  479. size--;
  480. }
  481. }
  482. static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
  483. {
  484. const u32 *wbuf;
  485. while ((size_t)buf % 4) {
  486. writeb(*buf++, &host->base->msdc_txdata);
  487. size--;
  488. }
  489. wbuf = (const u32 *)buf;
  490. while (size >= 4) {
  491. writel(*wbuf++, &host->base->msdc_txdata);
  492. size -= 4;
  493. }
  494. buf = (const u8 *)wbuf;
  495. while (size) {
  496. writeb(*buf++, &host->base->msdc_txdata);
  497. size--;
  498. }
  499. }
  500. static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
  501. {
  502. u32 status;
  503. u32 chksz;
  504. int ret = 0;
  505. while (1) {
  506. status = readl(&host->base->msdc_int);
  507. writel(status, &host->base->msdc_int);
  508. status &= DATA_INTS_MASK;
  509. if (status & MSDC_INT_DATCRCERR) {
  510. ret = -EIO;
  511. break;
  512. }
  513. if (status & MSDC_INT_DATTMO) {
  514. ret = -ETIMEDOUT;
  515. break;
  516. }
  517. chksz = min(size, (u32)MSDC_FIFO_SIZE);
  518. if (msdc_fifo_rx_bytes(host) >= chksz) {
  519. msdc_fifo_read(host, ptr, chksz);
  520. ptr += chksz;
  521. size -= chksz;
  522. }
  523. if (status & MSDC_INT_XFER_COMPL) {
  524. if (size) {
  525. pr_err("data not fully read\n");
  526. ret = -EIO;
  527. }
  528. break;
  529. }
  530. }
  531. return ret;
  532. }
  533. static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
  534. {
  535. u32 status;
  536. u32 chksz;
  537. int ret = 0;
  538. while (1) {
  539. status = readl(&host->base->msdc_int);
  540. writel(status, &host->base->msdc_int);
  541. status &= DATA_INTS_MASK;
  542. if (status & MSDC_INT_DATCRCERR) {
  543. ret = -EIO;
  544. break;
  545. }
  546. if (status & MSDC_INT_DATTMO) {
  547. ret = -ETIMEDOUT;
  548. break;
  549. }
  550. if (status & MSDC_INT_XFER_COMPL) {
  551. if (size) {
  552. pr_err("data not fully written\n");
  553. ret = -EIO;
  554. }
  555. break;
  556. }
  557. chksz = min(size, (u32)MSDC_FIFO_SIZE);
  558. if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
  559. msdc_fifo_write(host, ptr, chksz);
  560. ptr += chksz;
  561. size -= chksz;
  562. }
  563. }
  564. return ret;
  565. }
  566. static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
  567. {
  568. u32 size;
  569. int ret;
  570. if (data->flags == MMC_DATA_WRITE)
  571. host->last_data_write = 1;
  572. size = data->blocks * data->blocksize;
  573. if (data->flags == MMC_DATA_WRITE)
  574. ret = msdc_pio_write(host, (const u8 *)data->src, size);
  575. else
  576. ret = msdc_pio_read(host, (u8 *)data->dest, size);
  577. if (ret) {
  578. msdc_reset_hw(host);
  579. msdc_fifo_clr(host);
  580. }
  581. return ret;
  582. }
  583. static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  584. struct mmc_data *data)
  585. {
  586. struct msdc_host *host = dev_get_priv(dev);
  587. int cmd_ret, data_ret;
  588. cmd_ret = msdc_start_command(host, cmd, data);
  589. if (cmd_ret &&
  590. !(cmd_ret == -EIO &&
  591. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  592. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
  593. return cmd_ret;
  594. if (data) {
  595. data_ret = msdc_start_data(host, data);
  596. if (cmd_ret)
  597. return cmd_ret;
  598. else
  599. return data_ret;
  600. }
  601. return 0;
  602. }
  603. static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
  604. {
  605. u32 timeout, clk_ns, shift;
  606. u32 mode = 0;
  607. host->timeout_ns = ns;
  608. host->timeout_clks = clks;
  609. if (host->sclk == 0) {
  610. timeout = 0;
  611. } else {
  612. shift = host->dev_comp->sclk_cycle_shift;
  613. clk_ns = 1000000000UL / host->sclk;
  614. timeout = (ns + clk_ns - 1) / clk_ns + clks;
  615. /* unit is 1048576 sclk cycles */
  616. timeout = (timeout + (0x1 << shift) - 1) >> shift;
  617. if (host->dev_comp->clk_div_bits == 8)
  618. mode = (readl(&host->base->msdc_cfg) &
  619. MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
  620. else
  621. mode = (readl(&host->base->msdc_cfg) &
  622. MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
  623. /* DDR mode will double the clk cycles for data timeout */
  624. timeout = mode >= 2 ? timeout * 2 : timeout;
  625. timeout = timeout > 1 ? timeout - 1 : 0;
  626. timeout = timeout > 255 ? 255 : timeout;
  627. }
  628. clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
  629. timeout << SDC_CFG_DTOC_S);
  630. }
  631. static void msdc_set_buswidth(struct msdc_host *host, u32 width)
  632. {
  633. u32 val = readl(&host->base->sdc_cfg);
  634. val &= ~SDC_CFG_BUSWIDTH_M;
  635. switch (width) {
  636. default:
  637. case 1:
  638. val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
  639. break;
  640. case 4:
  641. val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
  642. break;
  643. case 8:
  644. val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
  645. break;
  646. }
  647. writel(val, &host->base->sdc_cfg);
  648. }
  649. static void msdc_set_mclk(struct udevice *dev,
  650. struct msdc_host *host, enum bus_mode timing, u32 hz)
  651. {
  652. u32 mode;
  653. u32 div;
  654. u32 sclk;
  655. u32 reg;
  656. if (!hz) {
  657. host->mclk = 0;
  658. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  659. return;
  660. }
  661. if (host->dev_comp->clk_div_bits == 8)
  662. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
  663. else
  664. clrbits_le32(&host->base->msdc_cfg,
  665. MSDC_CFG_HS400_CK_MODE_EXT);
  666. if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
  667. timing == MMC_HS_400) {
  668. if (timing == MMC_HS_400)
  669. mode = 0x3;
  670. else
  671. mode = 0x2; /* ddr mode and use divisor */
  672. if (hz >= (host->src_clk_freq >> 2)) {
  673. div = 0; /* mean div = 1/4 */
  674. sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
  675. } else {
  676. div = (host->src_clk_freq + ((hz << 2) - 1)) /
  677. (hz << 2);
  678. sclk = (host->src_clk_freq >> 2) / div;
  679. div = (div >> 1);
  680. }
  681. if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
  682. if (host->dev_comp->clk_div_bits == 8)
  683. setbits_le32(&host->base->msdc_cfg,
  684. MSDC_CFG_HS400_CK_MODE);
  685. else
  686. setbits_le32(&host->base->msdc_cfg,
  687. MSDC_CFG_HS400_CK_MODE_EXT);
  688. sclk = host->src_clk_freq >> 1;
  689. div = 0; /* div is ignore when bit18 is set */
  690. }
  691. } else if (hz >= host->src_clk_freq) {
  692. mode = 0x1; /* no divisor */
  693. div = 0;
  694. sclk = host->src_clk_freq;
  695. } else {
  696. mode = 0x0; /* use divisor */
  697. if (hz >= (host->src_clk_freq >> 1)) {
  698. div = 0; /* mean div = 1/2 */
  699. sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
  700. } else {
  701. div = (host->src_clk_freq + ((hz << 2) - 1)) /
  702. (hz << 2);
  703. sclk = (host->src_clk_freq >> 2) / div;
  704. }
  705. }
  706. clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  707. if (host->dev_comp->clk_div_bits == 8) {
  708. div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
  709. clrsetbits_le32(&host->base->msdc_cfg,
  710. MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
  711. (mode << MSDC_CFG_CKMOD_S) |
  712. (div << MSDC_CFG_CKDIV_S));
  713. } else {
  714. div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
  715. MSDC_CFG_CKDIV_EXT_S));
  716. clrsetbits_le32(&host->base->msdc_cfg,
  717. MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
  718. (mode << MSDC_CFG_CKMOD_EXT_S) |
  719. (div << MSDC_CFG_CKDIV_EXT_S));
  720. }
  721. readl_poll_timeout(&host->base->msdc_cfg, reg,
  722. reg & MSDC_CFG_CKSTB, 1000000);
  723. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
  724. host->sclk = sclk;
  725. host->mclk = hz;
  726. host->timing = timing;
  727. /* needed because clk changed. */
  728. msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
  729. /*
  730. * mmc_select_hs400() will drop to 50Mhz and High speed mode,
  731. * tune result of hs200/200Mhz is not suitable for 50Mhz
  732. */
  733. if (host->sclk <= 52000000) {
  734. writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
  735. writel(host->def_tune_para.pad_tune,
  736. &host->base->pad_tune);
  737. } else {
  738. writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
  739. writel(host->saved_tune_para.pad_tune,
  740. &host->base->pad_tune);
  741. }
  742. dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
  743. }
  744. static int msdc_ops_set_ios(struct udevice *dev)
  745. {
  746. struct msdc_plat *plat = dev_get_platdata(dev);
  747. struct msdc_host *host = dev_get_priv(dev);
  748. struct mmc *mmc = &plat->mmc;
  749. uint clock = mmc->clock;
  750. msdc_set_buswidth(host, mmc->bus_width);
  751. if (mmc->clk_disable)
  752. clock = 0;
  753. else if (clock < mmc->cfg->f_min)
  754. clock = mmc->cfg->f_min;
  755. if (host->mclk != clock || host->timing != mmc->selected_mode)
  756. msdc_set_mclk(dev, host, mmc->selected_mode, clock);
  757. return 0;
  758. }
  759. static int msdc_ops_get_cd(struct udevice *dev)
  760. {
  761. struct msdc_host *host = dev_get_priv(dev);
  762. u32 val;
  763. if (host->builtin_cd) {
  764. val = readl(&host->base->msdc_ps);
  765. val = !!(val & MSDC_PS_CDSTS);
  766. return !val ^ host->cd_active_high;
  767. }
  768. #if CONFIG_IS_ENABLED(DM_GPIO)
  769. if (!host->gpio_cd.dev)
  770. return 1;
  771. return dm_gpio_get_value(&host->gpio_cd);
  772. #else
  773. return 1;
  774. #endif
  775. }
  776. static int msdc_ops_get_wp(struct udevice *dev)
  777. {
  778. #if CONFIG_IS_ENABLED(DM_GPIO)
  779. struct msdc_host *host = dev_get_priv(dev);
  780. if (!host->gpio_wp.dev)
  781. return 0;
  782. return !dm_gpio_get_value(&host->gpio_wp);
  783. #else
  784. return 0;
  785. #endif
  786. }
  787. #ifdef MMC_SUPPORTS_TUNING
  788. static u32 test_delay_bit(u32 delay, u32 bit)
  789. {
  790. bit %= PAD_DELAY_MAX;
  791. return delay & (1 << bit);
  792. }
  793. static int get_delay_len(u32 delay, u32 start_bit)
  794. {
  795. int i;
  796. for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
  797. if (test_delay_bit(delay, start_bit + i) == 0)
  798. return i;
  799. }
  800. return PAD_DELAY_MAX - start_bit;
  801. }
  802. static struct msdc_delay_phase get_best_delay(struct udevice *dev,
  803. struct msdc_host *host, u32 delay)
  804. {
  805. int start = 0, len = 0;
  806. int start_final = 0, len_final = 0;
  807. u8 final_phase = 0xff;
  808. struct msdc_delay_phase delay_phase = { 0, };
  809. if (delay == 0) {
  810. dev_err(dev, "phase error: [map:%x]\n", delay);
  811. delay_phase.final_phase = final_phase;
  812. return delay_phase;
  813. }
  814. while (start < PAD_DELAY_MAX) {
  815. len = get_delay_len(delay, start);
  816. if (len_final < len) {
  817. start_final = start;
  818. len_final = len;
  819. }
  820. start += len ? len : 1;
  821. if (len >= 12 && start_final < 4)
  822. break;
  823. }
  824. /* The rule is to find the smallest delay cell */
  825. if (start_final == 0)
  826. final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
  827. else
  828. final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
  829. dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
  830. delay, len_final, final_phase);
  831. delay_phase.maxlen = len_final;
  832. delay_phase.start = start_final;
  833. delay_phase.final_phase = final_phase;
  834. return delay_phase;
  835. }
  836. static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
  837. {
  838. void __iomem *tune_reg = &host->base->pad_tune;
  839. if (host->dev_comp->pad_tune0)
  840. tune_reg = &host->base->pad_tune0;
  841. if (host->top_base)
  842. clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
  843. value << PAD_CMD_RXDLY_S);
  844. else
  845. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  846. value << MSDC_PAD_TUNE_CMDRDLY_S);
  847. }
  848. static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
  849. {
  850. void __iomem *tune_reg = &host->base->pad_tune;
  851. if (host->dev_comp->pad_tune0)
  852. tune_reg = &host->base->pad_tune0;
  853. if (host->top_base)
  854. clrsetbits_le32(&host->top_base->emmc_top_control,
  855. PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
  856. else
  857. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  858. value << MSDC_PAD_TUNE_DATRRDLY_S);
  859. }
  860. static int hs400_tune_response(struct udevice *dev, u32 opcode)
  861. {
  862. struct msdc_plat *plat = dev_get_platdata(dev);
  863. struct msdc_host *host = dev_get_priv(dev);
  864. struct mmc *mmc = &plat->mmc;
  865. u32 cmd_delay = 0;
  866. struct msdc_delay_phase final_cmd_delay = { 0, };
  867. u8 final_delay;
  868. void __iomem *tune_reg = &host->base->pad_cmd_tune;
  869. int cmd_err;
  870. int i, j;
  871. setbits_le32(&host->base->pad_cmd_tune, BIT(0));
  872. if (mmc->selected_mode == MMC_HS_200 ||
  873. mmc->selected_mode == UHS_SDR104)
  874. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  875. host->hs200_cmd_int_delay <<
  876. MSDC_PAD_TUNE_CMDRRDLY_S);
  877. if (host->r_smpl)
  878. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  879. else
  880. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  881. for (i = 0; i < PAD_DELAY_MAX; i++) {
  882. clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
  883. i << PAD_CMD_TUNE_RX_DLY3_S);
  884. for (j = 0; j < 3; j++) {
  885. mmc_send_tuning(mmc, opcode, &cmd_err);
  886. if (!cmd_err) {
  887. cmd_delay |= (1 << i);
  888. } else {
  889. cmd_delay &= ~(1 << i);
  890. break;
  891. }
  892. }
  893. }
  894. final_cmd_delay = get_best_delay(dev, host, cmd_delay);
  895. clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
  896. final_cmd_delay.final_phase <<
  897. PAD_CMD_TUNE_RX_DLY3_S);
  898. final_delay = final_cmd_delay.final_phase;
  899. dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
  900. return final_delay == 0xff ? -EIO : 0;
  901. }
  902. static int msdc_tune_response(struct udevice *dev, u32 opcode)
  903. {
  904. struct msdc_plat *plat = dev_get_platdata(dev);
  905. struct msdc_host *host = dev_get_priv(dev);
  906. struct mmc *mmc = &plat->mmc;
  907. u32 rise_delay = 0, fall_delay = 0;
  908. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  909. struct msdc_delay_phase internal_delay_phase;
  910. u8 final_delay, final_maxlen;
  911. u32 internal_delay = 0;
  912. void __iomem *tune_reg = &host->base->pad_tune;
  913. int cmd_err;
  914. int i, j;
  915. if (host->dev_comp->pad_tune0)
  916. tune_reg = &host->base->pad_tune0;
  917. if (mmc->selected_mode == MMC_HS_200 ||
  918. mmc->selected_mode == UHS_SDR104)
  919. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  920. host->hs200_cmd_int_delay <<
  921. MSDC_PAD_TUNE_CMDRRDLY_S);
  922. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  923. for (i = 0; i < PAD_DELAY_MAX; i++) {
  924. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  925. i << MSDC_PAD_TUNE_CMDRDLY_S);
  926. for (j = 0; j < 3; j++) {
  927. mmc_send_tuning(mmc, opcode, &cmd_err);
  928. if (!cmd_err) {
  929. rise_delay |= (1 << i);
  930. } else {
  931. rise_delay &= ~(1 << i);
  932. break;
  933. }
  934. }
  935. }
  936. final_rise_delay = get_best_delay(dev, host, rise_delay);
  937. /* if rising edge has enough margin, do not scan falling edge */
  938. if (final_rise_delay.maxlen >= 12 ||
  939. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  940. goto skip_fall;
  941. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  942. for (i = 0; i < PAD_DELAY_MAX; i++) {
  943. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  944. i << MSDC_PAD_TUNE_CMDRDLY_S);
  945. for (j = 0; j < 3; j++) {
  946. mmc_send_tuning(mmc, opcode, &cmd_err);
  947. if (!cmd_err) {
  948. fall_delay |= (1 << i);
  949. } else {
  950. fall_delay &= ~(1 << i);
  951. break;
  952. }
  953. }
  954. }
  955. final_fall_delay = get_best_delay(dev, host, fall_delay);
  956. skip_fall:
  957. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  958. if (final_maxlen == final_rise_delay.maxlen) {
  959. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  960. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  961. final_rise_delay.final_phase <<
  962. MSDC_PAD_TUNE_CMDRDLY_S);
  963. final_delay = final_rise_delay.final_phase;
  964. } else {
  965. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  966. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
  967. final_fall_delay.final_phase <<
  968. MSDC_PAD_TUNE_CMDRDLY_S);
  969. final_delay = final_fall_delay.final_phase;
  970. }
  971. if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
  972. goto skip_internal;
  973. for (i = 0; i < PAD_DELAY_MAX; i++) {
  974. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  975. i << MSDC_PAD_TUNE_CMDRRDLY_S);
  976. mmc_send_tuning(mmc, opcode, &cmd_err);
  977. if (!cmd_err)
  978. internal_delay |= (1 << i);
  979. }
  980. dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
  981. internal_delay_phase = get_best_delay(dev, host, internal_delay);
  982. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
  983. internal_delay_phase.final_phase <<
  984. MSDC_PAD_TUNE_CMDRRDLY_S);
  985. skip_internal:
  986. dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
  987. return final_delay == 0xff ? -EIO : 0;
  988. }
  989. static int msdc_tune_data(struct udevice *dev, u32 opcode)
  990. {
  991. struct msdc_plat *plat = dev_get_platdata(dev);
  992. struct msdc_host *host = dev_get_priv(dev);
  993. struct mmc *mmc = &plat->mmc;
  994. u32 rise_delay = 0, fall_delay = 0;
  995. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  996. u8 final_delay, final_maxlen;
  997. void __iomem *tune_reg = &host->base->pad_tune;
  998. int cmd_err;
  999. int i, ret;
  1000. if (host->dev_comp->pad_tune0)
  1001. tune_reg = &host->base->pad_tune0;
  1002. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1003. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1004. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1005. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1006. i << MSDC_PAD_TUNE_DATRRDLY_S);
  1007. ret = mmc_send_tuning(mmc, opcode, &cmd_err);
  1008. if (!ret) {
  1009. rise_delay |= (1 << i);
  1010. } else if (cmd_err) {
  1011. /* in this case, retune response is needed */
  1012. ret = msdc_tune_response(dev, opcode);
  1013. if (ret)
  1014. break;
  1015. }
  1016. }
  1017. final_rise_delay = get_best_delay(dev, host, rise_delay);
  1018. if (final_rise_delay.maxlen >= 12 ||
  1019. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1020. goto skip_fall;
  1021. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1022. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1023. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1024. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1025. i << MSDC_PAD_TUNE_DATRRDLY_S);
  1026. ret = mmc_send_tuning(mmc, opcode, &cmd_err);
  1027. if (!ret) {
  1028. fall_delay |= (1 << i);
  1029. } else if (cmd_err) {
  1030. /* in this case, retune response is needed */
  1031. ret = msdc_tune_response(dev, opcode);
  1032. if (ret)
  1033. break;
  1034. }
  1035. }
  1036. final_fall_delay = get_best_delay(dev, host, fall_delay);
  1037. skip_fall:
  1038. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1039. if (final_maxlen == final_rise_delay.maxlen) {
  1040. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1041. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1042. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1043. final_rise_delay.final_phase <<
  1044. MSDC_PAD_TUNE_DATRRDLY_S);
  1045. final_delay = final_rise_delay.final_phase;
  1046. } else {
  1047. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1048. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1049. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
  1050. final_fall_delay.final_phase <<
  1051. MSDC_PAD_TUNE_DATRRDLY_S);
  1052. final_delay = final_fall_delay.final_phase;
  1053. }
  1054. if (mmc->selected_mode == MMC_HS_200 ||
  1055. mmc->selected_mode == UHS_SDR104)
  1056. clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
  1057. host->hs200_write_int_delay <<
  1058. MSDC_PAD_TUNE_DATWRDLY_S);
  1059. dev_err(dev, "Final data pad delay: %x\n", final_delay);
  1060. return final_delay == 0xff ? -EIO : 0;
  1061. }
  1062. /*
  1063. * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
  1064. * together, which can save the tuning time.
  1065. */
  1066. static int msdc_tune_together(struct udevice *dev, u32 opcode)
  1067. {
  1068. struct msdc_plat *plat = dev_get_platdata(dev);
  1069. struct msdc_host *host = dev_get_priv(dev);
  1070. struct mmc *mmc = &plat->mmc;
  1071. u32 rise_delay = 0, fall_delay = 0;
  1072. struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
  1073. u8 final_delay, final_maxlen;
  1074. int i, ret;
  1075. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1076. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1077. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1078. msdc_set_cmd_delay(host, i);
  1079. msdc_set_data_delay(host, i);
  1080. ret = mmc_send_tuning(mmc, opcode, NULL);
  1081. if (!ret)
  1082. rise_delay |= (1 << i);
  1083. }
  1084. final_rise_delay = get_best_delay(dev, host, rise_delay);
  1085. if (final_rise_delay.maxlen >= 12 ||
  1086. (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
  1087. goto skip_fall;
  1088. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1089. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1090. for (i = 0; i < PAD_DELAY_MAX; i++) {
  1091. msdc_set_cmd_delay(host, i);
  1092. msdc_set_data_delay(host, i);
  1093. ret = mmc_send_tuning(mmc, opcode, NULL);
  1094. if (!ret)
  1095. fall_delay |= (1 << i);
  1096. }
  1097. final_fall_delay = get_best_delay(dev, host, fall_delay);
  1098. skip_fall:
  1099. final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
  1100. if (final_maxlen == final_rise_delay.maxlen) {
  1101. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1102. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1103. final_delay = final_rise_delay.final_phase;
  1104. } else {
  1105. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
  1106. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
  1107. final_delay = final_fall_delay.final_phase;
  1108. }
  1109. msdc_set_cmd_delay(host, final_delay);
  1110. msdc_set_data_delay(host, final_delay);
  1111. dev_info(dev, "Final pad delay: %x\n", final_delay);
  1112. return final_delay == 0xff ? -EIO : 0;
  1113. }
  1114. static int msdc_execute_tuning(struct udevice *dev, uint opcode)
  1115. {
  1116. struct msdc_plat *plat = dev_get_platdata(dev);
  1117. struct msdc_host *host = dev_get_priv(dev);
  1118. struct mmc *mmc = &plat->mmc;
  1119. int ret = 0;
  1120. if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
  1121. ret = msdc_tune_together(dev, opcode);
  1122. if (ret == -EIO) {
  1123. dev_err(dev, "Tune fail!\n");
  1124. return ret;
  1125. }
  1126. if (mmc->selected_mode == MMC_HS_400) {
  1127. clrbits_le32(&host->base->msdc_iocon,
  1128. MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
  1129. clrsetbits_le32(&host->base->pad_tune,
  1130. MSDC_PAD_TUNE_DATRRDLY_M, 0);
  1131. writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
  1132. /* for hs400 mode it must be set to 0 */
  1133. clrbits_le32(&host->base->patch_bit2,
  1134. MSDC_PB2_CFGCRCSTS);
  1135. host->hs400_mode = true;
  1136. }
  1137. goto tune_done;
  1138. }
  1139. if (mmc->selected_mode == MMC_HS_400)
  1140. ret = hs400_tune_response(dev, opcode);
  1141. else
  1142. ret = msdc_tune_response(dev, opcode);
  1143. if (ret == -EIO) {
  1144. dev_err(dev, "Tune response fail!\n");
  1145. return ret;
  1146. }
  1147. if (mmc->selected_mode != MMC_HS_400) {
  1148. ret = msdc_tune_data(dev, opcode);
  1149. if (ret == -EIO) {
  1150. dev_err(dev, "Tune data fail!\n");
  1151. return ret;
  1152. }
  1153. }
  1154. tune_done:
  1155. host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
  1156. host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
  1157. host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
  1158. return ret;
  1159. }
  1160. #endif
  1161. static void msdc_init_hw(struct msdc_host *host)
  1162. {
  1163. u32 val;
  1164. void __iomem *tune_reg = &host->base->pad_tune;
  1165. if (host->dev_comp->pad_tune0)
  1166. tune_reg = &host->base->pad_tune0;
  1167. /* Configure to MMC/SD mode, clock free running */
  1168. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
  1169. /* Use PIO mode */
  1170. setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
  1171. /* Reset */
  1172. msdc_reset_hw(host);
  1173. /* Enable/disable hw card detection according to fdt option */
  1174. if (host->builtin_cd)
  1175. clrsetbits_le32(&host->base->msdc_ps,
  1176. MSDC_PS_CDDBCE_M,
  1177. (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
  1178. MSDC_PS_CDEN);
  1179. else
  1180. clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
  1181. /* Clear all interrupts */
  1182. val = readl(&host->base->msdc_int);
  1183. writel(val, &host->base->msdc_int);
  1184. /* Enable data & cmd interrupts */
  1185. writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
  1186. writel(0, tune_reg);
  1187. writel(0, &host->base->msdc_iocon);
  1188. if (host->r_smpl)
  1189. setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1190. else
  1191. clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
  1192. writel(0x403c0046, &host->base->patch_bit0);
  1193. writel(0xffff4089, &host->base->patch_bit1);
  1194. if (host->dev_comp->stop_clk_fix)
  1195. clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
  1196. 3 << MSDC_PB1_STOP_DLY_S);
  1197. if (host->dev_comp->busy_check)
  1198. clrbits_le32(&host->base->patch_bit1, (1 << 7));
  1199. setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
  1200. if (host->dev_comp->async_fifo) {
  1201. clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
  1202. 3 << MSDC_PB2_RESPWAIT_S);
  1203. if (host->dev_comp->enhance_rx) {
  1204. if (host->top_base)
  1205. setbits_le32(&host->top_base->emmc_top_control,
  1206. SDC_RX_ENH_EN);
  1207. else
  1208. setbits_le32(&host->base->sdc_adv_cfg0,
  1209. SDC_RX_ENHANCE_EN);
  1210. } else {
  1211. clrsetbits_le32(&host->base->patch_bit2,
  1212. MSDC_PB2_RESPSTSENSEL_M,
  1213. 2 << MSDC_PB2_RESPSTSENSEL_S);
  1214. clrsetbits_le32(&host->base->patch_bit2,
  1215. MSDC_PB2_CRCSTSENSEL_M,
  1216. 2 << MSDC_PB2_CRCSTSENSEL_S);
  1217. }
  1218. /* use async fifo to avoid tune internal delay */
  1219. clrbits_le32(&host->base->patch_bit2,
  1220. MSDC_PB2_CFGRESP);
  1221. clrbits_le32(&host->base->patch_bit2,
  1222. MSDC_PB2_CFGCRCSTS);
  1223. }
  1224. if (host->dev_comp->data_tune) {
  1225. setbits_le32(tune_reg,
  1226. MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
  1227. clrsetbits_le32(&host->base->patch_bit0,
  1228. MSDC_INT_DAT_LATCH_CK_SEL_M,
  1229. host->latch_ck <<
  1230. MSDC_INT_DAT_LATCH_CK_SEL_S);
  1231. } else {
  1232. /* choose clock tune */
  1233. setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
  1234. }
  1235. /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
  1236. setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
  1237. /* disable detecting SDIO device interrupt function */
  1238. clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
  1239. /* Configure to default data timeout */
  1240. clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
  1241. 3 << SDC_CFG_DTOC_S);
  1242. if (host->dev_comp->stop_clk_fix) {
  1243. clrbits_le32(&host->base->sdc_fifo_cfg,
  1244. SDC_FIFO_CFG_WRVALIDSEL);
  1245. clrbits_le32(&host->base->sdc_fifo_cfg,
  1246. SDC_FIFO_CFG_RDVALIDSEL);
  1247. }
  1248. host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
  1249. host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
  1250. }
  1251. static void msdc_ungate_clock(struct msdc_host *host)
  1252. {
  1253. clk_enable(&host->src_clk);
  1254. clk_enable(&host->h_clk);
  1255. if (host->src_clk_cg.dev)
  1256. clk_enable(&host->src_clk_cg);
  1257. }
  1258. static int msdc_drv_probe(struct udevice *dev)
  1259. {
  1260. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1261. struct msdc_plat *plat = dev_get_platdata(dev);
  1262. struct msdc_host *host = dev_get_priv(dev);
  1263. struct mmc_config *cfg = &plat->cfg;
  1264. cfg->name = dev->name;
  1265. host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
  1266. host->src_clk_freq = clk_get_rate(&host->src_clk);
  1267. if (host->dev_comp->clk_div_bits == 8)
  1268. cfg->f_min = host->src_clk_freq / (4 * 255);
  1269. else
  1270. cfg->f_min = host->src_clk_freq / (4 * 4095);
  1271. cfg->b_max = 1024;
  1272. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1273. host->mmc = &plat->mmc;
  1274. host->timeout_ns = 100000000;
  1275. host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
  1276. #ifdef CONFIG_PINCTRL
  1277. pinctrl_select_state(dev, "default");
  1278. #endif
  1279. msdc_ungate_clock(host);
  1280. msdc_init_hw(host);
  1281. upriv->mmc = &plat->mmc;
  1282. return 0;
  1283. }
  1284. static int msdc_ofdata_to_platdata(struct udevice *dev)
  1285. {
  1286. struct msdc_plat *plat = dev_get_platdata(dev);
  1287. struct msdc_host *host = dev_get_priv(dev);
  1288. struct mmc_config *cfg = &plat->cfg;
  1289. fdt_addr_t base, top_base;
  1290. int ret;
  1291. base = dev_read_addr(dev);
  1292. if (base == FDT_ADDR_T_NONE)
  1293. return -EINVAL;
  1294. host->base = map_sysmem(base, 0);
  1295. top_base = dev_read_addr_index(dev, 1);
  1296. if (top_base == FDT_ADDR_T_NONE)
  1297. host->top_base = NULL;
  1298. else
  1299. host->top_base = map_sysmem(top_base, 0);
  1300. ret = mmc_of_parse(dev, cfg);
  1301. if (ret)
  1302. return ret;
  1303. ret = clk_get_by_name(dev, "source", &host->src_clk);
  1304. if (ret < 0)
  1305. return ret;
  1306. ret = clk_get_by_name(dev, "hclk", &host->h_clk);
  1307. if (ret < 0)
  1308. return ret;
  1309. clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
  1310. #if CONFIG_IS_ENABLED(DM_GPIO)
  1311. gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
  1312. gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
  1313. #endif
  1314. host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
  1315. host->hs200_cmd_int_delay =
  1316. dev_read_u32_default(dev, "cmd_int_delay", 0);
  1317. host->hs200_write_int_delay =
  1318. dev_read_u32_default(dev, "write_int_delay", 0);
  1319. host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
  1320. host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
  1321. host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
  1322. host->cd_active_high = dev_read_bool(dev, "cd-active-high");
  1323. return 0;
  1324. }
  1325. static int msdc_drv_bind(struct udevice *dev)
  1326. {
  1327. struct msdc_plat *plat = dev_get_platdata(dev);
  1328. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1329. }
  1330. static const struct dm_mmc_ops msdc_ops = {
  1331. .send_cmd = msdc_ops_send_cmd,
  1332. .set_ios = msdc_ops_set_ios,
  1333. .get_cd = msdc_ops_get_cd,
  1334. .get_wp = msdc_ops_get_wp,
  1335. #ifdef MMC_SUPPORTS_TUNING
  1336. .execute_tuning = msdc_execute_tuning,
  1337. #endif
  1338. };
  1339. static const struct msdc_compatible mt7620_compat = {
  1340. .clk_div_bits = 8,
  1341. .sclk_cycle_shift = 16,
  1342. .pad_tune0 = false,
  1343. .async_fifo = false,
  1344. .data_tune = false,
  1345. .busy_check = false,
  1346. .stop_clk_fix = false,
  1347. .enhance_rx = false
  1348. };
  1349. static const struct msdc_compatible mt7622_compat = {
  1350. .clk_div_bits = 12,
  1351. .pad_tune0 = true,
  1352. .async_fifo = true,
  1353. .data_tune = true,
  1354. .busy_check = true,
  1355. .stop_clk_fix = true,
  1356. };
  1357. static const struct msdc_compatible mt7623_compat = {
  1358. .clk_div_bits = 12,
  1359. .sclk_cycle_shift = 20,
  1360. .pad_tune0 = true,
  1361. .async_fifo = true,
  1362. .data_tune = true,
  1363. .busy_check = false,
  1364. .stop_clk_fix = false,
  1365. .enhance_rx = false
  1366. };
  1367. static const struct msdc_compatible mt8512_compat = {
  1368. .clk_div_bits = 12,
  1369. .sclk_cycle_shift = 20,
  1370. .pad_tune0 = true,
  1371. .async_fifo = true,
  1372. .data_tune = true,
  1373. .busy_check = true,
  1374. .stop_clk_fix = true,
  1375. };
  1376. static const struct msdc_compatible mt8516_compat = {
  1377. .clk_div_bits = 12,
  1378. .sclk_cycle_shift = 20,
  1379. .pad_tune0 = true,
  1380. .async_fifo = true,
  1381. .data_tune = true,
  1382. .busy_check = true,
  1383. .stop_clk_fix = true,
  1384. };
  1385. static const struct msdc_compatible mt8183_compat = {
  1386. .clk_div_bits = 12,
  1387. .sclk_cycle_shift = 20,
  1388. .pad_tune0 = true,
  1389. .async_fifo = true,
  1390. .data_tune = true,
  1391. .busy_check = true,
  1392. .stop_clk_fix = true,
  1393. };
  1394. static const struct udevice_id msdc_ids[] = {
  1395. { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
  1396. { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
  1397. { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
  1398. { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
  1399. { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
  1400. { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
  1401. {}
  1402. };
  1403. U_BOOT_DRIVER(mtk_sd_drv) = {
  1404. .name = "mtk_sd",
  1405. .id = UCLASS_MMC,
  1406. .of_match = msdc_ids,
  1407. .ofdata_to_platdata = msdc_ofdata_to_platdata,
  1408. .bind = msdc_drv_bind,
  1409. .probe = msdc_drv_probe,
  1410. .ops = &msdc_ops,
  1411. .platdata_auto_alloc_size = sizeof(struct msdc_plat),
  1412. .priv_auto_alloc_size = sizeof(struct msdc_host),
  1413. };