meson_gx_mmc.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <malloc.h>
  11. #include <pwrseq.h>
  12. #include <mmc.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/sd_emmc.h>
  16. #include <linux/delay.h>
  17. #include <linux/log2.h>
  18. static inline void *get_regbase(const struct mmc *mmc)
  19. {
  20. struct meson_mmc_platdata *pdata = mmc->priv;
  21. return pdata->regbase;
  22. }
  23. static inline uint32_t meson_read(struct mmc *mmc, int offset)
  24. {
  25. return readl(get_regbase(mmc) + offset);
  26. }
  27. static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
  28. {
  29. writel(val, get_regbase(mmc) + offset);
  30. }
  31. static void meson_mmc_config_clock(struct mmc *mmc)
  32. {
  33. uint32_t meson_mmc_clk = 0;
  34. unsigned int clk, clk_src, clk_div;
  35. if (!mmc->clock)
  36. return;
  37. /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
  38. if (mmc->clock > 16000000) {
  39. clk = SD_EMMC_CLKSRC_DIV2;
  40. clk_src = CLK_SRC_DIV2;
  41. } else {
  42. clk = SD_EMMC_CLKSRC_24M;
  43. clk_src = CLK_SRC_24M;
  44. }
  45. clk_div = DIV_ROUND_UP(clk, mmc->clock);
  46. /* 180 phase core clock */
  47. meson_mmc_clk |= CLK_CO_PHASE_180;
  48. /* 180 phase tx clock */
  49. meson_mmc_clk |= CLK_TX_PHASE_000;
  50. /* clock settings */
  51. meson_mmc_clk |= clk_src;
  52. meson_mmc_clk |= clk_div;
  53. meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
  54. }
  55. static int meson_dm_mmc_set_ios(struct udevice *dev)
  56. {
  57. struct mmc *mmc = mmc_get_mmc_dev(dev);
  58. uint32_t meson_mmc_cfg;
  59. meson_mmc_config_clock(mmc);
  60. meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  61. meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
  62. if (mmc->bus_width == 1)
  63. meson_mmc_cfg |= CFG_BUS_WIDTH_1;
  64. else if (mmc->bus_width == 4)
  65. meson_mmc_cfg |= CFG_BUS_WIDTH_4;
  66. else if (mmc->bus_width == 8)
  67. meson_mmc_cfg |= CFG_BUS_WIDTH_8;
  68. else
  69. return -EINVAL;
  70. /* 512 bytes block length */
  71. meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
  72. meson_mmc_cfg |= CFG_BL_LEN_512;
  73. /* Response timeout 256 clk */
  74. meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
  75. meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
  76. /* Command-command gap 16 clk */
  77. meson_mmc_cfg &= ~CFG_RC_CC_MASK;
  78. meson_mmc_cfg |= CFG_RC_CC_16;
  79. meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
  80. return 0;
  81. }
  82. static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
  83. struct mmc_cmd *cmd)
  84. {
  85. uint32_t meson_mmc_cmd = 0, cfg;
  86. meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
  87. if (cmd->resp_type & MMC_RSP_PRESENT) {
  88. if (cmd->resp_type & MMC_RSP_136)
  89. meson_mmc_cmd |= CMD_CFG_RESP_128;
  90. if (cmd->resp_type & MMC_RSP_BUSY)
  91. meson_mmc_cmd |= CMD_CFG_R1B;
  92. if (!(cmd->resp_type & MMC_RSP_CRC))
  93. meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
  94. } else {
  95. meson_mmc_cmd |= CMD_CFG_NO_RESP;
  96. }
  97. if (data) {
  98. cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  99. cfg &= ~CFG_BL_LEN_MASK;
  100. cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
  101. meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
  102. if (data->flags == MMC_DATA_WRITE)
  103. meson_mmc_cmd |= CMD_CFG_DATA_WR;
  104. meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
  105. data->blocks;
  106. }
  107. meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
  108. CMD_CFG_END_OF_CHAIN;
  109. meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
  110. }
  111. static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
  112. {
  113. struct meson_mmc_platdata *pdata = mmc->priv;
  114. unsigned int data_size;
  115. uint32_t data_addr = 0;
  116. if (data) {
  117. data_size = data->blocks * data->blocksize;
  118. if (data->flags == MMC_DATA_READ) {
  119. data_addr = (ulong) data->dest;
  120. invalidate_dcache_range(data_addr,
  121. data_addr + data_size);
  122. } else {
  123. pdata->w_buf = calloc(data_size, sizeof(char));
  124. data_addr = (ulong) pdata->w_buf;
  125. memcpy(pdata->w_buf, data->src, data_size);
  126. flush_dcache_range(data_addr, data_addr + data_size);
  127. }
  128. }
  129. meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
  130. }
  131. static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
  132. {
  133. if (cmd->resp_type & MMC_RSP_136) {
  134. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
  135. cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
  136. cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
  137. cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  138. } else {
  139. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  140. }
  141. }
  142. static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  143. struct mmc_data *data)
  144. {
  145. struct mmc *mmc = mmc_get_mmc_dev(dev);
  146. struct meson_mmc_platdata *pdata = mmc->priv;
  147. uint32_t status;
  148. ulong start;
  149. int ret = 0;
  150. /* max block size supported by chip is 512 byte */
  151. if (data && data->blocksize > 512)
  152. return -EINVAL;
  153. meson_mmc_setup_cmd(mmc, data, cmd);
  154. meson_mmc_setup_addr(mmc, data);
  155. meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
  156. /* use 10s timeout */
  157. start = get_timer(0);
  158. do {
  159. status = meson_read(mmc, MESON_SD_EMMC_STATUS);
  160. } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
  161. if (!(status & STATUS_END_OF_CHAIN))
  162. ret = -ETIMEDOUT;
  163. else if (status & STATUS_RESP_TIMEOUT)
  164. ret = -ETIMEDOUT;
  165. else if (status & STATUS_ERR_MASK)
  166. ret = -EIO;
  167. meson_mmc_read_response(mmc, cmd);
  168. if (data && data->flags == MMC_DATA_WRITE)
  169. free(pdata->w_buf);
  170. /* reset status bits */
  171. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  172. return ret;
  173. }
  174. static const struct dm_mmc_ops meson_dm_mmc_ops = {
  175. .send_cmd = meson_dm_mmc_send_cmd,
  176. .set_ios = meson_dm_mmc_set_ios,
  177. };
  178. static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
  179. {
  180. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  181. fdt_addr_t addr;
  182. addr = dev_read_addr(dev);
  183. if (addr == FDT_ADDR_T_NONE)
  184. return -EINVAL;
  185. pdata->regbase = (void *)addr;
  186. return 0;
  187. }
  188. static int meson_mmc_probe(struct udevice *dev)
  189. {
  190. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  191. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  192. struct mmc *mmc = &pdata->mmc;
  193. struct mmc_config *cfg = &pdata->cfg;
  194. struct clk_bulk clocks;
  195. uint32_t val;
  196. int ret;
  197. #ifdef CONFIG_PWRSEQ
  198. struct udevice *pwr_dev;
  199. #endif
  200. /* Enable the clocks feeding the MMC controller */
  201. ret = clk_get_bulk(dev, &clocks);
  202. if (ret)
  203. return ret;
  204. ret = clk_enable_bulk(&clocks);
  205. if (ret)
  206. return ret;
  207. cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
  208. MMC_VDD_31_32 | MMC_VDD_165_195;
  209. cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
  210. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  211. cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
  212. cfg->f_max = 100000000; /* 100 MHz */
  213. cfg->b_max = 511; /* max 512 - 1 blocks */
  214. cfg->name = dev->name;
  215. mmc->priv = pdata;
  216. upriv->mmc = mmc;
  217. mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
  218. #ifdef CONFIG_PWRSEQ
  219. /* Enable power if needed */
  220. ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
  221. &pwr_dev);
  222. if (!ret) {
  223. ret = pwrseq_set_power(pwr_dev, true);
  224. if (ret)
  225. return ret;
  226. }
  227. #endif
  228. /* reset all status bits */
  229. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  230. /* disable interrupts */
  231. meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
  232. /* enable auto clock mode */
  233. val = meson_read(mmc, MESON_SD_EMMC_CFG);
  234. val &= ~CFG_SDCLK_ALWAYS_ON;
  235. val |= CFG_AUTO_CLK;
  236. meson_write(mmc, val, MESON_SD_EMMC_CFG);
  237. return 0;
  238. }
  239. int meson_mmc_bind(struct udevice *dev)
  240. {
  241. struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
  242. return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
  243. }
  244. static const struct udevice_id meson_mmc_match[] = {
  245. { .compatible = "amlogic,meson-gx-mmc" },
  246. { .compatible = "amlogic,meson-axg-mmc" },
  247. { /* sentinel */ }
  248. };
  249. U_BOOT_DRIVER(meson_mmc) = {
  250. .name = "meson_gx_mmc",
  251. .id = UCLASS_MMC,
  252. .of_match = meson_mmc_match,
  253. .ops = &meson_dm_mmc_ops,
  254. .probe = meson_mmc_probe,
  255. .bind = meson_mmc_bind,
  256. .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
  257. .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
  258. };
  259. #ifdef CONFIG_PWRSEQ
  260. static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
  261. {
  262. struct gpio_desc reset;
  263. int ret;
  264. ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
  265. if (ret)
  266. return ret;
  267. dm_gpio_set_value(&reset, 1);
  268. udelay(1);
  269. dm_gpio_set_value(&reset, 0);
  270. udelay(200);
  271. return 0;
  272. }
  273. static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
  274. .set_power = meson_mmc_pwrseq_set_power,
  275. };
  276. static const struct udevice_id meson_mmc_pwrseq_ids[] = {
  277. { .compatible = "mmc-pwrseq-emmc" },
  278. { }
  279. };
  280. U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
  281. .name = "mmc_pwrseq_emmc",
  282. .id = UCLASS_PWRSEQ,
  283. .of_match = meson_mmc_pwrseq_ids,
  284. .ops = &meson_mmc_pwrseq_ops,
  285. };
  286. #endif