clk-uclass.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dt-structs.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/devres.h>
  18. #include <dm/read.h>
  19. #include <linux/bug.h>
  20. #include <linux/clk-provider.h>
  21. #include <linux/err.h>
  22. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  23. {
  24. return (const struct clk_ops *)dev->driver->ops;
  25. }
  26. struct clk *dev_get_clk_ptr(struct udevice *dev)
  27. {
  28. return (struct clk *)dev_get_uclass_priv(dev);
  29. }
  30. #if CONFIG_IS_ENABLED(OF_CONTROL)
  31. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  32. int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells,
  33. struct clk *clk)
  34. {
  35. int ret;
  36. ret = device_get_by_driver_info((struct driver_info *)cells->node,
  37. &clk->dev);
  38. if (ret)
  39. return ret;
  40. clk->id = cells->arg[0];
  41. return 0;
  42. }
  43. # else
  44. static int clk_of_xlate_default(struct clk *clk,
  45. struct ofnode_phandle_args *args)
  46. {
  47. debug("%s(clk=%p)\n", __func__, clk);
  48. if (args->args_count > 1) {
  49. debug("Invaild args_count: %d\n", args->args_count);
  50. return -EINVAL;
  51. }
  52. if (args->args_count)
  53. clk->id = args->args[0];
  54. else
  55. clk->id = 0;
  56. clk->data = 0;
  57. return 0;
  58. }
  59. static int clk_get_by_index_tail(int ret, ofnode node,
  60. struct ofnode_phandle_args *args,
  61. const char *list_name, int index,
  62. struct clk *clk)
  63. {
  64. struct udevice *dev_clk;
  65. const struct clk_ops *ops;
  66. assert(clk);
  67. clk->dev = NULL;
  68. if (ret)
  69. goto err;
  70. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  71. if (ret) {
  72. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  73. __func__, ret);
  74. return ret;
  75. }
  76. clk->dev = dev_clk;
  77. ops = clk_dev_ops(dev_clk);
  78. if (ops->of_xlate)
  79. ret = ops->of_xlate(clk, args);
  80. else
  81. ret = clk_of_xlate_default(clk, args);
  82. if (ret) {
  83. debug("of_xlate() failed: %d\n", ret);
  84. return ret;
  85. }
  86. return clk_request(dev_clk, clk);
  87. err:
  88. debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  89. __func__, ofnode_get_name(node), list_name, index, ret);
  90. return ret;
  91. }
  92. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  93. int index, struct clk *clk)
  94. {
  95. int ret;
  96. struct ofnode_phandle_args args;
  97. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  98. assert(clk);
  99. clk->dev = NULL;
  100. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  101. index, &args);
  102. if (ret) {
  103. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  104. __func__, ret);
  105. return ret;
  106. }
  107. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  108. index, clk);
  109. }
  110. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  111. {
  112. struct ofnode_phandle_args args;
  113. int ret;
  114. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  115. index, &args);
  116. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  117. index, clk);
  118. }
  119. int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
  120. {
  121. struct ofnode_phandle_args args;
  122. int ret;
  123. ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
  124. index, &args);
  125. return clk_get_by_index_tail(ret, node, &args, "clocks",
  126. index, clk);
  127. }
  128. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  129. {
  130. int i, ret, err, count;
  131. bulk->count = 0;
  132. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  133. if (count < 1)
  134. return count;
  135. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  136. if (!bulk->clks)
  137. return -ENOMEM;
  138. for (i = 0; i < count; i++) {
  139. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  140. if (ret < 0)
  141. goto bulk_get_err;
  142. ++bulk->count;
  143. }
  144. return 0;
  145. bulk_get_err:
  146. err = clk_release_all(bulk->clks, bulk->count);
  147. if (err)
  148. debug("%s: could release all clocks for %p\n",
  149. __func__, dev);
  150. return ret;
  151. }
  152. static struct clk *clk_set_default_get_by_id(struct clk *clk)
  153. {
  154. struct clk *c = clk;
  155. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  156. int ret = clk_get_by_id(clk->id, &c);
  157. if (ret) {
  158. debug("%s(): could not get parent clock pointer, id %lu\n",
  159. __func__, clk->id);
  160. ERR_PTR(ret);
  161. }
  162. }
  163. return c;
  164. }
  165. static int clk_set_default_parents(struct udevice *dev, int stage)
  166. {
  167. struct clk clk, parent_clk, *c, *p;
  168. int index;
  169. int num_parents;
  170. int ret;
  171. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  172. "#clock-cells");
  173. if (num_parents < 0) {
  174. debug("%s: could not read assigned-clock-parents for %p\n",
  175. __func__, dev);
  176. return 0;
  177. }
  178. for (index = 0; index < num_parents; index++) {
  179. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  180. index, &parent_clk);
  181. /* If -ENOENT, this is a no-op entry */
  182. if (ret == -ENOENT)
  183. continue;
  184. if (ret) {
  185. debug("%s: could not get parent clock %d for %s\n",
  186. __func__, index, dev_read_name(dev));
  187. return ret;
  188. }
  189. p = clk_set_default_get_by_id(&parent_clk);
  190. if (IS_ERR(p))
  191. return PTR_ERR(p);
  192. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  193. index, &clk);
  194. if (ret) {
  195. debug("%s: could not get assigned clock %d for %s\n",
  196. __func__, index, dev_read_name(dev));
  197. return ret;
  198. }
  199. /* This is clk provider device trying to reparent itself
  200. * It cannot be done right now but need to wait after the
  201. * device is probed
  202. */
  203. if (stage == 0 && clk.dev == dev)
  204. continue;
  205. if (stage > 0 && clk.dev != dev)
  206. /* do not setup twice the parent clocks */
  207. continue;
  208. c = clk_set_default_get_by_id(&clk);
  209. if (IS_ERR(c))
  210. return PTR_ERR(c);
  211. ret = clk_set_parent(c, p);
  212. /*
  213. * Not all drivers may support clock-reparenting (as of now).
  214. * Ignore errors due to this.
  215. */
  216. if (ret == -ENOSYS)
  217. continue;
  218. if (ret < 0) {
  219. debug("%s: failed to reparent clock %d for %s\n",
  220. __func__, index, dev_read_name(dev));
  221. return ret;
  222. }
  223. }
  224. return 0;
  225. }
  226. static int clk_set_default_rates(struct udevice *dev, int stage)
  227. {
  228. struct clk clk, *c;
  229. int index;
  230. int num_rates;
  231. int size;
  232. int ret = 0;
  233. u32 *rates = NULL;
  234. size = dev_read_size(dev, "assigned-clock-rates");
  235. if (size < 0)
  236. return 0;
  237. num_rates = size / sizeof(u32);
  238. rates = calloc(num_rates, sizeof(u32));
  239. if (!rates)
  240. return -ENOMEM;
  241. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  242. if (ret)
  243. goto fail;
  244. for (index = 0; index < num_rates; index++) {
  245. /* If 0 is passed, this is a no-op */
  246. if (!rates[index])
  247. continue;
  248. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  249. index, &clk);
  250. if (ret) {
  251. debug("%s: could not get assigned clock %d for %s\n",
  252. __func__, index, dev_read_name(dev));
  253. continue;
  254. }
  255. /* This is clk provider device trying to program itself
  256. * It cannot be done right now but need to wait after the
  257. * device is probed
  258. */
  259. if (stage == 0 && clk.dev == dev)
  260. continue;
  261. if (stage > 0 && clk.dev != dev)
  262. /* do not setup twice the parent clocks */
  263. continue;
  264. c = clk_set_default_get_by_id(&clk);
  265. if (IS_ERR(c))
  266. return PTR_ERR(c);
  267. ret = clk_set_rate(c, rates[index]);
  268. if (ret < 0) {
  269. debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
  270. __func__, index, clk.id, dev_read_name(dev));
  271. break;
  272. }
  273. }
  274. fail:
  275. free(rates);
  276. return ret;
  277. }
  278. int clk_set_defaults(struct udevice *dev, int stage)
  279. {
  280. int ret;
  281. if (!dev_of_valid(dev))
  282. return 0;
  283. /* If this not in SPL and pre-reloc state, don't take any action. */
  284. if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
  285. return 0;
  286. debug("%s(%s)\n", __func__, dev_read_name(dev));
  287. ret = clk_set_default_parents(dev, stage);
  288. if (ret)
  289. return ret;
  290. ret = clk_set_default_rates(dev, stage);
  291. if (ret < 0)
  292. return ret;
  293. return 0;
  294. }
  295. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  296. {
  297. int index;
  298. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  299. clk->dev = NULL;
  300. index = dev_read_stringlist_search(dev, "clock-names", name);
  301. if (index < 0) {
  302. debug("fdt_stringlist_search() failed: %d\n", index);
  303. return index;
  304. }
  305. return clk_get_by_index(dev, index, clk);
  306. }
  307. # endif /* OF_PLATDATA */
  308. int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
  309. {
  310. int index;
  311. debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
  312. ofnode_get_name(node), name, clk);
  313. clk->dev = NULL;
  314. index = ofnode_stringlist_search(node, "clock-names", name);
  315. if (index < 0) {
  316. debug("fdt_stringlist_search() failed: %d\n", index);
  317. return index;
  318. }
  319. return clk_get_by_index_nodev(node, index, clk);
  320. }
  321. int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
  322. {
  323. int ret;
  324. ret = clk_get_by_name_nodev(node, name, clk);
  325. if (ret == -ENODATA)
  326. return 0;
  327. return ret;
  328. }
  329. int clk_release_all(struct clk *clk, int count)
  330. {
  331. int i, ret;
  332. for (i = 0; i < count; i++) {
  333. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  334. /* check if clock has been previously requested */
  335. if (!clk[i].dev)
  336. continue;
  337. ret = clk_disable(&clk[i]);
  338. if (ret && ret != -ENOSYS)
  339. return ret;
  340. ret = clk_free(&clk[i]);
  341. if (ret && ret != -ENOSYS)
  342. return ret;
  343. }
  344. return 0;
  345. }
  346. #endif /* OF_CONTROL */
  347. int clk_request(struct udevice *dev, struct clk *clk)
  348. {
  349. const struct clk_ops *ops;
  350. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  351. if (!clk)
  352. return 0;
  353. ops = clk_dev_ops(dev);
  354. clk->dev = dev;
  355. if (!ops->request)
  356. return 0;
  357. return ops->request(clk);
  358. }
  359. int clk_free(struct clk *clk)
  360. {
  361. const struct clk_ops *ops;
  362. debug("%s(clk=%p)\n", __func__, clk);
  363. if (!clk_valid(clk))
  364. return 0;
  365. ops = clk_dev_ops(clk->dev);
  366. if (!ops->rfree)
  367. return 0;
  368. return ops->rfree(clk);
  369. }
  370. ulong clk_get_rate(struct clk *clk)
  371. {
  372. const struct clk_ops *ops;
  373. debug("%s(clk=%p)\n", __func__, clk);
  374. if (!clk_valid(clk))
  375. return 0;
  376. ops = clk_dev_ops(clk->dev);
  377. if (!ops->get_rate)
  378. return -ENOSYS;
  379. return ops->get_rate(clk);
  380. }
  381. struct clk *clk_get_parent(struct clk *clk)
  382. {
  383. struct udevice *pdev;
  384. struct clk *pclk;
  385. debug("%s(clk=%p)\n", __func__, clk);
  386. if (!clk_valid(clk))
  387. return NULL;
  388. pdev = dev_get_parent(clk->dev);
  389. pclk = dev_get_clk_ptr(pdev);
  390. if (!pclk)
  391. return ERR_PTR(-ENODEV);
  392. return pclk;
  393. }
  394. long long clk_get_parent_rate(struct clk *clk)
  395. {
  396. const struct clk_ops *ops;
  397. struct clk *pclk;
  398. debug("%s(clk=%p)\n", __func__, clk);
  399. if (!clk_valid(clk))
  400. return 0;
  401. pclk = clk_get_parent(clk);
  402. if (IS_ERR(pclk))
  403. return -ENODEV;
  404. ops = clk_dev_ops(pclk->dev);
  405. if (!ops->get_rate)
  406. return -ENOSYS;
  407. /* Read the 'rate' if not already set or if proper flag set*/
  408. if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
  409. pclk->rate = clk_get_rate(pclk);
  410. return pclk->rate;
  411. }
  412. ulong clk_set_rate(struct clk *clk, ulong rate)
  413. {
  414. const struct clk_ops *ops;
  415. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  416. if (!clk_valid(clk))
  417. return 0;
  418. ops = clk_dev_ops(clk->dev);
  419. if (!ops->set_rate)
  420. return -ENOSYS;
  421. return ops->set_rate(clk, rate);
  422. }
  423. int clk_set_parent(struct clk *clk, struct clk *parent)
  424. {
  425. const struct clk_ops *ops;
  426. int ret;
  427. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  428. if (!clk_valid(clk))
  429. return 0;
  430. ops = clk_dev_ops(clk->dev);
  431. if (!ops->set_parent)
  432. return -ENOSYS;
  433. ret = ops->set_parent(clk, parent);
  434. if (ret)
  435. return ret;
  436. if (CONFIG_IS_ENABLED(CLK_CCF))
  437. ret = device_reparent(clk->dev, parent->dev);
  438. return ret;
  439. }
  440. int clk_enable(struct clk *clk)
  441. {
  442. const struct clk_ops *ops;
  443. struct clk *clkp = NULL;
  444. int ret;
  445. debug("%s(clk=%p)\n", __func__, clk);
  446. if (!clk_valid(clk))
  447. return 0;
  448. ops = clk_dev_ops(clk->dev);
  449. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  450. /* Take id 0 as a non-valid clk, such as dummy */
  451. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  452. if (clkp->enable_count) {
  453. clkp->enable_count++;
  454. return 0;
  455. }
  456. if (clkp->dev->parent &&
  457. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  458. ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
  459. if (ret) {
  460. printf("Enable %s failed\n",
  461. clkp->dev->parent->name);
  462. return ret;
  463. }
  464. }
  465. }
  466. if (ops->enable) {
  467. ret = ops->enable(clk);
  468. if (ret) {
  469. printf("Enable %s failed\n", clk->dev->name);
  470. return ret;
  471. }
  472. }
  473. if (clkp)
  474. clkp->enable_count++;
  475. } else {
  476. if (!ops->enable)
  477. return -ENOSYS;
  478. return ops->enable(clk);
  479. }
  480. return 0;
  481. }
  482. int clk_enable_bulk(struct clk_bulk *bulk)
  483. {
  484. int i, ret;
  485. for (i = 0; i < bulk->count; i++) {
  486. ret = clk_enable(&bulk->clks[i]);
  487. if (ret < 0 && ret != -ENOSYS)
  488. return ret;
  489. }
  490. return 0;
  491. }
  492. int clk_disable(struct clk *clk)
  493. {
  494. const struct clk_ops *ops;
  495. struct clk *clkp = NULL;
  496. int ret;
  497. debug("%s(clk=%p)\n", __func__, clk);
  498. if (!clk_valid(clk))
  499. return 0;
  500. ops = clk_dev_ops(clk->dev);
  501. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  502. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  503. if (clkp->flags & CLK_IS_CRITICAL)
  504. return 0;
  505. if (clkp->enable_count == 0) {
  506. printf("clk %s already disabled\n",
  507. clkp->dev->name);
  508. return 0;
  509. }
  510. if (--clkp->enable_count > 0)
  511. return 0;
  512. }
  513. if (ops->disable) {
  514. ret = ops->disable(clk);
  515. if (ret)
  516. return ret;
  517. }
  518. if (clkp && clkp->dev->parent &&
  519. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  520. ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
  521. if (ret) {
  522. printf("Disable %s failed\n",
  523. clkp->dev->parent->name);
  524. return ret;
  525. }
  526. }
  527. } else {
  528. if (!ops->disable)
  529. return -ENOSYS;
  530. return ops->disable(clk);
  531. }
  532. return 0;
  533. }
  534. int clk_disable_bulk(struct clk_bulk *bulk)
  535. {
  536. int i, ret;
  537. for (i = 0; i < bulk->count; i++) {
  538. ret = clk_disable(&bulk->clks[i]);
  539. if (ret < 0 && ret != -ENOSYS)
  540. return ret;
  541. }
  542. return 0;
  543. }
  544. int clk_get_by_id(ulong id, struct clk **clkp)
  545. {
  546. struct udevice *dev;
  547. struct uclass *uc;
  548. int ret;
  549. ret = uclass_get(UCLASS_CLK, &uc);
  550. if (ret)
  551. return ret;
  552. uclass_foreach_dev(dev, uc) {
  553. struct clk *clk = dev_get_clk_ptr(dev);
  554. if (clk && clk->id == id) {
  555. *clkp = clk;
  556. return 0;
  557. }
  558. }
  559. return -ENOENT;
  560. }
  561. bool clk_is_match(const struct clk *p, const struct clk *q)
  562. {
  563. /* trivial case: identical struct clk's or both NULL */
  564. if (p == q)
  565. return true;
  566. /* trivial case #2: on the clk pointer is NULL */
  567. if (!p || !q)
  568. return false;
  569. /* same device, id and data */
  570. if (p->dev == q->dev && p->id == q->id && p->data == q->data)
  571. return true;
  572. return false;
  573. }
  574. static void devm_clk_release(struct udevice *dev, void *res)
  575. {
  576. clk_free(res);
  577. }
  578. static int devm_clk_match(struct udevice *dev, void *res, void *data)
  579. {
  580. return res == data;
  581. }
  582. struct clk *devm_clk_get(struct udevice *dev, const char *id)
  583. {
  584. int rc;
  585. struct clk *clk;
  586. clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
  587. if (unlikely(!clk))
  588. return ERR_PTR(-ENOMEM);
  589. rc = clk_get_by_name(dev, id, clk);
  590. if (rc)
  591. return ERR_PTR(rc);
  592. devres_add(dev, clk);
  593. return clk;
  594. }
  595. struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
  596. {
  597. struct clk *clk = devm_clk_get(dev, id);
  598. if (PTR_ERR(clk) == -ENODATA)
  599. return NULL;
  600. return clk;
  601. }
  602. void devm_clk_put(struct udevice *dev, struct clk *clk)
  603. {
  604. int rc;
  605. if (!clk)
  606. return;
  607. rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
  608. WARN_ON(rc);
  609. }
  610. int clk_uclass_post_probe(struct udevice *dev)
  611. {
  612. /*
  613. * when a clock provider is probed. Call clk_set_defaults()
  614. * also after the device is probed. This takes care of cases
  615. * where the DT is used to setup default parents and rates
  616. * using assigned-clocks
  617. */
  618. clk_set_defaults(dev, 1);
  619. return 0;
  620. }
  621. UCLASS_DRIVER(clk) = {
  622. .id = UCLASS_CLK,
  623. .name = "clk",
  624. .post_probe = clk_uclass_post_probe,
  625. };