pmc.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2016 Atmel Corporation
  4. * Wenyou.Yang <wenyou.yang@atmel.com>
  5. */
  6. #ifndef __AT91_PMC_H__
  7. #define __AT91_PMC_H__
  8. #include <linux/bitops.h>
  9. #include <linux/io.h>
  10. /* Keep a range of 256 available clocks for every clock type. */
  11. #define AT91_TO_CLK_ID(_t, _i) (((_t) << 8) | ((_i) & 0xff))
  12. #define AT91_CLK_ID_TO_DID(_i) ((_i) & 0xff)
  13. struct clk_range {
  14. unsigned long min;
  15. unsigned long max;
  16. };
  17. struct clk_master_layout {
  18. u32 offset;
  19. u32 mask;
  20. u8 pres_shift;
  21. };
  22. extern const struct clk_master_layout at91rm9200_master_layout;
  23. extern const struct clk_master_layout at91sam9x5_master_layout;
  24. struct clk_master_characteristics {
  25. struct clk_range output;
  26. u32 divisors[4];
  27. u8 have_div3_pres;
  28. };
  29. struct clk_pll_characteristics {
  30. struct clk_range input;
  31. int num_output;
  32. const struct clk_range *output;
  33. u16 *icpll;
  34. u8 *out;
  35. u8 upll : 1;
  36. };
  37. struct clk_pll_layout {
  38. u32 pllr_mask;
  39. u32 mul_mask;
  40. u32 frac_mask;
  41. u32 div_mask;
  42. u32 endiv_mask;
  43. u8 mul_shift;
  44. u8 frac_shift;
  45. u8 div_shift;
  46. u8 endiv_shift;
  47. };
  48. struct clk_programmable_layout {
  49. u8 pres_mask;
  50. u8 pres_shift;
  51. u8 css_mask;
  52. u8 have_slck_mck;
  53. u8 is_pres_direct;
  54. };
  55. struct clk_pcr_layout {
  56. u32 offset;
  57. u32 cmd;
  58. u32 div_mask;
  59. u32 gckcss_mask;
  60. u32 pid_mask;
  61. };
  62. extern const struct clk_programmable_layout at91rm9200_programmable_layout;
  63. extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
  64. extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
  65. extern const struct clk_ops at91_clk_ops;
  66. struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,
  67. const char *parent_name);
  68. struct clk *at91_clk_main_osc(void __iomem *reg, const char *name,
  69. const char *parent_name, bool bypass);
  70. struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name,
  71. const char *parent_name);
  72. struct clk *at91_clk_sam9x5_main(void __iomem *reg, const char *name,
  73. const char * const *parent_names, int num_parents,
  74. const u32 *mux_table, int type);
  75. struct clk *
  76. sam9x60_clk_register_div_pll(void __iomem *base, const char *name,
  77. const char *parent_name, u8 id,
  78. const struct clk_pll_characteristics *characteristics,
  79. const struct clk_pll_layout *layout, bool critical);
  80. struct clk *
  81. sam9x60_clk_register_frac_pll(void __iomem *base, const char *name,
  82. const char *parent_name, u8 id,
  83. const struct clk_pll_characteristics *characteristics,
  84. const struct clk_pll_layout *layout, bool critical);
  85. struct clk *
  86. at91_clk_register_master(void __iomem *base, const char *name,
  87. const char * const *parent_names, int num_parents,
  88. const struct clk_master_layout *layout,
  89. const struct clk_master_characteristics *characteristics,
  90. const u32 *mux_table);
  91. struct clk *
  92. at91_clk_sama7g5_register_master(void __iomem *base, const char *name,
  93. const char * const *parent_names, int num_parents,
  94. const u32 *mux_table, const u32 *clk_mux_table,
  95. bool critical, u8 id);
  96. struct clk *
  97. at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
  98. const char *name, const char *parent_name);
  99. struct clk *
  100. at91_clk_sama7g5_register_utmi(void __iomem *base, const char *name,
  101. const char *parent_name);
  102. struct clk *
  103. at91_clk_register_programmable(void __iomem *base, const char *name,
  104. const char * const *parent_names, u8 num_parents, u8 id,
  105. const struct clk_programmable_layout *layout,
  106. const u32 *clk_mux_table, const u32 *mux_table);
  107. struct clk *
  108. at91_clk_register_system(void __iomem *base, const char *name,
  109. const char *parent_name, u8 id);
  110. struct clk *
  111. at91_clk_register_peripheral(void __iomem *base, const char *name,
  112. const char *parent_name, u32 id);
  113. struct clk *
  114. at91_clk_register_sam9x5_peripheral(void __iomem *base,
  115. const struct clk_pcr_layout *layout,
  116. const char *name, const char *parent_name,
  117. u32 id, const struct clk_range *range);
  118. struct clk *
  119. at91_clk_register_generic(void __iomem *base,
  120. const struct clk_pcr_layout *layout, const char *name,
  121. const char * const *parent_names,
  122. const u32 *clk_mux_table, const u32 *mux_table,
  123. u8 num_parents, u8 id, const struct clk_range *range);
  124. int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
  125. int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
  126. void pmc_read(void __iomem *base, unsigned int off, unsigned int *val);
  127. void pmc_write(void __iomem *base, unsigned int off, unsigned int val);
  128. void pmc_update_bits(void __iomem *base, unsigned int off, unsigned int mask,
  129. unsigned int bits);
  130. #endif