compat.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Compatible code for non CCF AT91 platforms.
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/lists.h>
  13. #include <dm/util.h>
  14. #include <mach/at91_pmc.h>
  15. #include <mach/at91_sfr.h>
  16. #include <regmap.h>
  17. #include <syscon.h>
  18. #include "pmc.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. struct pmc_platdata {
  21. struct at91_pmc *reg_base;
  22. struct regmap *regmap_sfr;
  23. };
  24. static const struct udevice_id at91_pmc_match[] = {
  25. { .compatible = "atmel,at91rm9200-pmc" },
  26. { .compatible = "atmel,at91sam9260-pmc" },
  27. { .compatible = "atmel,at91sam9g45-pmc" },
  28. { .compatible = "atmel,at91sam9n12-pmc" },
  29. { .compatible = "atmel,at91sam9x5-pmc" },
  30. { .compatible = "atmel,sama5d3-pmc" },
  31. { .compatible = "atmel,sama5d2-pmc" },
  32. {}
  33. };
  34. U_BOOT_DRIVER(at91_pmc) = {
  35. .name = "at91-pmc",
  36. .id = UCLASS_SIMPLE_BUS,
  37. .of_match = at91_pmc_match,
  38. };
  39. static int at91_pmc_core_probe(struct udevice *dev)
  40. {
  41. struct pmc_platdata *plat = dev_get_platdata(dev);
  42. dev = dev_get_parent(dev);
  43. plat->reg_base = dev_read_addr_ptr(dev);
  44. return 0;
  45. }
  46. /**
  47. * at91_clk_sub_device_bind() - for the at91 clock driver
  48. * Recursively bind its children as clk devices.
  49. *
  50. * @return: 0 on success, or negative error code on failure
  51. */
  52. int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
  53. {
  54. const void *fdt = gd->fdt_blob;
  55. int offset = dev_of_offset(dev);
  56. bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  57. const char *name;
  58. int ret;
  59. for (offset = fdt_first_subnode(fdt, offset);
  60. offset > 0;
  61. offset = fdt_next_subnode(fdt, offset)) {
  62. if (pre_reloc_only &&
  63. !ofnode_pre_reloc(offset_to_ofnode(offset)))
  64. continue;
  65. /*
  66. * If this node has "compatible" property, this is not
  67. * a clock sub-node, but a normal device. skip.
  68. */
  69. fdt_get_property(fdt, offset, "compatible", &ret);
  70. if (ret >= 0)
  71. continue;
  72. if (ret != -FDT_ERR_NOTFOUND)
  73. return ret;
  74. name = fdt_get_name(fdt, offset, NULL);
  75. if (!name)
  76. return -EINVAL;
  77. ret = device_bind_driver_to_node(dev, drv_name, name,
  78. offset_to_ofnode(offset), NULL);
  79. if (ret)
  80. return ret;
  81. }
  82. return 0;
  83. }
  84. int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  85. {
  86. int periph;
  87. if (args->args_count) {
  88. debug("Invalid args_count: %d\n", args->args_count);
  89. return -EINVAL;
  90. }
  91. periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
  92. -1);
  93. if (periph < 0)
  94. return -EINVAL;
  95. clk->id = periph;
  96. return 0;
  97. }
  98. int at91_clk_probe(struct udevice *dev)
  99. {
  100. struct udevice *dev_periph_container, *dev_pmc;
  101. struct pmc_platdata *plat = dev_get_platdata(dev);
  102. dev_periph_container = dev_get_parent(dev);
  103. dev_pmc = dev_get_parent(dev_periph_container);
  104. plat->reg_base = dev_read_addr_ptr(dev_pmc);
  105. return 0;
  106. }
  107. /* SCKC specific code. */
  108. static const struct udevice_id at91_sckc_match[] = {
  109. { .compatible = "atmel,at91sam9x5-sckc" },
  110. {}
  111. };
  112. U_BOOT_DRIVER(at91_sckc) = {
  113. .name = "at91-sckc",
  114. .id = UCLASS_SIMPLE_BUS,
  115. .of_match = at91_sckc_match,
  116. };
  117. /* Slow clock specific code. */
  118. static int at91_slow_clk_enable(struct clk *clk)
  119. {
  120. return 0;
  121. }
  122. static ulong at91_slow_clk_get_rate(struct clk *clk)
  123. {
  124. return CONFIG_SYS_AT91_SLOW_CLOCK;
  125. }
  126. static struct clk_ops at91_slow_clk_ops = {
  127. .enable = at91_slow_clk_enable,
  128. .get_rate = at91_slow_clk_get_rate,
  129. };
  130. static const struct udevice_id at91_slow_clk_match[] = {
  131. { .compatible = "atmel,at91sam9x5-clk-slow" },
  132. {}
  133. };
  134. U_BOOT_DRIVER(at91_slow_clk) = {
  135. .name = "at91-slow-clk",
  136. .id = UCLASS_CLK,
  137. .of_match = at91_slow_clk_match,
  138. .ops = &at91_slow_clk_ops,
  139. };
  140. /* Master clock specific code. */
  141. static ulong at91_master_clk_get_rate(struct clk *clk)
  142. {
  143. return gd->arch.mck_rate_hz;
  144. }
  145. static struct clk_ops at91_master_clk_ops = {
  146. .get_rate = at91_master_clk_get_rate,
  147. };
  148. static const struct udevice_id at91_master_clk_match[] = {
  149. { .compatible = "atmel,at91rm9200-clk-master" },
  150. { .compatible = "atmel,at91sam9x5-clk-master" },
  151. {}
  152. };
  153. U_BOOT_DRIVER(at91_master_clk) = {
  154. .name = "at91-master-clk",
  155. .id = UCLASS_CLK,
  156. .of_match = at91_master_clk_match,
  157. .ops = &at91_master_clk_ops,
  158. };
  159. /* Main osc clock specific code. */
  160. static int main_osc_clk_enable(struct clk *clk)
  161. {
  162. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  163. struct at91_pmc *pmc = plat->reg_base;
  164. if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
  165. return 0;
  166. return -EINVAL;
  167. }
  168. static ulong main_osc_clk_get_rate(struct clk *clk)
  169. {
  170. return gd->arch.main_clk_rate_hz;
  171. }
  172. static struct clk_ops main_osc_clk_ops = {
  173. .enable = main_osc_clk_enable,
  174. .get_rate = main_osc_clk_get_rate,
  175. };
  176. static int main_osc_clk_probe(struct udevice *dev)
  177. {
  178. return at91_pmc_core_probe(dev);
  179. }
  180. static const struct udevice_id main_osc_clk_match[] = {
  181. { .compatible = "atmel,at91sam9x5-clk-main" },
  182. {}
  183. };
  184. U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = {
  185. .name = "at91sam9x5-main-osc-clk",
  186. .id = UCLASS_CLK,
  187. .of_match = main_osc_clk_match,
  188. .probe = main_osc_clk_probe,
  189. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  190. .ops = &main_osc_clk_ops,
  191. };
  192. /* PLLA clock specific code. */
  193. static int plla_clk_enable(struct clk *clk)
  194. {
  195. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  196. struct at91_pmc *pmc = plat->reg_base;
  197. if (readl(&pmc->sr) & AT91_PMC_LOCKA)
  198. return 0;
  199. return -EINVAL;
  200. }
  201. static ulong plla_clk_get_rate(struct clk *clk)
  202. {
  203. return gd->arch.plla_rate_hz;
  204. }
  205. static struct clk_ops plla_clk_ops = {
  206. .enable = plla_clk_enable,
  207. .get_rate = plla_clk_get_rate,
  208. };
  209. static int plla_clk_probe(struct udevice *dev)
  210. {
  211. return at91_pmc_core_probe(dev);
  212. }
  213. static const struct udevice_id plla_clk_match[] = {
  214. { .compatible = "atmel,sama5d3-clk-pll" },
  215. {}
  216. };
  217. U_BOOT_DRIVER(at91_plla_clk) = {
  218. .name = "at91-plla-clk",
  219. .id = UCLASS_CLK,
  220. .of_match = plla_clk_match,
  221. .probe = plla_clk_probe,
  222. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  223. .ops = &plla_clk_ops,
  224. };
  225. /* PLLA DIV clock specific code. */
  226. static int at91_plladiv_clk_enable(struct clk *clk)
  227. {
  228. return 0;
  229. }
  230. static ulong at91_plladiv_clk_get_rate(struct clk *clk)
  231. {
  232. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  233. struct at91_pmc *pmc = plat->reg_base;
  234. struct clk source;
  235. ulong clk_rate;
  236. int ret;
  237. ret = clk_get_by_index(clk->dev, 0, &source);
  238. if (ret)
  239. return -EINVAL;
  240. clk_rate = clk_get_rate(&source);
  241. if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
  242. clk_rate /= 2;
  243. return clk_rate;
  244. }
  245. static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)
  246. {
  247. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  248. struct at91_pmc *pmc = plat->reg_base;
  249. struct clk source;
  250. ulong parent_rate;
  251. int ret;
  252. ret = clk_get_by_index(clk->dev, 0, &source);
  253. if (ret)
  254. return -EINVAL;
  255. parent_rate = clk_get_rate(&source);
  256. if ((parent_rate != rate) && ((parent_rate) / 2 != rate))
  257. return -EINVAL;
  258. if (parent_rate != rate) {
  259. writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
  260. &pmc->mckr);
  261. }
  262. return 0;
  263. }
  264. static struct clk_ops at91_plladiv_clk_ops = {
  265. .enable = at91_plladiv_clk_enable,
  266. .get_rate = at91_plladiv_clk_get_rate,
  267. .set_rate = at91_plladiv_clk_set_rate,
  268. };
  269. static int at91_plladiv_clk_probe(struct udevice *dev)
  270. {
  271. return at91_pmc_core_probe(dev);
  272. }
  273. static const struct udevice_id at91_plladiv_clk_match[] = {
  274. { .compatible = "atmel,at91sam9x5-clk-plldiv" },
  275. {}
  276. };
  277. U_BOOT_DRIVER(at91_plladiv_clk) = {
  278. .name = "at91-plladiv-clk",
  279. .id = UCLASS_CLK,
  280. .of_match = at91_plladiv_clk_match,
  281. .probe = at91_plladiv_clk_probe,
  282. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  283. .ops = &at91_plladiv_clk_ops,
  284. };
  285. /* System clock specific code. */
  286. #define SYSTEM_MAX_ID 31
  287. /**
  288. * at91_system_clk_bind() - for the system clock driver
  289. * Recursively bind its children as clk devices.
  290. *
  291. * @return: 0 on success, or negative error code on failure
  292. */
  293. static int at91_system_clk_bind(struct udevice *dev)
  294. {
  295. return at91_clk_sub_device_bind(dev, "system-clk");
  296. }
  297. static const struct udevice_id at91_system_clk_match[] = {
  298. { .compatible = "atmel,at91rm9200-clk-system" },
  299. {}
  300. };
  301. U_BOOT_DRIVER(at91_system_clk) = {
  302. .name = "at91-system-clk",
  303. .id = UCLASS_MISC,
  304. .of_match = at91_system_clk_match,
  305. .bind = at91_system_clk_bind,
  306. };
  307. static inline int is_pck(int id)
  308. {
  309. return (id >= 8) && (id <= 15);
  310. }
  311. static ulong system_clk_get_rate(struct clk *clk)
  312. {
  313. struct clk clk_dev;
  314. int ret;
  315. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  316. if (ret)
  317. return -EINVAL;
  318. return clk_get_rate(&clk_dev);
  319. }
  320. static ulong system_clk_set_rate(struct clk *clk, ulong rate)
  321. {
  322. struct clk clk_dev;
  323. int ret;
  324. ret = clk_get_by_index(clk->dev, 0, &clk_dev);
  325. if (ret)
  326. return -EINVAL;
  327. return clk_set_rate(&clk_dev, rate);
  328. }
  329. static int system_clk_enable(struct clk *clk)
  330. {
  331. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  332. struct at91_pmc *pmc = plat->reg_base;
  333. u32 mask;
  334. if (clk->id > SYSTEM_MAX_ID)
  335. return -EINVAL;
  336. mask = BIT(clk->id);
  337. writel(mask, &pmc->scer);
  338. /**
  339. * For the programmable clocks the Ready status in the PMC
  340. * status register should be checked after enabling.
  341. * For other clocks this is unnecessary.
  342. */
  343. if (!is_pck(clk->id))
  344. return 0;
  345. while (!(readl(&pmc->sr) & mask))
  346. ;
  347. return 0;
  348. }
  349. static struct clk_ops system_clk_ops = {
  350. .of_xlate = at91_clk_of_xlate,
  351. .get_rate = system_clk_get_rate,
  352. .set_rate = system_clk_set_rate,
  353. .enable = system_clk_enable,
  354. };
  355. U_BOOT_DRIVER(system_clk) = {
  356. .name = "system-clk",
  357. .id = UCLASS_CLK,
  358. .probe = at91_clk_probe,
  359. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  360. .ops = &system_clk_ops,
  361. };
  362. /* Peripheral clock specific code. */
  363. #define PERIPHERAL_ID_MIN 2
  364. #define PERIPHERAL_ID_MAX 31
  365. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  366. enum periph_clk_type {
  367. CLK_PERIPH_AT91RM9200 = 0,
  368. CLK_PERIPH_AT91SAM9X5,
  369. };
  370. /**
  371. * sam9x5_periph_clk_bind() - for the periph clock driver
  372. * Recursively bind its children as clk devices.
  373. *
  374. * @return: 0 on success, or negative error code on failure
  375. */
  376. static int sam9x5_periph_clk_bind(struct udevice *dev)
  377. {
  378. return at91_clk_sub_device_bind(dev, "periph-clk");
  379. }
  380. static const struct udevice_id sam9x5_periph_clk_match[] = {
  381. {
  382. .compatible = "atmel,at91rm9200-clk-peripheral",
  383. .data = CLK_PERIPH_AT91RM9200,
  384. },
  385. {
  386. .compatible = "atmel,at91sam9x5-clk-peripheral",
  387. .data = CLK_PERIPH_AT91SAM9X5,
  388. },
  389. {}
  390. };
  391. U_BOOT_DRIVER(sam9x5_periph_clk) = {
  392. .name = "sam9x5-periph-clk",
  393. .id = UCLASS_MISC,
  394. .of_match = sam9x5_periph_clk_match,
  395. .bind = sam9x5_periph_clk_bind,
  396. };
  397. static int periph_clk_enable(struct clk *clk)
  398. {
  399. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  400. struct at91_pmc *pmc = plat->reg_base;
  401. enum periph_clk_type clk_type;
  402. void *addr;
  403. if (clk->id < PERIPHERAL_ID_MIN)
  404. return -1;
  405. clk_type = dev_get_driver_data(dev_get_parent(clk->dev));
  406. if (clk_type == CLK_PERIPH_AT91RM9200) {
  407. addr = &pmc->pcer;
  408. if (clk->id > PERIPHERAL_ID_MAX)
  409. addr = &pmc->pcer1;
  410. setbits_le32(addr, PERIPHERAL_MASK(clk->id));
  411. } else {
  412. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  413. setbits_le32(&pmc->pcr,
  414. AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
  415. }
  416. return 0;
  417. }
  418. static ulong periph_get_rate(struct clk *clk)
  419. {
  420. struct udevice *dev;
  421. struct clk clk_dev;
  422. ulong clk_rate;
  423. int ret;
  424. dev = dev_get_parent(clk->dev);
  425. ret = clk_get_by_index(dev, 0, &clk_dev);
  426. if (ret)
  427. return ret;
  428. clk_rate = clk_get_rate(&clk_dev);
  429. clk_free(&clk_dev);
  430. return clk_rate;
  431. }
  432. static struct clk_ops periph_clk_ops = {
  433. .of_xlate = at91_clk_of_xlate,
  434. .enable = periph_clk_enable,
  435. .get_rate = periph_get_rate,
  436. };
  437. U_BOOT_DRIVER(clk_periph) = {
  438. .name = "periph-clk",
  439. .id = UCLASS_CLK,
  440. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  441. .probe = at91_clk_probe,
  442. .ops = &periph_clk_ops,
  443. };
  444. /* UTMI clock specific code. */
  445. #ifdef CONFIG_AT91_UTMI
  446. /*
  447. * The purpose of this clock is to generate a 480 MHz signal. A different
  448. * rate can't be configured.
  449. */
  450. #define UTMI_RATE 480000000
  451. static int utmi_clk_enable(struct clk *clk)
  452. {
  453. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  454. struct at91_pmc *pmc = plat->reg_base;
  455. struct clk clk_dev;
  456. ulong clk_rate;
  457. u32 utmi_ref_clk_freq;
  458. u32 tmp;
  459. int err;
  460. int timeout = 2000000;
  461. if (readl(&pmc->sr) & AT91_PMC_LOCKU)
  462. return 0;
  463. /*
  464. * If mainck rate is different from 12 MHz, we have to configure the
  465. * FREQ field of the SFR_UTMICKTRIM register to generate properly
  466. * the utmi clock.
  467. */
  468. err = clk_get_by_index(clk->dev, 0, &clk_dev);
  469. if (err)
  470. return -EINVAL;
  471. clk_rate = clk_get_rate(&clk_dev);
  472. switch (clk_rate) {
  473. case 12000000:
  474. utmi_ref_clk_freq = 0;
  475. break;
  476. case 16000000:
  477. utmi_ref_clk_freq = 1;
  478. break;
  479. case 24000000:
  480. utmi_ref_clk_freq = 2;
  481. break;
  482. /*
  483. * Not supported on SAMA5D2 but it's not an issue since MAINCK
  484. * maximum value is 24 MHz.
  485. */
  486. case 48000000:
  487. utmi_ref_clk_freq = 3;
  488. break;
  489. default:
  490. printf("UTMICK: unsupported mainck rate\n");
  491. return -EINVAL;
  492. }
  493. if (plat->regmap_sfr) {
  494. err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
  495. if (err)
  496. return -EINVAL;
  497. tmp &= ~AT91_UTMICKTRIM_FREQ;
  498. tmp |= utmi_ref_clk_freq;
  499. err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
  500. if (err)
  501. return -EINVAL;
  502. } else if (utmi_ref_clk_freq) {
  503. printf("UTMICK: sfr node required\n");
  504. return -EINVAL;
  505. }
  506. tmp = readl(&pmc->uckr);
  507. tmp |= AT91_PMC_UPLLEN |
  508. AT91_PMC_UPLLCOUNT |
  509. AT91_PMC_BIASEN;
  510. writel(tmp, &pmc->uckr);
  511. while ((--timeout) && !(readl(&pmc->sr) & AT91_PMC_LOCKU))
  512. ;
  513. if (!timeout) {
  514. printf("UTMICK: timeout waiting for UPLL lock\n");
  515. return -ETIMEDOUT;
  516. }
  517. return 0;
  518. }
  519. static ulong utmi_clk_get_rate(struct clk *clk)
  520. {
  521. /* UTMI clk rate is fixed. */
  522. return UTMI_RATE;
  523. }
  524. static struct clk_ops utmi_clk_ops = {
  525. .enable = utmi_clk_enable,
  526. .get_rate = utmi_clk_get_rate,
  527. };
  528. static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
  529. {
  530. struct pmc_platdata *plat = dev_get_platdata(dev);
  531. struct udevice *syscon;
  532. uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  533. "regmap-sfr", &syscon);
  534. if (syscon)
  535. plat->regmap_sfr = syscon_get_regmap(syscon);
  536. return 0;
  537. }
  538. static int utmi_clk_probe(struct udevice *dev)
  539. {
  540. return at91_pmc_core_probe(dev);
  541. }
  542. static const struct udevice_id utmi_clk_match[] = {
  543. { .compatible = "atmel,at91sam9x5-clk-utmi" },
  544. {}
  545. };
  546. U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
  547. .name = "at91sam9x5-utmi-clk",
  548. .id = UCLASS_CLK,
  549. .of_match = utmi_clk_match,
  550. .probe = utmi_clk_probe,
  551. .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
  552. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  553. .ops = &utmi_clk_ops,
  554. };
  555. #endif /* CONFIG_AT91_UTMI */
  556. /* H32MX clock specific code. */
  557. #ifdef CONFIG_AT91_H32MX
  558. #define H32MX_MAX_FREQ 90000000
  559. static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
  560. {
  561. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  562. struct at91_pmc *pmc = plat->reg_base;
  563. ulong rate = gd->arch.mck_rate_hz;
  564. if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
  565. rate /= 2;
  566. if (rate > H32MX_MAX_FREQ)
  567. dev_dbg(clk->dev, "H32MX clock is too fast\n");
  568. return rate;
  569. }
  570. static struct clk_ops sama5d4_h32mx_clk_ops = {
  571. .get_rate = sama5d4_h32mx_clk_get_rate,
  572. };
  573. static int sama5d4_h32mx_clk_probe(struct udevice *dev)
  574. {
  575. return at91_pmc_core_probe(dev);
  576. }
  577. static const struct udevice_id sama5d4_h32mx_clk_match[] = {
  578. { .compatible = "atmel,sama5d4-clk-h32mx" },
  579. {}
  580. };
  581. U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
  582. .name = "sama5d4-h32mx-clk",
  583. .id = UCLASS_CLK,
  584. .of_match = sama5d4_h32mx_clk_match,
  585. .probe = sama5d4_h32mx_clk_probe,
  586. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  587. .ops = &sama5d4_h32mx_clk_ops,
  588. };
  589. #endif /* CONFIG_AT91_H32MX */
  590. /* Generic clock specific code. */
  591. #ifdef CONFIG_AT91_GENERIC_CLK
  592. #define GENERATED_SOURCE_MAX 6
  593. #define GENERATED_MAX_DIV 255
  594. /**
  595. * generated_clk_bind() - for the generated clock driver
  596. * Recursively bind its children as clk devices.
  597. *
  598. * @return: 0 on success, or negative error code on failure
  599. */
  600. static int generated_clk_bind(struct udevice *dev)
  601. {
  602. return at91_clk_sub_device_bind(dev, "generic-clk");
  603. }
  604. static const struct udevice_id generated_clk_match[] = {
  605. { .compatible = "atmel,sama5d2-clk-generated" },
  606. {}
  607. };
  608. U_BOOT_DRIVER(generated_clk) = {
  609. .name = "generated-clk",
  610. .id = UCLASS_MISC,
  611. .of_match = generated_clk_match,
  612. .bind = generated_clk_bind,
  613. };
  614. struct generic_clk_priv {
  615. u32 num_parents;
  616. };
  617. static ulong generic_clk_get_rate(struct clk *clk)
  618. {
  619. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  620. struct at91_pmc *pmc = plat->reg_base;
  621. struct clk parent;
  622. ulong clk_rate;
  623. u32 tmp, gckdiv;
  624. u8 clock_source, parent_index;
  625. int ret;
  626. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  627. tmp = readl(&pmc->pcr);
  628. clock_source = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
  629. AT91_PMC_PCR_GCKCSS_MASK;
  630. gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
  631. parent_index = clock_source - 1;
  632. ret = clk_get_by_index(dev_get_parent(clk->dev), parent_index, &parent);
  633. if (ret)
  634. return 0;
  635. clk_rate = clk_get_rate(&parent) / (gckdiv + 1);
  636. clk_free(&parent);
  637. return clk_rate;
  638. }
  639. static ulong generic_clk_set_rate(struct clk *clk, ulong rate)
  640. {
  641. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  642. struct at91_pmc *pmc = plat->reg_base;
  643. struct generic_clk_priv *priv = dev_get_priv(clk->dev);
  644. struct clk parent, best_parent;
  645. ulong tmp_rate, best_rate = rate, parent_rate;
  646. int tmp_diff, best_diff = -1;
  647. u32 div, best_div = 0;
  648. u8 best_parent_index, best_clock_source = 0;
  649. u8 i;
  650. u32 tmp;
  651. int ret;
  652. for (i = 0; i < priv->num_parents; i++) {
  653. ret = clk_get_by_index(dev_get_parent(clk->dev), i, &parent);
  654. if (ret)
  655. return ret;
  656. parent_rate = clk_get_rate(&parent);
  657. if (IS_ERR_VALUE(parent_rate))
  658. return parent_rate;
  659. for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
  660. tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
  661. tmp_diff = abs(rate - tmp_rate);
  662. if (best_diff < 0 || best_diff > tmp_diff) {
  663. best_rate = tmp_rate;
  664. best_diff = tmp_diff;
  665. best_div = div - 1;
  666. best_parent = parent;
  667. best_parent_index = i;
  668. best_clock_source = best_parent_index + 1;
  669. }
  670. if (!best_diff || tmp_rate < rate)
  671. break;
  672. }
  673. if (!best_diff)
  674. break;
  675. }
  676. debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
  677. best_parent.dev->name, best_rate, best_div);
  678. ret = clk_enable(&best_parent);
  679. if (ret)
  680. return ret;
  681. writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
  682. tmp = readl(&pmc->pcr);
  683. tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
  684. tmp |= AT91_PMC_PCR_GCKCSS_(best_clock_source) |
  685. AT91_PMC_PCR_CMD_WRITE |
  686. AT91_PMC_PCR_GCKDIV_(best_div) |
  687. AT91_PMC_PCR_GCKEN;
  688. writel(tmp, &pmc->pcr);
  689. while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
  690. ;
  691. return 0;
  692. }
  693. static struct clk_ops generic_clk_ops = {
  694. .of_xlate = at91_clk_of_xlate,
  695. .get_rate = generic_clk_get_rate,
  696. .set_rate = generic_clk_set_rate,
  697. };
  698. static int generic_clk_ofdata_to_platdata(struct udevice *dev)
  699. {
  700. struct generic_clk_priv *priv = dev_get_priv(dev);
  701. u32 cells[GENERATED_SOURCE_MAX];
  702. u32 num_parents;
  703. num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
  704. dev_of_offset(dev_get_parent(dev)), "clocks", cells,
  705. GENERATED_SOURCE_MAX);
  706. if (!num_parents)
  707. return -1;
  708. priv->num_parents = num_parents;
  709. return 0;
  710. }
  711. U_BOOT_DRIVER(generic_clk) = {
  712. .name = "generic-clk",
  713. .id = UCLASS_CLK,
  714. .probe = at91_clk_probe,
  715. .ofdata_to_platdata = generic_clk_ofdata_to_platdata,
  716. .priv_auto_alloc_size = sizeof(struct generic_clk_priv),
  717. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  718. .ops = &generic_clk_ops,
  719. };
  720. #endif /* CONFIG_AT91_GENERIC_CLK */
  721. /* USB clock specific code. */
  722. #ifdef CONFIG_AT91_USB_CLK
  723. #define AT91_USB_CLK_SOURCE_MAX 2
  724. #define AT91_USB_CLK_MAX_DIV 15
  725. struct at91_usb_clk_priv {
  726. u32 num_clksource;
  727. };
  728. static ulong at91_usb_clk_get_rate(struct clk *clk)
  729. {
  730. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  731. struct at91_pmc *pmc = plat->reg_base;
  732. struct clk source;
  733. u32 tmp, usbdiv;
  734. u8 source_index;
  735. int ret;
  736. tmp = readl(&pmc->pcr);
  737. source_index = (tmp >> AT91_PMC_USB_USBS_OFFSET) &
  738. AT91_PMC_USB_USBS_MASK;
  739. usbdiv = (tmp >> AT91_PMC_USB_DIV_OFFSET) & AT91_PMC_USB_DIV_MASK;
  740. ret = clk_get_by_index(clk->dev, source_index, &source);
  741. if (ret)
  742. return 0;
  743. return clk_get_rate(&source) / (usbdiv + 1);
  744. }
  745. static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)
  746. {
  747. struct pmc_platdata *plat = dev_get_platdata(clk->dev);
  748. struct at91_pmc *pmc = plat->reg_base;
  749. struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);
  750. struct clk source, best_source;
  751. ulong tmp_rate, best_rate = rate, source_rate;
  752. int tmp_diff, best_diff = -1;
  753. u32 div, best_div = 0;
  754. u8 best_source_index = 0;
  755. u8 i;
  756. u32 tmp;
  757. int ret;
  758. for (i = 0; i < priv->num_clksource; i++) {
  759. ret = clk_get_by_index(clk->dev, i, &source);
  760. if (ret)
  761. return ret;
  762. source_rate = clk_get_rate(&source);
  763. if (IS_ERR_VALUE(source_rate))
  764. return source_rate;
  765. for (div = 1; div < AT91_USB_CLK_MAX_DIV + 2; div++) {
  766. tmp_rate = DIV_ROUND_CLOSEST(source_rate, div);
  767. tmp_diff = abs(rate - tmp_rate);
  768. if (best_diff < 0 || best_diff > tmp_diff) {
  769. best_rate = tmp_rate;
  770. best_diff = tmp_diff;
  771. best_div = div - 1;
  772. best_source = source;
  773. best_source_index = i;
  774. }
  775. if (!best_diff || tmp_rate < rate)
  776. break;
  777. }
  778. if (!best_diff)
  779. break;
  780. }
  781. debug("AT91 USB: best sourc: %s, best_rate = %ld, best_div = %d\n",
  782. best_source.dev->name, best_rate, best_div);
  783. ret = clk_enable(&best_source);
  784. if (ret)
  785. return ret;
  786. tmp = AT91_PMC_USB_USBS_(best_source_index) |
  787. AT91_PMC_USB_DIV_(best_div);
  788. writel(tmp, &pmc->usb);
  789. return 0;
  790. }
  791. static struct clk_ops at91_usb_clk_ops = {
  792. .get_rate = at91_usb_clk_get_rate,
  793. .set_rate = at91_usb_clk_set_rate,
  794. };
  795. static int at91_usb_clk_ofdata_to_platdata(struct udevice *dev)
  796. {
  797. struct at91_usb_clk_priv *priv = dev_get_priv(dev);
  798. u32 cells[AT91_USB_CLK_SOURCE_MAX];
  799. u32 num_clksource;
  800. num_clksource = fdtdec_get_int_array_count(gd->fdt_blob,
  801. dev_of_offset(dev),
  802. "clocks", cells,
  803. AT91_USB_CLK_SOURCE_MAX);
  804. if (!num_clksource)
  805. return -1;
  806. priv->num_clksource = num_clksource;
  807. return 0;
  808. }
  809. static int at91_usb_clk_probe(struct udevice *dev)
  810. {
  811. return at91_pmc_core_probe(dev);
  812. }
  813. static const struct udevice_id at91_usb_clk_match[] = {
  814. { .compatible = "atmel,at91sam9x5-clk-usb" },
  815. {}
  816. };
  817. U_BOOT_DRIVER(at91_usb_clk) = {
  818. .name = "at91-usb-clk",
  819. .id = UCLASS_CLK,
  820. .of_match = at91_usb_clk_match,
  821. .probe = at91_usb_clk_probe,
  822. .ofdata_to_platdata = at91_usb_clk_ofdata_to_platdata,
  823. .priv_auto_alloc_size = sizeof(struct at91_usb_clk_priv),
  824. .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
  825. .ops = &at91_usb_clk_ops,
  826. };
  827. #endif /* CONFIG_AT91_USB_CLK */