clk-utmi.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * UTMI clock support for AT91 architectures.
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. *
  9. * Based on drivers/clk/at91/clk-utmi.c from Linux.
  10. */
  11. #include <asm/processor.h>
  12. #include <common.h>
  13. #include <clk-uclass.h>
  14. #include <dm.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/clk/at91_pmc.h>
  17. #include <mach/at91_sfr.h>
  18. #include <regmap.h>
  19. #include <syscon.h>
  20. #include "pmc.h"
  21. #define UBOOT_DM_CLK_AT91_UTMI "at91-utmi-clk"
  22. #define UBOOT_DM_CLK_AT91_SAMA7G5_UTMI "at91-sama7g5-utmi-clk"
  23. /*
  24. * The purpose of this clock is to generate a 480 MHz signal. A different
  25. * rate can't be configured.
  26. */
  27. #define UTMI_RATE 480000000
  28. struct clk_utmi {
  29. void __iomem *base;
  30. struct regmap *regmap_sfr;
  31. struct clk clk;
  32. };
  33. #define to_clk_utmi(_clk) container_of(_clk, struct clk_utmi, clk)
  34. static inline bool clk_utmi_ready(struct regmap *regmap)
  35. {
  36. unsigned int status;
  37. pmc_read(regmap, AT91_PMC_SR, &status);
  38. return !!(status & AT91_PMC_LOCKU);
  39. }
  40. static int clk_utmi_enable(struct clk *clk)
  41. {
  42. struct clk_utmi *utmi = to_clk_utmi(clk);
  43. unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
  44. AT91_PMC_BIASEN;
  45. unsigned int utmi_ref_clk_freq;
  46. ulong parent_rate = clk_get_parent_rate(clk);
  47. /*
  48. * If mainck rate is different from 12 MHz, we have to configure the
  49. * FREQ field of the SFR_UTMICKTRIM register to generate properly
  50. * the utmi clock.
  51. */
  52. switch (parent_rate) {
  53. case 12000000:
  54. utmi_ref_clk_freq = 0;
  55. break;
  56. case 16000000:
  57. utmi_ref_clk_freq = 1;
  58. break;
  59. case 24000000:
  60. utmi_ref_clk_freq = 2;
  61. break;
  62. /*
  63. * Not supported on SAMA5D2 but it's not an issue since MAINCK
  64. * maximum value is 24 MHz.
  65. */
  66. case 48000000:
  67. utmi_ref_clk_freq = 3;
  68. break;
  69. default:
  70. debug("UTMICK: unsupported mainck rate\n");
  71. return -EINVAL;
  72. }
  73. if (utmi->regmap_sfr) {
  74. regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
  75. AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
  76. } else if (utmi_ref_clk_freq) {
  77. debug("UTMICK: sfr node required\n");
  78. return -EINVAL;
  79. }
  80. pmc_update_bits(utmi->base, AT91_CKGR_UCKR, uckr, uckr);
  81. while (!clk_utmi_ready(utmi->base)) {
  82. debug("waiting for utmi...\n");
  83. cpu_relax();
  84. }
  85. return 0;
  86. }
  87. static int clk_utmi_disable(struct clk *clk)
  88. {
  89. struct clk_utmi *utmi = to_clk_utmi(clk);
  90. pmc_update_bits(utmi->base, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0);
  91. return 0;
  92. }
  93. static ulong clk_utmi_get_rate(struct clk *clk)
  94. {
  95. /* UTMI clk rate is fixed. */
  96. return UTMI_RATE;
  97. }
  98. static const struct clk_ops utmi_ops = {
  99. .enable = clk_utmi_enable,
  100. .disable = clk_utmi_disable,
  101. .get_rate = clk_utmi_get_rate,
  102. };
  103. struct clk *at91_clk_register_utmi(void __iomem *base, struct udevice *dev,
  104. const char *name, const char *parent_name)
  105. {
  106. struct udevice *syscon;
  107. struct clk_utmi *utmi;
  108. struct clk *clk;
  109. int ret;
  110. if (!base || !dev || !name || !parent_name)
  111. return ERR_PTR(-EINVAL);
  112. ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  113. "regmap-sfr", &syscon);
  114. if (ret)
  115. return ERR_PTR(ret);
  116. utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
  117. if (!utmi)
  118. return ERR_PTR(-ENOMEM);
  119. utmi->base = base;
  120. utmi->regmap_sfr = syscon_get_regmap(syscon);
  121. if (!utmi->regmap_sfr) {
  122. kfree(utmi);
  123. return ERR_PTR(-ENODEV);
  124. }
  125. clk = &utmi->clk;
  126. clk->flags = CLK_GET_RATE_NOCACHE;
  127. ret = clk_register(clk, UBOOT_DM_CLK_AT91_UTMI, name, parent_name);
  128. if (ret) {
  129. kfree(utmi);
  130. clk = ERR_PTR(ret);
  131. }
  132. return clk;
  133. }
  134. U_BOOT_DRIVER(at91_utmi_clk) = {
  135. .name = UBOOT_DM_CLK_AT91_UTMI,
  136. .id = UCLASS_CLK,
  137. .ops = &utmi_ops,
  138. .flags = DM_FLAG_PRE_RELOC,
  139. };
  140. static int clk_utmi_sama7g5_enable(struct clk *clk)
  141. {
  142. struct clk_utmi *utmi = to_clk_utmi(clk);
  143. ulong parent_rate = clk_get_parent_rate(clk);
  144. unsigned int val;
  145. switch (parent_rate) {
  146. case 16000000:
  147. val = 0;
  148. break;
  149. case 20000000:
  150. val = 2;
  151. break;
  152. case 24000000:
  153. val = 3;
  154. break;
  155. case 32000000:
  156. val = 5;
  157. break;
  158. default:
  159. debug("UTMICK: unsupported main_xtal rate\n");
  160. return -EINVAL;
  161. }
  162. pmc_write(utmi->base, AT91_PMC_XTALF, val);
  163. return 0;
  164. }
  165. static const struct clk_ops sama7g5_utmi_ops = {
  166. .enable = clk_utmi_sama7g5_enable,
  167. .get_rate = clk_utmi_get_rate,
  168. };
  169. struct clk *at91_clk_sama7g5_register_utmi(void __iomem *base,
  170. const char *name, const char *parent_name)
  171. {
  172. struct clk_utmi *utmi;
  173. struct clk *clk;
  174. int ret;
  175. if (!base || !name || !parent_name)
  176. return ERR_PTR(-EINVAL);
  177. utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
  178. if (!utmi)
  179. return ERR_PTR(-ENOMEM);
  180. utmi->base = base;
  181. clk = &utmi->clk;
  182. ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAMA7G5_UTMI, name,
  183. parent_name);
  184. if (ret) {
  185. kfree(utmi);
  186. clk = ERR_PTR(ret);
  187. }
  188. return clk;
  189. }
  190. U_BOOT_DRIVER(at91_sama7g5_utmi_clk) = {
  191. .name = UBOOT_DM_CLK_AT91_SAMA7G5_UTMI,
  192. .id = UCLASS_CLK,
  193. .ops = &sama7g5_utmi_ops,
  194. .flags = DM_FLAG_PRE_RELOC,
  195. };