clk-peripheral.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Peripheral clock support for AT91 architectures.
  4. *
  5. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  6. *
  7. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  8. *
  9. * Based on drivers/clk/at91/clk-peripheral.c from Linux.
  10. */
  11. #include <common.h>
  12. #include <clk-uclass.h>
  13. #include <dm.h>
  14. #include <linux/io.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/clk/at91_pmc.h>
  17. #include "pmc.h"
  18. #define UBOOT_DM_CLK_AT91_PERIPH "at91-periph-clk"
  19. #define UBOOT_DM_CLK_AT91_SAM9X5_PERIPH "at91-sam9x5-periph-clk"
  20. #define PERIPHERAL_ID_MIN 2
  21. #define PERIPHERAL_ID_MAX 31
  22. #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
  23. #define PERIPHERAL_MAX_SHIFT 3
  24. struct clk_peripheral {
  25. void __iomem *base;
  26. struct clk clk;
  27. u32 id;
  28. };
  29. #define to_clk_peripheral(_c) container_of(_c, struct clk_peripheral, clk)
  30. struct clk_sam9x5_peripheral {
  31. const struct clk_pcr_layout *layout;
  32. void __iomem *base;
  33. struct clk clk;
  34. struct clk_range range;
  35. u32 id;
  36. u32 div;
  37. bool auto_div;
  38. };
  39. #define to_clk_sam9x5_peripheral(_c) \
  40. container_of(_c, struct clk_sam9x5_peripheral, clk)
  41. static int clk_peripheral_enable(struct clk *clk)
  42. {
  43. struct clk_peripheral *periph = to_clk_peripheral(clk);
  44. int offset = AT91_PMC_PCER;
  45. u32 id = periph->id;
  46. if (id < PERIPHERAL_ID_MIN)
  47. return 0;
  48. if (id > PERIPHERAL_ID_MAX)
  49. offset = AT91_PMC_PCER1;
  50. pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
  51. return 0;
  52. }
  53. static int clk_peripheral_disable(struct clk *clk)
  54. {
  55. struct clk_peripheral *periph = to_clk_peripheral(clk);
  56. int offset = AT91_PMC_PCDR;
  57. u32 id = periph->id;
  58. if (id < PERIPHERAL_ID_MIN)
  59. return -EINVAL;
  60. if (id > PERIPHERAL_ID_MAX)
  61. offset = AT91_PMC_PCDR1;
  62. pmc_write(periph->base, offset, PERIPHERAL_MASK(id));
  63. return 0;
  64. }
  65. static const struct clk_ops peripheral_ops = {
  66. .enable = clk_peripheral_enable,
  67. .disable = clk_peripheral_disable,
  68. .get_rate = clk_generic_get_rate,
  69. };
  70. struct clk *
  71. at91_clk_register_peripheral(void __iomem *base, const char *name,
  72. const char *parent_name, u32 id)
  73. {
  74. struct clk_peripheral *periph;
  75. struct clk *clk;
  76. int ret;
  77. if (!base || !name || !parent_name || id > PERIPHERAL_ID_MAX)
  78. return ERR_PTR(-EINVAL);
  79. periph = kzalloc(sizeof(*periph), GFP_KERNEL);
  80. if (!periph)
  81. return ERR_PTR(-ENOMEM);
  82. periph->id = id;
  83. periph->base = base;
  84. clk = &periph->clk;
  85. clk->flags = CLK_GET_RATE_NOCACHE;
  86. ret = clk_register(clk, UBOOT_DM_CLK_AT91_PERIPH, name, parent_name);
  87. if (ret) {
  88. kfree(periph);
  89. clk = ERR_PTR(ret);
  90. }
  91. return clk;
  92. }
  93. U_BOOT_DRIVER(at91_periph_clk) = {
  94. .name = UBOOT_DM_CLK_AT91_PERIPH,
  95. .id = UCLASS_CLK,
  96. .ops = &peripheral_ops,
  97. .flags = DM_FLAG_PRE_RELOC,
  98. };
  99. static int clk_sam9x5_peripheral_enable(struct clk *clk)
  100. {
  101. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
  102. if (periph->id < PERIPHERAL_ID_MIN)
  103. return 0;
  104. pmc_write(periph->base, periph->layout->offset,
  105. (periph->id & periph->layout->pid_mask));
  106. pmc_update_bits(periph->base, periph->layout->offset,
  107. periph->layout->cmd | AT91_PMC_PCR_EN,
  108. periph->layout->cmd | AT91_PMC_PCR_EN);
  109. return 0;
  110. }
  111. static int clk_sam9x5_peripheral_disable(struct clk *clk)
  112. {
  113. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
  114. if (periph->id < PERIPHERAL_ID_MIN)
  115. return -EINVAL;
  116. pmc_write(periph->base, periph->layout->offset,
  117. (periph->id & periph->layout->pid_mask));
  118. pmc_update_bits(periph->base, periph->layout->offset,
  119. AT91_PMC_PCR_EN | periph->layout->cmd,
  120. periph->layout->cmd);
  121. return 0;
  122. }
  123. static ulong clk_sam9x5_peripheral_get_rate(struct clk *clk)
  124. {
  125. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
  126. ulong parent_rate = clk_get_parent_rate(clk);
  127. u32 val, shift = ffs(periph->layout->div_mask) - 1;
  128. if (!parent_rate)
  129. return 0;
  130. pmc_write(periph->base, periph->layout->offset,
  131. (periph->id & periph->layout->pid_mask));
  132. pmc_read(periph->base, periph->layout->offset, &val);
  133. shift = (val & periph->layout->div_mask) >> shift;
  134. return parent_rate >> shift;
  135. }
  136. static ulong clk_sam9x5_peripheral_set_rate(struct clk *clk, ulong rate)
  137. {
  138. struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);
  139. ulong parent_rate = clk_get_parent_rate(clk);
  140. int shift;
  141. if (!parent_rate)
  142. return 0;
  143. if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
  144. if (parent_rate == rate)
  145. return rate;
  146. else
  147. return 0;
  148. }
  149. if (periph->range.max && rate > periph->range.max)
  150. return 0;
  151. for (shift = 0; shift <= PERIPHERAL_MAX_SHIFT; shift++) {
  152. if (parent_rate >> shift <= rate)
  153. break;
  154. }
  155. if (shift == PERIPHERAL_MAX_SHIFT + 1)
  156. return 0;
  157. pmc_write(periph->base, periph->layout->offset,
  158. (periph->id & periph->layout->pid_mask));
  159. pmc_update_bits(periph->base, periph->layout->offset,
  160. periph->layout->div_mask | periph->layout->cmd,
  161. (shift << (ffs(periph->layout->div_mask) - 1)) |
  162. periph->layout->cmd);
  163. return parent_rate >> shift;
  164. }
  165. static const struct clk_ops sam9x5_peripheral_ops = {
  166. .enable = clk_sam9x5_peripheral_enable,
  167. .disable = clk_sam9x5_peripheral_disable,
  168. .get_rate = clk_sam9x5_peripheral_get_rate,
  169. .set_rate = clk_sam9x5_peripheral_set_rate,
  170. };
  171. struct clk *
  172. at91_clk_register_sam9x5_peripheral(void __iomem *base,
  173. const struct clk_pcr_layout *layout,
  174. const char *name, const char *parent_name,
  175. u32 id, const struct clk_range *range)
  176. {
  177. struct clk_sam9x5_peripheral *periph;
  178. struct clk *clk;
  179. int ret;
  180. if (!base || !layout || !name || !parent_name || !range)
  181. return ERR_PTR(-EINVAL);
  182. periph = kzalloc(sizeof(*periph), GFP_KERNEL);
  183. if (!periph)
  184. return ERR_PTR(-ENOMEM);
  185. periph->id = id;
  186. periph->base = base;
  187. periph->layout = layout;
  188. periph->range = *range;
  189. clk = &periph->clk;
  190. clk->flags = CLK_GET_RATE_NOCACHE;
  191. ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X5_PERIPH, name,
  192. parent_name);
  193. if (ret) {
  194. kfree(periph);
  195. clk = ERR_PTR(ret);
  196. }
  197. return clk;
  198. }
  199. U_BOOT_DRIVER(at91_sam9x5_periph_clk) = {
  200. .name = UBOOT_DM_CLK_AT91_SAM9X5_PERIPH,
  201. .id = UCLASS_CLK,
  202. .ops = &sam9x5_peripheral_ops,
  203. .flags = DM_FLAG_PRE_RELOC,
  204. };