Kconfig 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
  1. config CLK_AT91
  2. bool "AT91 clock drivers"
  3. depends on CLK
  4. select MISC
  5. help
  6. This option is used to enable the AT91 clock driver.
  7. The driver supports the AT91 clock generator, including
  8. the oscillators and PLLs, such as main clock, slow clock,
  9. PLLA, UTMI PLL. Clocks can also be a source clock of other
  10. clocks a tree structure, such as master clock, usb device
  11. clock, matrix clock and generic clock.
  12. Devices can use a common clock API to request a particular
  13. clock, enable it and get its rate.
  14. config AT91_UTMI
  15. bool "Support UTMI PLL Clock"
  16. depends on CLK_AT91
  17. select REGMAP
  18. select SPL_REGMAP if SPL_DM
  19. select SYSCON
  20. select SPL_SYSCON if SPL_DM
  21. help
  22. This option is used to enable the AT91 UTMI PLL clock
  23. driver. It is the clock provider of USB, and UPLLCK is the
  24. output of 480 MHz UTMI PLL, The souce clock of the UTMI
  25. PLL is the main clock, so the main clock must select the
  26. fast crystal oscillator to meet the frequency accuracy
  27. required by USB.
  28. config AT91_USB_CLK
  29. bool "Support USB OHCI Input Clock"
  30. depends on CLK_AT91
  31. help
  32. This option is used to enable the USB Input Clock, from
  33. the device tree, configure the USBS bit (PLLA or UTMI PLL)
  34. and USBDIV field of the PMC_USB register.
  35. config AT91_H32MX
  36. bool "Support H32MX 32-bit Matrix Clock"
  37. depends on CLK_AT91
  38. help
  39. This option is used to enable the AT91 H32MX matrixes
  40. clock driver. There are H64MX and H32MX matrixes clocks,
  41. H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit
  42. matrix clock is to be configured as MCK if MCK does not
  43. exceed 83 MHz, else it is to be configured as MCK/2.
  44. config AT91_GENERIC_CLK
  45. bool "Support Generic Clock"
  46. depends on CLK_AT91
  47. help
  48. This option is used to enable the AT91 generic clock
  49. driver. Some peripherals may need a second clock source
  50. that may be different from the system clock. This second
  51. clock is the generic clock (GCLK) and is managed by
  52. the PMC via PMC_PCR register.
  53. config AT91_SAM9X60_PLL
  54. bool "PLL support for SAM9X60 SoCs"
  55. depends on CLK_AT91
  56. help
  57. This option is used to enable the AT91 SAM9X60's PLL clock
  58. driver.