clk.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2007
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. */
  8. #ifndef __ASM_ARM_ARCH_CLK_H__
  9. #define __ASM_ARM_ARCH_CLK_H__
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/at91_pmc.h>
  12. #include <asm/global_data.h>
  13. #define GCK_CSS_SLOW_CLK 0
  14. #define GCK_CSS_MAIN_CLK 1
  15. #define GCK_CSS_PLLA_CLK 2
  16. #define GCK_CSS_UPLL_CLK 3
  17. #define GCK_CSS_MCK_CLK 4
  18. #define GCK_CSS_AUDIO_CLK 5
  19. #define AT91_UTMI_PLL_CLK_FREQ 480000000
  20. static inline unsigned long get_cpu_clk_rate(void)
  21. {
  22. DECLARE_GLOBAL_DATA_PTR;
  23. return gd->arch.cpu_clk_rate_hz;
  24. }
  25. static inline unsigned long get_main_clk_rate(void)
  26. {
  27. DECLARE_GLOBAL_DATA_PTR;
  28. return gd->arch.main_clk_rate_hz;
  29. }
  30. static inline unsigned long get_mck_clk_rate(void)
  31. {
  32. DECLARE_GLOBAL_DATA_PTR;
  33. return gd->arch.mck_rate_hz;
  34. }
  35. static inline unsigned long get_plla_clk_rate(void)
  36. {
  37. DECLARE_GLOBAL_DATA_PTR;
  38. return gd->arch.plla_rate_hz;
  39. }
  40. static inline unsigned long get_pllb_clk_rate(void)
  41. {
  42. DECLARE_GLOBAL_DATA_PTR;
  43. return gd->arch.pllb_rate_hz;
  44. }
  45. static inline u32 get_pllb_init(void)
  46. {
  47. DECLARE_GLOBAL_DATA_PTR;
  48. return gd->arch.at91_pllb_usb_init;
  49. }
  50. #ifdef CPU_HAS_H32MXDIV
  51. static inline unsigned int get_h32mxdiv(void)
  52. {
  53. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  54. return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
  55. }
  56. #else
  57. static inline unsigned int get_h32mxdiv(void)
  58. {
  59. return 0;
  60. }
  61. #endif
  62. static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
  63. {
  64. if (get_h32mxdiv())
  65. return get_mck_clk_rate() / 2;
  66. else
  67. return get_mck_clk_rate();
  68. }
  69. static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
  70. {
  71. if (get_h32mxdiv())
  72. return get_mck_clk_rate() / 2;
  73. else
  74. return get_mck_clk_rate();
  75. }
  76. static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
  77. {
  78. return get_mck_clk_rate();
  79. }
  80. static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
  81. {
  82. if (get_h32mxdiv())
  83. return get_mck_clk_rate() / 2;
  84. else
  85. return get_mck_clk_rate();
  86. }
  87. static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
  88. {
  89. if (get_h32mxdiv())
  90. return get_mck_clk_rate() / 2;
  91. else
  92. return get_mck_clk_rate();
  93. }
  94. static inline unsigned long get_mci_clk_rate(void)
  95. {
  96. if (get_h32mxdiv())
  97. return get_mck_clk_rate() / 2;
  98. else
  99. return get_mck_clk_rate();
  100. }
  101. static inline unsigned long get_pit_clk_rate(void)
  102. {
  103. if (get_h32mxdiv())
  104. return get_mck_clk_rate() / 2;
  105. else
  106. return get_mck_clk_rate();
  107. }
  108. int at91_clock_init(unsigned long main_clock);
  109. void at91_periph_clk_enable(int id);
  110. void at91_periph_clk_disable(int id);
  111. int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
  112. u32 at91_get_periph_generated_clk(u32 id);
  113. void at91_system_clk_enable(int sys_clk);
  114. void at91_system_clk_disable(int sys_clk);
  115. int at91_upll_clk_enable(void);
  116. int at91_upll_clk_disable(void);
  117. void at91_usb_clk_init(u32 value);
  118. int at91_pllb_clk_enable(u32 pllbr);
  119. int at91_pllb_clk_disable(void);
  120. void at91_pllicpr_init(u32 icpr);
  121. #endif /* __ASM_ARM_ARCH_CLK_H__ */