at91sam9x5_matrix.h 3.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Matrix-centric header file for the AT91SAM9X5 family
  4. *
  5. * Copyright (C) 2012-2013 Atmel Corporation.
  6. *
  7. * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  8. * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
  9. */
  10. #ifndef __AT91SAM9X5_MATRIX_H__
  11. #define __AT91SAM9X5_MATRIX_H__
  12. #ifndef __ASSEMBLY__
  13. /* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
  14. struct at91_matrix {
  15. u32 mcfg[16];
  16. u32 scfg[16];
  17. u32 pras[16][2];
  18. u32 mrcr; /* 0x100 Master Remap Control */
  19. u32 filler[5];
  20. #ifdef CONFIG_AT91SAM9X5
  21. u32 filler1[2];
  22. #endif
  23. /* EBI Chip Select Assignment Register
  24. * 0x118: AT91SAM9N12
  25. * 0x120: AT91SAM9X5
  26. */
  27. u32 ebicsa;
  28. u32 filler4[47];
  29. #ifdef CONFIG_AT91SAM9N12
  30. u32 filler5[2];
  31. #endif
  32. u32 wpmr;
  33. u32 wpsr;
  34. };
  35. #endif /* __ASSEMBLY__ */
  36. #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
  37. #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
  38. #define AT91_MATRIX_ULBT_FOUR (2 << 0)
  39. #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
  40. #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
  41. #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
  42. #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
  43. #define AT91_MATRIX_ULBT_128 (7 << 0)
  44. #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
  45. #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
  46. #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
  47. #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
  48. #define AT91_MATRIX_M0PR_SHIFT 0
  49. #define AT91_MATRIX_M1PR_SHIFT 4
  50. #define AT91_MATRIX_M2PR_SHIFT 8
  51. #define AT91_MATRIX_M3PR_SHIFT 12
  52. #define AT91_MATRIX_M4PR_SHIFT 16
  53. #define AT91_MATRIX_M5PR_SHIFT 20
  54. #define AT91_MATRIX_M6PR_SHIFT 24
  55. #define AT91_MATRIX_M7PR_SHIFT 28
  56. #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
  57. #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
  58. #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
  59. #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
  60. #define AT91_MATRIX_RCB0 (1 << 0)
  61. #define AT91_MATRIX_RCB1 (1 << 1)
  62. #define AT91_MATRIX_RCB2 (1 << 2)
  63. #define AT91_MATRIX_RCB3 (1 << 3)
  64. #define AT91_MATRIX_RCB4 (1 << 4)
  65. #define AT91_MATRIX_RCB5 (1 << 5)
  66. #define AT91_MATRIX_RCB6 (1 << 6)
  67. #define AT91_MATRIX_RCB7 (1 << 7)
  68. #define AT91_MATRIX_RCB8 (1 << 8)
  69. #define AT91_MATRIX_RCB9 (1 << 9)
  70. #define AT91_MATRIX_RCB10 (1 << 10)
  71. #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
  72. #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
  73. #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
  74. #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
  75. #define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
  76. #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
  77. #define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
  78. #define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
  79. #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
  80. #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
  81. #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
  82. #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
  83. #define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
  84. #define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
  85. #define AT91_MATRIX_MP_OFF (0 << 25)
  86. #define AT91_MATRIX_MP_ON (1 << 25)
  87. #endif