at91sam9g45_matrix.h 3.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Matrix-centric header file for the AT91SAM9M1x family
  4. *
  5. * Copyright (C) 2008 Atmel Corporation.
  6. *
  7. * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  8. * Based on AT91SAM9G45 preliminary datasheet.
  9. */
  10. #ifndef AT91SAM9G45_MATRIX_H
  11. #define AT91SAM9G45_MATRIX_H
  12. #ifndef __ASSEMBLY__
  13. struct at91_matrix {
  14. u32 mcfg[16];
  15. u32 scfg[16];
  16. u32 pras[16][2];
  17. u32 mrcr; /* 0x100 Master Remap Control */
  18. u32 filler[3];
  19. u32 tcmr;
  20. u32 filler2;
  21. u32 ddrmpr;
  22. u32 filler3[3];
  23. u32 ebicsa;
  24. u32 filler4[47];
  25. u32 wpmr;
  26. u32 wpsr;
  27. };
  28. #endif /* __ASSEMBLY__ */
  29. #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
  30. #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
  31. #define AT91_MATRIX_ULBT_FOUR (2 << 0)
  32. #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
  33. #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
  34. #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
  35. #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
  36. #define AT91_MATRIX_ULBT_128 (7 << 0)
  37. #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
  38. #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
  39. #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
  40. #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
  41. #define AT91_MATRIX_M0PR_SHIFT 0
  42. #define AT91_MATRIX_M1PR_SHIFT 4
  43. #define AT91_MATRIX_M2PR_SHIFT 8
  44. #define AT91_MATRIX_M3PR_SHIFT 12
  45. #define AT91_MATRIX_M4PR_SHIFT 16
  46. #define AT91_MATRIX_M5PR_SHIFT 20
  47. #define AT91_MATRIX_M6PR_SHIFT 24
  48. #define AT91_MATRIX_M7PR_SHIFT 28
  49. #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
  50. #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
  51. #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
  52. #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
  53. #define AT91_MATRIX_RCB0 (1 << 0)
  54. #define AT91_MATRIX_RCB1 (1 << 1)
  55. #define AT91_MATRIX_RCB2 (1 << 2)
  56. #define AT91_MATRIX_RCB3 (1 << 3)
  57. #define AT91_MATRIX_RCB4 (1 << 4)
  58. #define AT91_MATRIX_RCB5 (1 << 5)
  59. #define AT91_MATRIX_RCB6 (1 << 6)
  60. #define AT91_MATRIX_RCB7 (1 << 7)
  61. #define AT91_MATRIX_RCB8 (1 << 8)
  62. #define AT91_MATRIX_RCB9 (1 << 9)
  63. #define AT91_MATRIX_RCB10 (1 << 10)
  64. #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
  65. #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
  66. #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
  67. #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
  68. #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
  69. #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
  70. #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
  71. #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
  72. #define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
  73. #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
  74. #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
  75. #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
  76. #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
  77. #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
  78. #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
  79. #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
  80. #endif