at91sam9_smc.h 2.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h]
  4. *
  5. * Copyright (C) 2007 Andrew Victor
  6. * Copyright (C) 2007 Atmel Corporation.
  7. *
  8. * Static Memory Controllers (SMC) - System peripherals registers.
  9. * Based on AT91SAM9261 datasheet revision D.
  10. */
  11. #ifndef AT91SAM9_SMC_H
  12. #define AT91SAM9_SMC_H
  13. #ifdef __ASSEMBLY__
  14. #ifndef ATMEL_BASE_SMC
  15. #define ATMEL_BASE_SMC ATMEL_BASE_SMC0
  16. #endif
  17. #define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
  18. #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
  19. #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
  20. #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
  21. #else
  22. typedef struct at91_cs {
  23. u32 setup; /* 0x00 SMC Setup Register */
  24. u32 pulse; /* 0x04 SMC Pulse Register */
  25. u32 cycle; /* 0x08 SMC Cycle Register */
  26. u32 mode; /* 0x0C SMC Mode Register */
  27. } at91_cs_t;
  28. typedef struct at91_smc {
  29. at91_cs_t cs[8];
  30. } at91_smc_t;
  31. #endif /* __ASSEMBLY__ */
  32. #define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
  33. #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
  34. #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
  35. #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
  36. #define AT91_SMC_PULSE_NWE(x) (x & 0x7f)
  37. #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8)
  38. #define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16)
  39. #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24)
  40. #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
  41. #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
  42. #define AT91_SMC_MODE_RM_NCS 0x00000000
  43. #define AT91_SMC_MODE_RM_NRD 0x00000001
  44. #define AT91_SMC_MODE_WM_NCS 0x00000000
  45. #define AT91_SMC_MODE_WM_NWE 0x00000002
  46. #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
  47. #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
  48. #define AT91_SMC_MODE_EXNW_READY 0x00000030
  49. #define AT91_SMC_MODE_BAT 0x00000100
  50. #define AT91_SMC_MODE_DBW_8 0x00000000
  51. #define AT91_SMC_MODE_DBW_16 0x00001000
  52. #define AT91_SMC_MODE_DBW_32 0x00002000
  53. #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
  54. #define AT91_SMC_MODE_TDF 0x00100000
  55. #define AT91_SMC_MODE_PMEN 0x01000000
  56. #define AT91_SMC_MODE_PS_4 0x00000000
  57. #define AT91_SMC_MODE_PS_8 0x10000000
  58. #define AT91_SMC_MODE_PS_16 0x20000000
  59. #define AT91_SMC_MODE_PS_32 0x30000000
  60. #endif