at91sam9_sdramc.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
  4. *
  5. * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. * Copyright (C) 2007 Andrew Victor
  7. * Copyright (C) 2007 Atmel Corporation.
  8. *
  9. * SDRAM Controllers (SDRAMC) - System peripherals registers.
  10. * Based on AT91SAM9261 datasheet revision D.
  11. */
  12. #ifndef AT91SAM9_SDRAMC_H
  13. #define AT91SAM9_SDRAMC_H
  14. #ifdef __ASSEMBLY__
  15. #ifndef ATMEL_BASE_SDRAMC
  16. #define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0
  17. #endif
  18. #define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
  19. #define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
  20. #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
  21. #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
  22. #else
  23. struct sdramc_reg {
  24. u32 mr;
  25. u32 tr;
  26. u32 cr;
  27. u32 lpr;
  28. u32 ier;
  29. u32 idr;
  30. u32 imr;
  31. u32 isr;
  32. u32 mdr;
  33. };
  34. int sdramc_initialize(unsigned int sdram_address,
  35. const struct sdramc_reg *p);
  36. #endif
  37. /* SDRAM Controller (SDRAMC) registers */
  38. #define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
  39. #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
  40. #define AT91_SDRAMC_MODE_NORMAL 0
  41. #define AT91_SDRAMC_MODE_NOP 1
  42. #define AT91_SDRAMC_MODE_PRECHARGE 2
  43. #define AT91_SDRAMC_MODE_LMR 3
  44. #define AT91_SDRAMC_MODE_REFRESH 4
  45. #define AT91_SDRAMC_MODE_EXT_LMR 5
  46. #define AT91_SDRAMC_MODE_DEEP 6
  47. #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
  48. #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
  49. #define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
  50. #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
  51. #define AT91_SDRAMC_NC_8 (0 << 0)
  52. #define AT91_SDRAMC_NC_9 (1 << 0)
  53. #define AT91_SDRAMC_NC_10 (2 << 0)
  54. #define AT91_SDRAMC_NC_11 (3 << 0)
  55. #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
  56. #define AT91_SDRAMC_NR_11 (0 << 2)
  57. #define AT91_SDRAMC_NR_12 (1 << 2)
  58. #define AT91_SDRAMC_NR_13 (2 << 2)
  59. #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
  60. #define AT91_SDRAMC_NB_2 (0 << 4)
  61. #define AT91_SDRAMC_NB_4 (1 << 4)
  62. #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
  63. #define AT91_SDRAMC_CAS_1 (1 << 5)
  64. #define AT91_SDRAMC_CAS_2 (2 << 5)
  65. #define AT91_SDRAMC_CAS_3 (3 << 5)
  66. #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
  67. #define AT91_SDRAMC_DBW_32 (0 << 7)
  68. #define AT91_SDRAMC_DBW_16 (1 << 7)
  69. #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
  70. #define AT91_SDRAMC_TWR_VAL(x) (x << 8)
  71. #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
  72. #define AT91_SDRAMC_TRC_VAL(x) (x << 12)
  73. #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
  74. #define AT91_SDRAMC_TRP_VAL(x) (x << 16)
  75. #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
  76. #define AT91_SDRAMC_TRCD_VAL(x) (x << 20)
  77. #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
  78. #define AT91_SDRAMC_TRAS_VAL(x) (x << 24)
  79. #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
  80. #define AT91_SDRAMC_TXSR_VAL(x) (x << 28)
  81. #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
  82. #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
  83. #define AT91_SDRAMC_LPCB_DISABLE 0
  84. #define AT91_SDRAMC_LPCB_SELF_REFRESH 1
  85. #define AT91_SDRAMC_LPCB_POWER_DOWN 2
  86. #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
  87. #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
  88. #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
  89. #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
  90. #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
  91. #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
  92. #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
  93. #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
  94. #define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
  95. #define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
  96. #define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
  97. #define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
  98. #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
  99. #define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
  100. #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
  101. #define AT91_SDRAMC_MD_SDRAM 0
  102. #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
  103. #endif