at91sam9263.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
  4. *
  5. * (C) 2007 Atmel Corporation.
  6. * (C) Copyright 2010
  7. * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
  8. *
  9. * Definitions for the SoC:
  10. * AT91SAM9263
  11. */
  12. #ifndef AT91SAM9263_H
  13. #define AT91SAM9263_H
  14. /*
  15. * Peripheral identifiers/interrupts.
  16. */
  17. #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
  18. #define ATMEL_ID_SYS 1 /* System Peripherals */
  19. #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
  20. #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
  21. #define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
  22. /* Reserved: 5 */
  23. /* Reserved: 6 */
  24. #define ATMEL_ID_USART0 7 /* USART 0 */
  25. #define ATMEL_ID_USART1 8 /* USART 1 */
  26. #define ATMEL_ID_USART2 9 /* USART 2 */
  27. #define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */
  28. #define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */
  29. #define ATMEL_ID_CAN 12 /* CAN */
  30. #define ATMEL_ID_TWI 13 /* Two-Wire Interface */
  31. #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
  32. #define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
  33. #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
  34. #define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */
  35. #define ATMEL_ID_AC97C 18 /* AC97 Controller */
  36. #define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
  37. #define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */
  38. #define ATMEL_ID_EMAC 21 /* Ethernet */
  39. /* Reserved: 22 */
  40. #define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */
  41. #define ATMEL_ID_UDP 24 /* USB Device Port */
  42. #define ATMEL_ID_ISI 25 /* Image Sensor Interface */
  43. #define ATMEL_ID_LCDC 26 /* LCD Controller */
  44. #define ATMEL_ID_DMA 27 /* DMA Controller */
  45. /* Reserved: 28 */
  46. #define ATMEL_ID_UHP 29 /* USB Host port */
  47. #define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
  48. #define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
  49. /*
  50. * User Peripherals physical base addresses.
  51. */
  52. #define ATMEL_BASE_UDP 0xfff78000
  53. #define ATMEL_BASE_TCB0 0xfff7c000
  54. #define ATMEL_BASE_TC0 0xfff7c000
  55. #define ATMEL_BASE_TC1 0xfff7c040
  56. #define ATMEL_BASE_TC2 0xfff7c080
  57. #define ATMEL_BASE_MCI0 0xfff80000
  58. #define ATMEL_BASE_MCI1 0xfff84000
  59. #define ATMEL_BASE_TWI 0xfff88000
  60. #define ATMEL_BASE_USART0 0xfff8c000
  61. #define ATMEL_BASE_USART1 0xfff90000
  62. #define ATMEL_BASE_USART2 0xfff94000
  63. #define ATMEL_BASE_SSC0 0xfff98000
  64. #define ATMEL_BASE_SSC1 0xfff9c000
  65. #define ATMEL_BASE_AC97C 0xfffa0000
  66. #define ATMEL_BASE_SPI0 0xfffa4000
  67. #define ATMEL_BASE_SPI1 0xfffa8000
  68. #define ATMEL_BASE_CAN 0xfffac000
  69. #define ATMEL_BASE_PWMC 0xfffb8000
  70. #define ATMEL_BASE_EMAC 0xfffbc000
  71. #define ATMEL_BASE_ISI 0xfffc4000
  72. #define ATMEL_BASE_2DGE 0xfffc8000
  73. /*
  74. * System Peripherals physical base addresses.
  75. */
  76. #define ATMEL_BASE_ECC0 0xffffe000
  77. #define ATMEL_BASE_SDRAMC0 0xffffe200
  78. #define ATMEL_BASE_SMC0 0xffffe400
  79. #define ATMEL_BASE_ECC1 0xffffe600
  80. #define ATMEL_BASE_SDRAMC1 0xffffe800
  81. #define ATMEL_BASE_SMC1 0xffffea00
  82. #define ATMEL_BASE_MATRIX 0xffffec00
  83. #define ATMEL_BASE_CCFG 0xffffed10
  84. #define ATMEL_BASE_DBGU 0xffffee00
  85. #define ATMEL_BASE_AIC 0xfffff000
  86. #define ATMEL_BASE_PIOA 0xfffff200
  87. #define ATMEL_BASE_PIOB 0xfffff400
  88. #define ATMEL_BASE_PIOC 0xfffff600
  89. #define ATMEL_BASE_PIOD 0xfffff800
  90. #define ATMEL_BASE_PIOE 0xfffffa00
  91. #define ATMEL_BASE_PMC 0xfffffc00
  92. #define ATMEL_BASE_RSTC 0xfffffd00
  93. #define ATMEL_BASE_SHDWC 0xfffffd10
  94. #define ATMEL_BASE_RTT0 0xfffffd20
  95. #define ATMEL_BASE_PIT 0xfffffd30
  96. #define ATMEL_BASE_WDT 0xfffffd40
  97. #define ATMEL_BASE_RTT1 0xfffffd50
  98. #define ATMEL_BASE_GPBR 0xfffffd60
  99. /*
  100. * Internal Memory.
  101. */
  102. #define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */
  103. #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */
  104. #define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */
  105. #define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */
  106. #define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */
  107. #define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */
  108. /*
  109. * External memory
  110. */
  111. #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
  112. #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
  113. #define ATMEL_BASE_CS2 0x30000000
  114. #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
  115. #define ATMEL_BASE_CS4 0x50000000
  116. #define ATMEL_BASE_CS5 0x60000000
  117. #define ATMEL_BASE_CS6 0x70000000
  118. #define ATMEL_BASE_CS7 0x80000000
  119. /* Timer */
  120. #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
  121. /*
  122. * Other misc defines
  123. */
  124. #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
  125. #define ATMEL_BASE_PIO ATMEL_BASE_PIOA
  126. #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
  127. /*
  128. * Cpu Name
  129. */
  130. #define ATMEL_CPU_NAME "AT91SAM9263"
  131. #endif