at91_tc.h 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  4. */
  5. #ifndef AT91_TC_H
  6. #define AT91_TC_H
  7. typedef struct at91_tcc {
  8. u32 ccr; /* 0x00 Channel Control Register */
  9. u32 cmr; /* 0x04 Channel Mode Register */
  10. u32 reserved1[2];
  11. u32 cv; /* 0x10 Counter Value */
  12. u32 ra; /* 0x14 Register A */
  13. u32 rb; /* 0x18 Register B */
  14. u32 rc; /* 0x1C Register C */
  15. u32 sr; /* 0x20 Status Register */
  16. u32 ier; /* 0x24 Interrupt Enable Register */
  17. u32 idr; /* 0x28 Interrupt Disable Register */
  18. u32 imr; /* 0x2C Interrupt Mask Register */
  19. u32 reserved3[4];
  20. } at91_tcc_t;
  21. #define AT91_TC_CCR_CLKEN 0x00000001
  22. #define AT91_TC_CCR_CLKDIS 0x00000002
  23. #define AT91_TC_CCR_SWTRG 0x00000004
  24. #define AT91_TC_CMR_CPCTRG 0x00004000
  25. #define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
  26. #define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
  27. #define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
  28. #define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
  29. #define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
  30. #define AT91_TC_CMR_TCCLKS_XC0 0x00000005
  31. #define AT91_TC_CMR_TCCLKS_XC1 0x00000006
  32. #define AT91_TC_CMR_TCCLKS_XC2 0x00000007
  33. typedef struct at91_tc {
  34. at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
  35. u32 bcr; /* 0xC0 TC Block Control Register */
  36. u32 bmr; /* 0xC4 TC Block Mode Register */
  37. } at91_tc_t;
  38. #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
  39. #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
  40. #define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
  41. #define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
  42. #define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
  43. #define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
  44. #define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
  45. #define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
  46. #define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
  47. #define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
  48. #define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
  49. #define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
  50. #endif