at91_spi.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
  4. *
  5. * Copyright (C) 2005 Ivan Kokshaysky
  6. * Copyright (C) SAN People
  7. *
  8. * Serial Peripheral Interface (SPI) registers.
  9. * Based on AT91RM9200 datasheet revision E.
  10. */
  11. #ifndef AT91_SPI_H
  12. #define AT91_SPI_H
  13. #include <asm/arch/at91_pdc.h>
  14. typedef struct at91_spi {
  15. u32 cr; /* 0x00 Control Register */
  16. u32 mr; /* 0x04 Mode Register */
  17. u32 rdr; /* 0x08 Receive Data Register */
  18. u32 tdr; /* 0x0C Transmit Data Register */
  19. u32 sr; /* 0x10 Status Register */
  20. u32 ier; /* 0x14 Interrupt Enable Register */
  21. u32 idr; /* 0x18 Interrupt Disable Register */
  22. u32 imr; /* 0x1C Interrupt Mask Register */
  23. u32 reserve1[4];
  24. u32 csr[4]; /* 0x30 Chip Select Register 0-3 */
  25. u32 reserve2[48];
  26. at91_pdc_t pdc;
  27. } at91_spi_t;
  28. #ifdef CONFIG_ATMEL_LEGACY
  29. #define AT91_SPI_CR 0x00 /* Control Register */
  30. #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
  31. #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
  32. #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
  33. #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
  34. #define AT91_SPI_MR 0x04 /* Mode Register */
  35. #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
  36. #define AT91_SPI_PS (1 << 1) /* Peripheral Select */
  37. #define AT91_SPI_PS_FIXED (0 << 1)
  38. #define AT91_SPI_PS_VARIABLE (1 << 1)
  39. #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
  40. #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
  41. #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
  42. #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
  43. #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
  44. #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
  45. #define AT91_SPI_RDR 0x08 /* Receive Data Register */
  46. #define AT91_SPI_RD (0xffff << 0) /* Receive Data */
  47. #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
  48. #define AT91_SPI_TDR 0x0c /* Transmit Data Register */
  49. #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
  50. #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
  51. #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
  52. #define AT91_SPI_SR 0x10 /* Status Register */
  53. #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
  54. #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
  55. #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
  56. #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
  57. #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
  58. #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
  59. #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
  60. #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
  61. #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
  62. #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
  63. #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
  64. #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
  65. #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
  66. #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
  67. #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
  68. #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
  69. #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
  70. #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
  71. #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
  72. #define AT91_SPI_BITS_8 (0 << 4)
  73. #define AT91_SPI_BITS_9 (1 << 4)
  74. #define AT91_SPI_BITS_10 (2 << 4)
  75. #define AT91_SPI_BITS_11 (3 << 4)
  76. #define AT91_SPI_BITS_12 (4 << 4)
  77. #define AT91_SPI_BITS_13 (5 << 4)
  78. #define AT91_SPI_BITS_14 (6 << 4)
  79. #define AT91_SPI_BITS_15 (7 << 4)
  80. #define AT91_SPI_BITS_16 (8 << 4)
  81. #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
  82. #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
  83. #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
  84. #define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */
  85. #define AT91_SPI_RCR 0x0104 /* Receive Counter Register */
  86. #define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */
  87. #define AT91_SPI_TCR 0x010c /* Transmit Counter Register */
  88. #define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */
  89. #define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */
  90. #define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */
  91. #define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */
  92. #define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */
  93. #define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */
  94. #define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */
  95. #define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */
  96. #define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */
  97. #define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
  98. #endif /* CONFIG_ATMEL_LEGACY */
  99. #endif