at91_matrix.h 8.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  4. */
  5. #ifndef AT91_MATRIX_H
  6. #define AT91_MATRIX_H
  7. #ifdef __ASSEMBLY__
  8. #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
  9. #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
  10. #elif defined(CONFIG_AT91SAM9261)
  11. #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
  12. #elif defined(CONFIG_AT91SAM9263)
  13. #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
  14. #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  15. #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
  16. #else
  17. #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
  18. #endif
  19. #define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
  20. #else
  21. #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
  22. #define AT91_MATRIX_MASTERS 6
  23. #define AT91_MATRIX_SLAVES 5
  24. #elif defined(CONFIG_AT91SAM9261)
  25. #define AT91_MATRIX_MASTERS 1
  26. #define AT91_MATRIX_SLAVES 5
  27. #elif defined(CONFIG_AT91SAM9263)
  28. #define AT91_MATRIX_MASTERS 9
  29. #define AT91_MATRIX_SLAVES 7
  30. #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  31. #define AT91_MATRIX_MASTERS 11
  32. #define AT91_MATRIX_SLAVES 8
  33. #else
  34. #error CPU not supported. Please update at91_matrix.h
  35. #endif
  36. typedef struct at91_priority {
  37. u32 a;
  38. u32 b;
  39. } at91_priority_t;
  40. typedef struct at91_matrix {
  41. u32 mcfg[AT91_MATRIX_MASTERS];
  42. #if defined(CONFIG_AT91SAM9261)
  43. u32 scfg[AT91_MATRIX_SLAVES];
  44. u32 res61_1[3];
  45. u32 tcr;
  46. u32 res61_2[2];
  47. u32 csa;
  48. u32 pucr;
  49. u32 res61_3[114];
  50. #else
  51. u32 reserve1[16 - AT91_MATRIX_MASTERS];
  52. u32 scfg[AT91_MATRIX_SLAVES];
  53. u32 reserve2[16 - AT91_MATRIX_SLAVES];
  54. at91_priority_t pr[AT91_MATRIX_SLAVES];
  55. u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
  56. u32 mrcr; /* 0x100 Master Remap Control */
  57. u32 reserve4[3];
  58. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  59. u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
  60. u32 womr; /* 0x1E4 Write Protect Mode */
  61. u32 wpsr; /* 0x1E8 Write Protect Status */
  62. u32 resg45_1[10];
  63. #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
  64. u32 res60_1[3];
  65. u32 csa;
  66. u32 res60_2[56];
  67. #elif defined(CONFIG_AT91SAM9263)
  68. u32 res63_1;
  69. u32 tcmr;
  70. u32 res63_2[2];
  71. u32 csa[2];
  72. u32 res63_3[54];
  73. #else
  74. u32 reserve5[60];
  75. #endif
  76. #endif
  77. } at91_matrix_t;
  78. #endif /* __ASSEMBLY__ */
  79. #define AT91_MATRIX_CSA_DBPUC 0x00000100
  80. #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
  81. #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
  82. #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
  83. #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
  84. #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
  85. #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
  86. #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
  87. #if defined CONFIG_AT91SAM9261
  88. /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
  89. #define AT91_MATRIX_MCFG_RCB0 (1 << 0)
  90. /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
  91. #define AT91_MATRIX_MCFG_RCB1 (1 << 1)
  92. #endif
  93. /* Undefined Length Burst Type */
  94. #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
  95. defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  96. #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
  97. #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
  98. #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
  99. #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
  100. #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
  101. #endif
  102. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  103. #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
  104. #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
  105. #define AT91_MATRIX_MCFG_ULBT_128 0x00000007
  106. #endif
  107. /* Default Master Type */
  108. #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
  109. #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
  110. #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
  111. /* Fixed Index of Default Master */
  112. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \
  113. defined(CONFIG_AT91SAM9M10G45)
  114. #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
  115. #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
  116. #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
  117. #endif
  118. /* Maximum Number of Allowed Cycles for a Burst */
  119. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  120. #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
  121. #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
  122. defined(CONFIG_AT91SAM9263)
  123. #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
  124. #endif
  125. /* Arbitration Type */
  126. #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
  127. #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
  128. #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
  129. #endif
  130. /* Master Remap Control Register */
  131. #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
  132. defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  133. /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
  134. #define AT91_MATRIX_MRCR_RCB0 (1 << 0)
  135. /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
  136. #define AT91_MATRIX_MRCR_RCB1 (1 << 1)
  137. #endif
  138. #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
  139. defined(CONFIG_AT91SAM9M10G45)
  140. #define AT91_MATRIX_MRCR_RCB2 0x00000004
  141. #define AT91_MATRIX_MRCR_RCB3 0x00000008
  142. #define AT91_MATRIX_MRCR_RCB4 0x00000010
  143. #define AT91_MATRIX_MRCR_RCB5 0x00000020
  144. #define AT91_MATRIX_MRCR_RCB6 0x00000040
  145. #define AT91_MATRIX_MRCR_RCB7 0x00000080
  146. #define AT91_MATRIX_MRCR_RCB8 0x00000100
  147. #endif
  148. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  149. #define AT91_MATRIX_MRCR_RCB9 0x00000200
  150. #define AT91_MATRIX_MRCR_RCB10 0x00000400
  151. #define AT91_MATRIX_MRCR_RCB11 0x00000800
  152. #endif
  153. /* TCM Configuration Register */
  154. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  155. /* Size of ITCM enabled memory block */
  156. #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
  157. #define AT91_MATRIX_TCMR_ITCM_32 0x00000040
  158. /* Size of DTCM enabled memory block */
  159. #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
  160. #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
  161. #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
  162. /* Wait state TCM register */
  163. #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
  164. #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
  165. #endif
  166. #if defined(CONFIG_AT91SAM9263)
  167. /* Size of ITCM enabled memory block */
  168. #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
  169. #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
  170. #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
  171. /* Size of DTCM enabled memory block */
  172. #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
  173. #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
  174. #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
  175. #endif
  176. #if defined(CONFIG_AT91SAM9261)
  177. /* Size of ITCM enabled memory block */
  178. #define AT91_MATRIX_TCMR_ITCM_0 0x00000000
  179. #define AT91_MATRIX_TCMR_ITCM_16 0x00000005
  180. #define AT91_MATRIX_TCMR_ITCM_32 0x00000006
  181. #define AT91_MATRIX_TCMR_ITCM_64 0x00000007
  182. /* Size of DTCM enabled memory block */
  183. #define AT91_MATRIX_TCMR_DTCM_0 0x00000000
  184. #define AT91_MATRIX_TCMR_DTCM_16 0x00000050
  185. #define AT91_MATRIX_TCMR_DTCM_32 0x00000060
  186. #define AT91_MATRIX_TCMR_DTCM_64 0x00000070
  187. #endif
  188. #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
  189. /* Video Mode Configuration Register */
  190. #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
  191. #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
  192. /* Write Protect Mode Register */
  193. #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
  194. #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
  195. #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
  196. /* Write Protect Status Register */
  197. #define AT91_MATRIX_WPSR_NO_WPV 0x00000000
  198. #define AT91_MATRIX_WPSR_WPV 0x00000001
  199. #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
  200. #endif
  201. /* USB Pad Pull-Up Control Register */
  202. #if defined(CONFIG_AT91SAM9261)
  203. #define AT91_MATRIX_USBPUCR_PUON 0x40000000
  204. #endif
  205. #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
  206. #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
  207. #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
  208. #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
  209. #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
  210. #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
  211. #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
  212. #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
  213. #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
  214. #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
  215. #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
  216. #endif