at91_emac.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  4. *
  5. * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
  6. */
  7. #ifndef AT91_H
  8. #define AT91_H
  9. typedef struct at91_emac {
  10. u32 ctl;
  11. u32 cfg;
  12. u32 sr;
  13. u32 tar;
  14. u32 tcr;
  15. u32 tsr;
  16. u32 rbqp;
  17. u32 reserved0;
  18. u32 rsr;
  19. u32 isr;
  20. u32 ier;
  21. u32 idr;
  22. u32 imr;
  23. u32 man;
  24. u32 reserved1[2];
  25. u32 fra;
  26. u32 scol;
  27. u32 mocl;
  28. u32 ok;
  29. u32 seqe;
  30. u32 ale;
  31. u32 dte;
  32. u32 lcol;
  33. u32 ecol;
  34. u32 cse;
  35. u32 tue;
  36. u32 cde;
  37. u32 elr;
  38. u32 rjb;
  39. u32 usf;
  40. u32 sqee;
  41. u32 drfc;
  42. u32 reserved2[3];
  43. u32 hsh;
  44. u32 hsl;
  45. u32 sa1l;
  46. u32 sa1h;
  47. u32 sa2l;
  48. u32 sa2h;
  49. u32 sa3l;
  50. u32 sa3h;
  51. u32 sa4l;
  52. u32 sa4h;
  53. } at91_emac_t;
  54. #define AT91_EMAC_CTL_LB 0x0001
  55. #define AT91_EMAC_CTL_LBL 0x0002
  56. #define AT91_EMAC_CTL_RE 0x0004
  57. #define AT91_EMAC_CTL_TE 0x0008
  58. #define AT91_EMAC_CTL_MPE 0x0010
  59. #define AT91_EMAC_CTL_CSR 0x0020
  60. #define AT91_EMAC_CTL_ISR 0x0040
  61. #define AT91_EMAC_CTL_WES 0x0080
  62. #define AT91_EMAC_CTL_BP 0x1000
  63. #define AT91_EMAC_CFG_SPD 0x0001
  64. #define AT91_EMAC_CFG_FD 0x0002
  65. #define AT91_EMAC_CFG_BR 0x0004
  66. #define AT91_EMAC_CFG_CAF 0x0010
  67. #define AT91_EMAC_CFG_NBC 0x0020
  68. #define AT91_EMAC_CFG_MTI 0x0040
  69. #define AT91_EMAC_CFG_UNI 0x0080
  70. #define AT91_EMAC_CFG_BIG 0x0100
  71. #define AT91_EMAC_CFG_EAE 0x0200
  72. #define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF
  73. #define AT91_EMAC_CFG_MCLK_8 0x0000
  74. #define AT91_EMAC_CFG_MCLK_16 0x0400
  75. #define AT91_EMAC_CFG_MCLK_32 0x0800
  76. #define AT91_EMAC_CFG_MCLK_64 0x0C00
  77. #define AT91_EMAC_CFG_RTY 0x1000
  78. #define AT91_EMAC_CFG_RMII 0x2000
  79. #define AT91_EMAC_SR_LINK 0x0001
  80. #define AT91_EMAC_SR_MDIO 0x0002
  81. #define AT91_EMAC_SR_IDLE 0x0004
  82. #define AT91_EMAC_TCR_LEN(x) (x & 0x7FF)
  83. #define AT91_EMAC_TCR_NCRC 0x8000
  84. #define AT91_EMAC_TSR_OVR 0x0001
  85. #define AT91_EMAC_TSR_COL 0x0002
  86. #define AT91_EMAC_TSR_RLE 0x0004
  87. #define AT91_EMAC_TSR_TXIDLE 0x0008
  88. #define AT91_EMAC_TSR_BNQ 0x0010
  89. #define AT91_EMAC_TSR_COMP 0x0020
  90. #define AT91_EMAC_TSR_UND 0x0040
  91. #define AT91_EMAC_RSR_BNA 0x0001
  92. #define AT91_EMAC_RSR_REC 0x0002
  93. #define AT91_EMAC_RSR_OVR 0x0004
  94. /* ISR, IER, IDR, IMR use the same bits */
  95. #define AT91_EMAC_IxR_DONE 0x0001
  96. #define AT91_EMAC_IxR_RCOM 0x0002
  97. #define AT91_EMAC_IxR_RBNA 0x0004
  98. #define AT91_EMAC_IxR_TOVR 0x0008
  99. #define AT91_EMAC_IxR_TUND 0x0010
  100. #define AT91_EMAC_IxR_RTRY 0x0020
  101. #define AT91_EMAC_IxR_TBRE 0x0040
  102. #define AT91_EMAC_IxR_TCOM 0x0080
  103. #define AT91_EMAC_IxR_TIDLE 0x0100
  104. #define AT91_EMAC_IxR_LINK 0x0200
  105. #define AT91_EMAC_IxR_ROVR 0x0400
  106. #define AT91_EMAC_IxR_HRESP 0x0800
  107. #define AT91_EMAC_MAN_DATA_MASK 0xFFFF
  108. #define AT91_EMAC_MAN_CODE_802_3 0x00020000
  109. #define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18)
  110. #define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23)
  111. #define AT91_EMAC_MAN_RW_R 0x20000000
  112. #define AT91_EMAC_MAN_RW_W 0x10000000
  113. #define AT91_EMAC_MAN_HIGH 0x40000000
  114. #define AT91_EMAC_MAN_LOW 0x80000000
  115. #endif