omap36xx.dtsi 4.1 KB

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  1. /*
  2. * Device Tree Source for OMAP3 SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. #include <dt-bindings/media/omap3-isp.h>
  11. #include "omap3.dtsi"
  12. / {
  13. aliases {
  14. serial3 = &uart4;
  15. };
  16. cpus {
  17. /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
  18. cpu@0 {
  19. operating-points = <
  20. /* kHz uV */
  21. 300000 1012500
  22. 600000 1200000
  23. 800000 1325000
  24. >;
  25. clock-latency = <300000>; /* From legacy driver */
  26. };
  27. };
  28. ocp@68000000 {
  29. uart4: serial@49042000 {
  30. compatible = "ti,omap3-uart";
  31. reg = <0x49042000 0x400>;
  32. interrupts = <80>;
  33. dmas = <&sdma 81 &sdma 82>;
  34. dma-names = "tx", "rx";
  35. ti,hwmods = "uart4";
  36. clock-frequency = <48000000>;
  37. };
  38. abb_mpu_iva: regulator-abb-mpu {
  39. compatible = "ti,abb-v1";
  40. regulator-name = "abb_mpu_iva";
  41. #address-cells = <0>;
  42. #size-cells = <0>;
  43. reg = <0x483072f0 0x8>, <0x48306818 0x4>;
  44. reg-names = "base-address", "int-address";
  45. ti,tranxdone-status-mask = <0x4000000>;
  46. clocks = <&sys_ck>;
  47. ti,settling-time = <30>;
  48. ti,clock-cycles = <8>;
  49. ti,abb_info = <
  50. /*uV ABB efuse rbb_m fbb_m vset_m*/
  51. 1012500 0 0 0 0 0
  52. 1200000 0 0 0 0 0
  53. 1325000 0 0 0 0 0
  54. 1375000 1 0 0 0 0
  55. >;
  56. };
  57. omap3_pmx_core2: pinmux@480025a0 {
  58. compatible = "ti,omap3-padconf", "pinctrl-single";
  59. reg = <0x480025a0 0x5c>;
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. #interrupt-cells = <1>;
  63. interrupt-controller;
  64. pinctrl-single,register-width = <16>;
  65. pinctrl-single,function-mask = <0xff1f>;
  66. };
  67. isp: isp@480bc000 {
  68. compatible = "ti,omap3-isp";
  69. reg = <0x480bc000 0x12fc
  70. 0x480bd800 0x0600>;
  71. interrupts = <24>;
  72. iommus = <&mmu_isp>;
  73. syscon = <&scm_conf 0x2f0>;
  74. ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
  75. #clock-cells = <1>;
  76. ports {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. };
  80. };
  81. bandgap@48002524 {
  82. reg = <0x48002524 0x4>;
  83. compatible = "ti,omap36xx-bandgap";
  84. #thermal-sensor-cells = <0>;
  85. };
  86. };
  87. };
  88. /* OMAP3630 needs dss_96m_fck for VENC */
  89. &venc {
  90. clocks = <&dss_tv_fck>, <&dss_96m_fck>;
  91. clock-names = "fck", "tv_dac_clk";
  92. };
  93. &ssi {
  94. status = "ok";
  95. clocks = <&ssi_ssr_fck>,
  96. <&ssi_sst_fck>,
  97. <&ssi_ick>;
  98. clock-names = "ssi_ssr_fck",
  99. "ssi_sst_fck",
  100. "ssi_ick";
  101. };
  102. /include/ "omap34xx-omap36xx-clocks.dtsi"
  103. /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
  104. /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
  105. /include/ "omap36xx-clocks.dtsi"