omap36xx-am35xx-omap3430es2plus-clocks.dtsi 7.6 KB

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  1. /*
  2. * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. &prm_clocks {
  11. corex2_d3_fck: corex2_d3_fck {
  12. #clock-cells = <0>;
  13. compatible = "fixed-factor-clock";
  14. clocks = <&corex2_fck>;
  15. clock-mult = <1>;
  16. clock-div = <3>;
  17. };
  18. corex2_d5_fck: corex2_d5_fck {
  19. #clock-cells = <0>;
  20. compatible = "fixed-factor-clock";
  21. clocks = <&corex2_fck>;
  22. clock-mult = <1>;
  23. clock-div = <5>;
  24. };
  25. };
  26. &cm_clocks {
  27. dpll5_ck: dpll5_ck@d04 {
  28. #clock-cells = <0>;
  29. compatible = "ti,omap3-dpll-clock";
  30. clocks = <&sys_ck>, <&sys_ck>;
  31. reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
  32. ti,low-power-stop;
  33. ti,lock;
  34. };
  35. dpll5_m2_ck: dpll5_m2_ck@d50 {
  36. #clock-cells = <0>;
  37. compatible = "ti,divider-clock";
  38. clocks = <&dpll5_ck>;
  39. ti,max-div = <31>;
  40. reg = <0x0d50>;
  41. ti,index-starts-at-one;
  42. };
  43. sgx_gate_fck: sgx_gate_fck@b00 {
  44. #clock-cells = <0>;
  45. compatible = "ti,composite-gate-clock";
  46. clocks = <&core_ck>;
  47. ti,bit-shift = <1>;
  48. reg = <0x0b00>;
  49. };
  50. core_d3_ck: core_d3_ck {
  51. #clock-cells = <0>;
  52. compatible = "fixed-factor-clock";
  53. clocks = <&core_ck>;
  54. clock-mult = <1>;
  55. clock-div = <3>;
  56. };
  57. core_d4_ck: core_d4_ck {
  58. #clock-cells = <0>;
  59. compatible = "fixed-factor-clock";
  60. clocks = <&core_ck>;
  61. clock-mult = <1>;
  62. clock-div = <4>;
  63. };
  64. core_d6_ck: core_d6_ck {
  65. #clock-cells = <0>;
  66. compatible = "fixed-factor-clock";
  67. clocks = <&core_ck>;
  68. clock-mult = <1>;
  69. clock-div = <6>;
  70. };
  71. omap_192m_alwon_fck: omap_192m_alwon_fck {
  72. #clock-cells = <0>;
  73. compatible = "fixed-factor-clock";
  74. clocks = <&dpll4_m2x2_ck>;
  75. clock-mult = <1>;
  76. clock-div = <1>;
  77. };
  78. core_d2_ck: core_d2_ck {
  79. #clock-cells = <0>;
  80. compatible = "fixed-factor-clock";
  81. clocks = <&core_ck>;
  82. clock-mult = <1>;
  83. clock-div = <2>;
  84. };
  85. sgx_mux_fck: sgx_mux_fck@b40 {
  86. #clock-cells = <0>;
  87. compatible = "ti,composite-mux-clock";
  88. clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
  89. reg = <0x0b40>;
  90. };
  91. sgx_fck: sgx_fck {
  92. #clock-cells = <0>;
  93. compatible = "ti,composite-clock";
  94. clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
  95. };
  96. sgx_ick: sgx_ick@b10 {
  97. #clock-cells = <0>;
  98. compatible = "ti,wait-gate-clock";
  99. clocks = <&l3_ick>;
  100. reg = <0x0b10>;
  101. ti,bit-shift = <0>;
  102. };
  103. cpefuse_fck: cpefuse_fck@a08 {
  104. #clock-cells = <0>;
  105. compatible = "ti,gate-clock";
  106. clocks = <&sys_ck>;
  107. reg = <0x0a08>;
  108. ti,bit-shift = <0>;
  109. };
  110. ts_fck: ts_fck@a08 {
  111. #clock-cells = <0>;
  112. compatible = "ti,gate-clock";
  113. clocks = <&omap_32k_fck>;
  114. reg = <0x0a08>;
  115. ti,bit-shift = <1>;
  116. };
  117. usbtll_fck: usbtll_fck@a08 {
  118. #clock-cells = <0>;
  119. compatible = "ti,wait-gate-clock";
  120. clocks = <&dpll5_m2_ck>;
  121. reg = <0x0a08>;
  122. ti,bit-shift = <2>;
  123. };
  124. usbtll_ick: usbtll_ick@a18 {
  125. #clock-cells = <0>;
  126. compatible = "ti,omap3-interface-clock";
  127. clocks = <&core_l4_ick>;
  128. reg = <0x0a18>;
  129. ti,bit-shift = <2>;
  130. };
  131. mmchs3_ick: mmchs3_ick@a10 {
  132. #clock-cells = <0>;
  133. compatible = "ti,omap3-interface-clock";
  134. clocks = <&core_l4_ick>;
  135. reg = <0x0a10>;
  136. ti,bit-shift = <30>;
  137. };
  138. mmchs3_fck: mmchs3_fck@a00 {
  139. #clock-cells = <0>;
  140. compatible = "ti,wait-gate-clock";
  141. clocks = <&core_96m_fck>;
  142. reg = <0x0a00>;
  143. ti,bit-shift = <30>;
  144. };
  145. dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
  146. #clock-cells = <0>;
  147. compatible = "ti,dss-gate-clock";
  148. clocks = <&dpll4_m4x2_ck>;
  149. ti,bit-shift = <0>;
  150. reg = <0x0e00>;
  151. ti,set-rate-parent;
  152. };
  153. dss_ick: dss_ick_3430es2@e10 {
  154. #clock-cells = <0>;
  155. compatible = "ti,omap3-dss-interface-clock";
  156. clocks = <&l4_ick>;
  157. reg = <0x0e10>;
  158. ti,bit-shift = <0>;
  159. };
  160. usbhost_120m_fck: usbhost_120m_fck@1400 {
  161. #clock-cells = <0>;
  162. compatible = "ti,gate-clock";
  163. clocks = <&dpll5_m2_ck>;
  164. reg = <0x1400>;
  165. ti,bit-shift = <1>;
  166. };
  167. usbhost_48m_fck: usbhost_48m_fck@1400 {
  168. #clock-cells = <0>;
  169. compatible = "ti,dss-gate-clock";
  170. clocks = <&omap_48m_fck>;
  171. reg = <0x1400>;
  172. ti,bit-shift = <0>;
  173. };
  174. usbhost_ick: usbhost_ick@1410 {
  175. #clock-cells = <0>;
  176. compatible = "ti,omap3-dss-interface-clock";
  177. clocks = <&l4_ick>;
  178. reg = <0x1410>;
  179. ti,bit-shift = <0>;
  180. };
  181. };
  182. &cm_clockdomains {
  183. dpll5_clkdm: dpll5_clkdm {
  184. compatible = "ti,clockdomain";
  185. clocks = <&dpll5_ck>;
  186. };
  187. sgx_clkdm: sgx_clkdm {
  188. compatible = "ti,clockdomain";
  189. clocks = <&sgx_ick>;
  190. };
  191. dss_clkdm: dss_clkdm {
  192. compatible = "ti,clockdomain";
  193. clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
  194. <&dss1_alwon_fck>, <&dss_ick>;
  195. };
  196. core_l4_clkdm: core_l4_clkdm {
  197. compatible = "ti,clockdomain";
  198. clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
  199. <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
  200. <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
  201. <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
  202. <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
  203. <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
  204. <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
  205. <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
  206. <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
  207. <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
  208. <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
  209. };
  210. usbhost_clkdm: usbhost_clkdm {
  211. compatible = "ti,clockdomain";
  212. clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
  213. <&usbhost_ick>;
  214. };
  215. };