omap34xx-omap36xx-clocks.dtsi 8.3 KB

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  1. /*
  2. * Device Tree Source for OMAP34XX/OMAP36XX clock data
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. &cm_clocks {
  11. security_l4_ick2: security_l4_ick2 {
  12. #clock-cells = <0>;
  13. compatible = "fixed-factor-clock";
  14. clocks = <&l4_ick>;
  15. clock-mult = <1>;
  16. clock-div = <1>;
  17. };
  18. aes1_ick: aes1_ick@a14 {
  19. #clock-cells = <0>;
  20. compatible = "ti,omap3-interface-clock";
  21. clocks = <&security_l4_ick2>;
  22. ti,bit-shift = <3>;
  23. reg = <0x0a14>;
  24. };
  25. rng_ick: rng_ick@a14 {
  26. #clock-cells = <0>;
  27. compatible = "ti,omap3-interface-clock";
  28. clocks = <&security_l4_ick2>;
  29. reg = <0x0a14>;
  30. ti,bit-shift = <2>;
  31. };
  32. sha11_ick: sha11_ick@a14 {
  33. #clock-cells = <0>;
  34. compatible = "ti,omap3-interface-clock";
  35. clocks = <&security_l4_ick2>;
  36. reg = <0x0a14>;
  37. ti,bit-shift = <1>;
  38. };
  39. des1_ick: des1_ick@a14 {
  40. #clock-cells = <0>;
  41. compatible = "ti,omap3-interface-clock";
  42. clocks = <&security_l4_ick2>;
  43. reg = <0x0a14>;
  44. ti,bit-shift = <0>;
  45. };
  46. cam_mclk: cam_mclk@f00 {
  47. #clock-cells = <0>;
  48. compatible = "ti,gate-clock";
  49. clocks = <&dpll4_m5x2_ck>;
  50. ti,bit-shift = <0>;
  51. reg = <0x0f00>;
  52. ti,set-rate-parent;
  53. };
  54. cam_ick: cam_ick@f10 {
  55. #clock-cells = <0>;
  56. compatible = "ti,omap3-no-wait-interface-clock";
  57. clocks = <&l4_ick>;
  58. reg = <0x0f10>;
  59. ti,bit-shift = <0>;
  60. };
  61. csi2_96m_fck: csi2_96m_fck@f00 {
  62. #clock-cells = <0>;
  63. compatible = "ti,gate-clock";
  64. clocks = <&core_96m_fck>;
  65. reg = <0x0f00>;
  66. ti,bit-shift = <1>;
  67. };
  68. security_l3_ick: security_l3_ick {
  69. #clock-cells = <0>;
  70. compatible = "fixed-factor-clock";
  71. clocks = <&l3_ick>;
  72. clock-mult = <1>;
  73. clock-div = <1>;
  74. };
  75. pka_ick: pka_ick@a14 {
  76. #clock-cells = <0>;
  77. compatible = "ti,omap3-interface-clock";
  78. clocks = <&security_l3_ick>;
  79. reg = <0x0a14>;
  80. ti,bit-shift = <4>;
  81. };
  82. icr_ick: icr_ick@a10 {
  83. #clock-cells = <0>;
  84. compatible = "ti,omap3-interface-clock";
  85. clocks = <&core_l4_ick>;
  86. reg = <0x0a10>;
  87. ti,bit-shift = <29>;
  88. };
  89. des2_ick: des2_ick@a10 {
  90. #clock-cells = <0>;
  91. compatible = "ti,omap3-interface-clock";
  92. clocks = <&core_l4_ick>;
  93. reg = <0x0a10>;
  94. ti,bit-shift = <26>;
  95. };
  96. mspro_ick: mspro_ick@a10 {
  97. #clock-cells = <0>;
  98. compatible = "ti,omap3-interface-clock";
  99. clocks = <&core_l4_ick>;
  100. reg = <0x0a10>;
  101. ti,bit-shift = <23>;
  102. };
  103. mailboxes_ick: mailboxes_ick@a10 {
  104. #clock-cells = <0>;
  105. compatible = "ti,omap3-interface-clock";
  106. clocks = <&core_l4_ick>;
  107. reg = <0x0a10>;
  108. ti,bit-shift = <7>;
  109. };
  110. ssi_l4_ick: ssi_l4_ick {
  111. #clock-cells = <0>;
  112. compatible = "fixed-factor-clock";
  113. clocks = <&l4_ick>;
  114. clock-mult = <1>;
  115. clock-div = <1>;
  116. };
  117. sr1_fck: sr1_fck@c00 {
  118. #clock-cells = <0>;
  119. compatible = "ti,wait-gate-clock";
  120. clocks = <&sys_ck>;
  121. reg = <0x0c00>;
  122. ti,bit-shift = <6>;
  123. };
  124. sr2_fck: sr2_fck@c00 {
  125. #clock-cells = <0>;
  126. compatible = "ti,wait-gate-clock";
  127. clocks = <&sys_ck>;
  128. reg = <0x0c00>;
  129. ti,bit-shift = <7>;
  130. };
  131. sr_l4_ick: sr_l4_ick {
  132. #clock-cells = <0>;
  133. compatible = "fixed-factor-clock";
  134. clocks = <&l4_ick>;
  135. clock-mult = <1>;
  136. clock-div = <1>;
  137. };
  138. dpll2_fck: dpll2_fck@40 {
  139. #clock-cells = <0>;
  140. compatible = "ti,divider-clock";
  141. clocks = <&core_ck>;
  142. ti,bit-shift = <19>;
  143. ti,max-div = <7>;
  144. reg = <0x0040>;
  145. ti,index-starts-at-one;
  146. };
  147. dpll2_ck: dpll2_ck@4 {
  148. #clock-cells = <0>;
  149. compatible = "ti,omap3-dpll-clock";
  150. clocks = <&sys_ck>, <&dpll2_fck>;
  151. reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
  152. ti,low-power-stop;
  153. ti,lock;
  154. ti,low-power-bypass;
  155. };
  156. dpll2_m2_ck: dpll2_m2_ck@44 {
  157. #clock-cells = <0>;
  158. compatible = "ti,divider-clock";
  159. clocks = <&dpll2_ck>;
  160. ti,max-div = <31>;
  161. reg = <0x0044>;
  162. ti,index-starts-at-one;
  163. };
  164. iva2_ck: iva2_ck@0 {
  165. #clock-cells = <0>;
  166. compatible = "ti,wait-gate-clock";
  167. clocks = <&dpll2_m2_ck>;
  168. reg = <0x0000>;
  169. ti,bit-shift = <0>;
  170. };
  171. modem_fck: modem_fck@a00 {
  172. #clock-cells = <0>;
  173. compatible = "ti,omap3-interface-clock";
  174. clocks = <&sys_ck>;
  175. reg = <0x0a00>;
  176. ti,bit-shift = <31>;
  177. };
  178. sad2d_ick: sad2d_ick@a10 {
  179. #clock-cells = <0>;
  180. compatible = "ti,omap3-interface-clock";
  181. clocks = <&l3_ick>;
  182. reg = <0x0a10>;
  183. ti,bit-shift = <3>;
  184. };
  185. mad2d_ick: mad2d_ick@a18 {
  186. #clock-cells = <0>;
  187. compatible = "ti,omap3-interface-clock";
  188. clocks = <&l3_ick>;
  189. reg = <0x0a18>;
  190. ti,bit-shift = <3>;
  191. };
  192. mspro_fck: mspro_fck@a00 {
  193. #clock-cells = <0>;
  194. compatible = "ti,wait-gate-clock";
  195. clocks = <&core_96m_fck>;
  196. reg = <0x0a00>;
  197. ti,bit-shift = <23>;
  198. };
  199. };
  200. &cm_clockdomains {
  201. cam_clkdm: cam_clkdm {
  202. compatible = "ti,clockdomain";
  203. clocks = <&cam_ick>, <&csi2_96m_fck>;
  204. };
  205. iva2_clkdm: iva2_clkdm {
  206. compatible = "ti,clockdomain";
  207. clocks = <&iva2_ck>;
  208. };
  209. dpll2_clkdm: dpll2_clkdm {
  210. compatible = "ti,clockdomain";
  211. clocks = <&dpll2_ck>;
  212. };
  213. wkup_clkdm: wkup_clkdm {
  214. compatible = "ti,clockdomain";
  215. clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
  216. <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
  217. <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
  218. };
  219. d2d_clkdm: d2d_clkdm {
  220. compatible = "ti,clockdomain";
  221. clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
  222. };
  223. core_l4_clkdm: core_l4_clkdm {
  224. compatible = "ti,clockdomain";
  225. clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
  226. <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
  227. <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
  228. <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
  229. <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
  230. <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
  231. <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
  232. <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
  233. <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
  234. <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
  235. <&mspro_fck>;
  236. };
  237. };