ulcb.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/renesas/ulcb/ulcb.c
  4. * This file is ULCB board support.
  5. *
  6. * Copyright (C) 2017 Renesas Electronics Corporation
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <netdev.h>
  11. #include <dm.h>
  12. #include <dm/platform_data/serial_sh.h>
  13. #include <asm/processor.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/io.h>
  16. #include <linux/errno.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/rmobile.h>
  21. #include <asm/arch/rcar-mstp.h>
  22. #include <asm/arch/sh_sdhi.h>
  23. #include <i2c.h>
  24. #include <mmc.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. void s_init(void)
  27. {
  28. }
  29. #define DVFS_MSTP926 BIT(26)
  30. #define HSUSB_MSTP704 BIT(4) /* HSUSB */
  31. int board_early_init_f(void)
  32. {
  33. #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
  34. /* DVFS for reset */
  35. mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
  36. #endif
  37. return 0;
  38. }
  39. /* HSUSB block registers */
  40. #define HSUSB_REG_LPSTS 0xE6590102
  41. #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
  42. #define HSUSB_REG_UGCTRL2 0xE6590184
  43. #define HSUSB_REG_UGCTRL2_USB0SEL 0x30
  44. #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
  45. int board_init(void)
  46. {
  47. /* adress of boot parameters */
  48. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  49. /* USB1 pull-up */
  50. setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
  51. /* Configure the HSUSB block */
  52. mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
  53. /* Choice USB0SEL */
  54. clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
  55. HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
  56. /* low power status */
  57. setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
  58. return 0;
  59. }
  60. int dram_init(void)
  61. {
  62. if (fdtdec_setup_mem_size_base() != 0)
  63. return -EINVAL;
  64. return 0;
  65. }
  66. int dram_init_banksize(void)
  67. {
  68. fdtdec_setup_memory_banksize();
  69. return 0;
  70. }
  71. #ifdef CONFIG_MULTI_DTB_FIT
  72. int board_fit_config_name_match(const char *name)
  73. {
  74. /* PRR driver is not available yet */
  75. u32 cpu_type = rmobile_get_cpu_type();
  76. if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
  77. !strcmp(name, "r8a7795-h3ulcb-u-boot"))
  78. return 0;
  79. if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
  80. !strcmp(name, "r8a7796-m3ulcb-u-boot"))
  81. return 0;
  82. if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
  83. !strcmp(name, "r8a77965-m3nulcb-u-boot"))
  84. return 0;
  85. return -1;
  86. }
  87. #endif