README.mpc832xemds 3.7 KB

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  1. Freescale MPC832XEMDS Board
  2. -----------------------------------------
  3. 1. Board Switches and Jumpers
  4. 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
  5. For some reason, the HW designers describe the switch settings
  6. in terms of 0 and 1, and then map that to physical switches where
  7. the label "On" refers to logic 0 and "Off" is logic 1.
  8. Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
  9. bits may contribute to signals that are numbered based at 0,
  10. and some of those signals may be high-bit-number-0 too. Heed
  11. well the names and labels and do not get confused.
  12. "Off" == 1
  13. "On" == 0
  14. SW3 is switch 18 as silk-screened onto the board.
  15. SW4[8] is the bit labeled 8 on Switch 4.
  16. SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
  17. SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
  18. SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
  19. and bits labeled 8 is set as "Off".
  20. 1.1 For the MPC832XEMDS PROTO Board
  21. First, make sure the board default setting is consistent with the document
  22. shipped with your board. Then apply the following setting:
  23. SW3[1-8]= 0000_1000 (core PLL setting, core enable)
  24. SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
  25. SW5[1-8]= 0010_0110 (Boot from high end)
  26. SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
  27. SW7[1-8]= 1000_0011 (QE PLL setting)
  28. ENET3/4 MII mode settings:
  29. J1 1-2 (ETH3_TXER)
  30. J2 2-3 (MII mode)
  31. J3 2-3 (MII mode)
  32. J4 2-3 (ADSL clockOscillator)
  33. J5 1-2 (ETH4_TXER)
  34. J6 2-3 (ClockOscillator)
  35. JP1 removed (don't force PORESET)
  36. JP2 mounted (ETH4/2 MII)
  37. JP3 mounted (ETH3 MII)
  38. JP4 mounted (HRCW from BCSR)
  39. ENET3/4 RMII mode settings:
  40. J1 1-2 (ETH3_TXER)
  41. J2 1-2 (RMII mode)
  42. J3 1-2 (RMII mode)
  43. J4 2-3 (ADSL clockOscillator)
  44. J5 1-2 (ETH4_TXER)
  45. J6 2-3 (ClockOscillator)
  46. JP1 removed (don't force PORESET)
  47. JP2 removed (ETH4/2 RMII)
  48. JP3 removed (ETH3 RMII)
  49. JP4 removed (HRCW from FLASH)
  50. on board Oscillator: 66M
  51. 2. Memory Map
  52. 2.1 The memory map should look pretty much like this:
  53. 0x0000_0000 0x7fff_ffff DDR 2G
  54. 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
  55. 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
  56. 0xc000_0000 0xdfff_ffff Empty 512M
  57. 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
  58. 0xe020_0000 0xe02f_ffff Empty 1M
  59. 0xe030_0000 0xe03f_ffff PCI IO 1M
  60. 0xe040_0000 0xefff_ffff Empty 252M
  61. 0xf400_0000 0xf7ff_ffff Empty 64M
  62. 0xf800_0000 0xf800_7fff BCSR on CS1 32K
  63. 0xf800_8000 0xf800_ffff PIB CS2 32K
  64. 0xf801_0000 0xf801_7fff PIB CS3 32K
  65. 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
  66. 3. Definitions
  67. 3.1 Explanation of NEW definitions in:
  68. include/configs/MPC832XEPB.h
  69. CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
  70. CONFIG_MPC832x MPC832x specific
  71. CONFIG_MPC832XEMDS MPC832XEMDS board specific
  72. 4. Compilation
  73. Assuming you're using BASH shell:
  74. export CROSS_COMPILE=your-cross-compile-prefix
  75. cd u-boot
  76. make distclean
  77. make MPC832XEMDS_config
  78. make
  79. MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
  80. 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
  81. 2)To Make U-Boot image support PCI 33MHz, use
  82. Make MPC832XEMDS_HOST_33_config
  83. 3)To Make U-Boot image support PCI 66MHz, use
  84. Make MPC832XEMDS_HOST_66M_config
  85. 5. Downloading and Flashing Images
  86. 5.0 Download over network:
  87. tftp 10000 u-boot.bin
  88. 5.1 Reflash U-boot Image using U-boot
  89. tftp 20000 u-boot.bin
  90. protect off fe000000 fe0fffff
  91. erase fe000000 fe0fffff
  92. cp.b 20000 fe000000 xxxx
  93. You have to supply the correct byte count with 'xxxx' from the TFTP result log.
  94. Maybe 3ffff will work too, that corresponds to the erased sectors.
  95. 6. Notes
  96. 1) The console baudrate for MPC832XEMDS is 115200bps.