T1040QDS.h 22 KB

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  1. /*
  2. * Copyright 2013-2014 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. /*
  25. * T1040 QDS board configuration file
  26. */
  27. #ifdef CONFIG_RAMBOOT_PBL
  28. #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  29. #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  30. #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
  31. #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
  32. #endif
  33. /* High Level Configuration Options */
  34. #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  35. /* support deep sleep */
  36. #define CONFIG_DEEP_SLEEP
  37. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  38. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  39. #endif
  40. #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  41. #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
  42. #define CONFIG_PCI_INDIRECT_BRIDGE
  43. #define CONFIG_PCIE1 /* PCIE controller 1 */
  44. #define CONFIG_PCIE2 /* PCIE controller 2 */
  45. #define CONFIG_PCIE3 /* PCIE controller 3 */
  46. #define CONFIG_PCIE4 /* PCIE controller 4 */
  47. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  48. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  49. #define CONFIG_ENV_OVERWRITE
  50. #ifdef CONFIG_MTD_NOR_FLASH
  51. #if defined(CONFIG_SPIFLASH)
  52. #elif defined(CONFIG_SDCARD)
  53. #define CONFIG_SYS_MMC_ENV_DEV 0
  54. #endif
  55. #endif
  56. #ifndef __ASSEMBLY__
  57. unsigned long get_board_sys_clk(void);
  58. unsigned long get_board_ddr_clk(void);
  59. #endif
  60. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  61. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  62. /*
  63. * These can be toggled for performance analysis, otherwise use default.
  64. */
  65. #define CONFIG_SYS_CACHE_STASHING
  66. #define CONFIG_BACKSIDE_L2_CACHE
  67. #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  68. #define CONFIG_BTB /* toggle branch predition */
  69. #define CONFIG_DDR_ECC
  70. #ifdef CONFIG_DDR_ECC
  71. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  72. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  73. #endif
  74. #define CONFIG_ENABLE_36BIT_PHYS
  75. #define CONFIG_ADDR_MAP
  76. #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  77. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  78. #define CONFIG_SYS_MEMTEST_END 0x00400000
  79. /*
  80. * Config the L3 Cache as L3 SRAM
  81. */
  82. #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  83. #define CONFIG_SYS_DCSRBAR 0xf0000000
  84. #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  85. /* EEPROM */
  86. #define CONFIG_ID_EEPROM
  87. #define CONFIG_SYS_I2C_EEPROM_NXID
  88. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  89. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  90. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  91. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  92. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  93. /*
  94. * DDR Setup
  95. */
  96. #define CONFIG_VERY_BIG_RAM
  97. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  98. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  99. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  100. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  101. #define CONFIG_DDR_SPD
  102. #define CONFIG_SYS_SPD_BUS_NUM 0
  103. #define SPD_EEPROM_ADDRESS 0x51
  104. #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  105. /*
  106. * IFC Definitions
  107. */
  108. #define CONFIG_SYS_FLASH_BASE 0xe0000000
  109. #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  110. #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  111. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  112. + 0x8000000) | \
  113. CSPR_PORT_SIZE_16 | \
  114. CSPR_MSEL_NOR | \
  115. CSPR_V)
  116. #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  117. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  118. CSPR_PORT_SIZE_16 | \
  119. CSPR_MSEL_NOR | \
  120. CSPR_V)
  121. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  122. /*
  123. * TDM Definition
  124. */
  125. #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
  126. /* NOR Flash Timing Params */
  127. #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  128. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  129. FTIM0_NOR_TEADC(0x5) | \
  130. FTIM0_NOR_TEAHC(0x5))
  131. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  132. FTIM1_NOR_TRAD_NOR(0x1A) |\
  133. FTIM1_NOR_TSEQRAD_NOR(0x13))
  134. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  135. FTIM2_NOR_TCH(0x4) | \
  136. FTIM2_NOR_TWPH(0x0E) | \
  137. FTIM2_NOR_TWP(0x1c))
  138. #define CONFIG_SYS_NOR_FTIM3 0x0
  139. #define CONFIG_SYS_FLASH_QUIET_TEST
  140. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  141. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  142. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  143. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  144. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  145. #define CONFIG_SYS_FLASH_EMPTY_INFO
  146. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  147. + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  148. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  149. #define QIXIS_BASE 0xffdf0000
  150. #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
  151. #define QIXIS_LBMAP_SWITCH 0x06
  152. #define QIXIS_LBMAP_MASK 0x0f
  153. #define QIXIS_LBMAP_SHIFT 0
  154. #define QIXIS_LBMAP_DFLTBANK 0x00
  155. #define QIXIS_LBMAP_ALTBANK 0x04
  156. #define QIXIS_RST_CTL_RESET 0x31
  157. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  158. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  159. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  160. #define QIXIS_RST_FORCE_MEM 0x01
  161. #define CONFIG_SYS_CSPR3_EXT (0xf)
  162. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  163. | CSPR_PORT_SIZE_8 \
  164. | CSPR_MSEL_GPCM \
  165. | CSPR_V)
  166. #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
  167. #define CONFIG_SYS_CSOR3 0x0
  168. /* QIXIS Timing parameters for IFC CS3 */
  169. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  170. FTIM0_GPCM_TEADC(0x0e) | \
  171. FTIM0_GPCM_TEAHC(0x0e))
  172. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  173. FTIM1_GPCM_TRAD(0x3f))
  174. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  175. FTIM2_GPCM_TCH(0x8) | \
  176. FTIM2_GPCM_TWP(0x1f))
  177. #define CONFIG_SYS_CS3_FTIM3 0x0
  178. #define CONFIG_NAND_FSL_IFC
  179. #define CONFIG_SYS_NAND_BASE 0xff800000
  180. #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  181. #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  182. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  183. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  184. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  185. | CSPR_V)
  186. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  187. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  188. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  189. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  190. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  191. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  192. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  193. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  194. #define CONFIG_SYS_NAND_ONFI_DETECTION
  195. /* ONFI NAND Flash mode0 Timing Params */
  196. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  197. FTIM0_NAND_TWP(0x18) | \
  198. FTIM0_NAND_TWCHT(0x07) | \
  199. FTIM0_NAND_TWH(0x0a))
  200. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  201. FTIM1_NAND_TWBE(0x39) | \
  202. FTIM1_NAND_TRR(0x0e) | \
  203. FTIM1_NAND_TRP(0x18))
  204. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  205. FTIM2_NAND_TREH(0x0a) | \
  206. FTIM2_NAND_TWHRE(0x1e))
  207. #define CONFIG_SYS_NAND_FTIM3 0x0
  208. #define CONFIG_SYS_NAND_DDR_LAW 11
  209. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  210. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  211. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  212. #if defined(CONFIG_MTD_RAW_NAND)
  213. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  214. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  215. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  216. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  217. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  218. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  219. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  220. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  221. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  222. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  223. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  224. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  225. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  226. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  227. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  228. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  229. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  230. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  231. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  232. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  233. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  234. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  235. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  236. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  237. #else
  238. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  239. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  240. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  241. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  242. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  243. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  244. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  245. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  246. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  247. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  248. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  249. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  250. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  251. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  252. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  253. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  254. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  255. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  256. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  257. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  258. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  259. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  260. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  261. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  262. #endif
  263. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  264. #if defined(CONFIG_RAMBOOT_PBL)
  265. #define CONFIG_SYS_RAMBOOT
  266. #endif
  267. #define CONFIG_HWCONFIG
  268. /* define to use L1 as initial stack */
  269. #define CONFIG_L1_INIT_RAM
  270. #define CONFIG_SYS_INIT_RAM_LOCK
  271. #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  272. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  273. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
  274. /* The assembler doesn't like typecast */
  275. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  276. ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  277. CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  278. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  279. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  280. GENERATED_GBL_DATA_SIZE)
  281. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  282. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  283. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  284. /* Serial Port - controlled on board with jumper J8
  285. * open - index 2
  286. * shorted - index 1
  287. */
  288. #define CONFIG_SYS_NS16550_SERIAL
  289. #define CONFIG_SYS_NS16550_REG_SIZE 1
  290. #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  291. #define CONFIG_SYS_BAUDRATE_TABLE \
  292. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  293. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  294. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  295. #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  296. #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  297. /* Video */
  298. #define CONFIG_FSL_DIU_FB
  299. #ifdef CONFIG_FSL_DIU_FB
  300. #define CONFIG_FSL_DIU_CH7301
  301. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  302. #define CONFIG_VIDEO_LOGO
  303. #define CONFIG_VIDEO_BMP_LOGO
  304. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  305. /*
  306. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  307. * disable empty flash sector detection, which is I/O-intensive.
  308. */
  309. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  310. #endif
  311. /* I2C */
  312. #define CONFIG_SYS_I2C
  313. #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
  314. #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
  315. #define CONFIG_SYS_FSL_I2C2_SPEED 50000
  316. #define CONFIG_SYS_FSL_I2C3_SPEED 50000
  317. #define CONFIG_SYS_FSL_I2C4_SPEED 50000
  318. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  319. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  320. #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  321. #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  322. #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  323. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  324. #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  325. #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  326. #define I2C_MUX_PCA_ADDR 0x77
  327. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  328. /* I2C bus multiplexer */
  329. #define I2C_MUX_CH_DEFAULT 0x8
  330. #define I2C_MUX_CH_DIU 0xC
  331. /* LDI/DVI Encoder for display */
  332. #define CONFIG_SYS_I2C_LDI_ADDR 0x38
  333. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  334. /*
  335. * RTC configuration
  336. */
  337. #define RTC
  338. #define CONFIG_RTC_DS3231 1
  339. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  340. /*
  341. * eSPI - Enhanced SPI
  342. */
  343. /*
  344. * General PCI
  345. * Memory space is mapped 1-1, but I/O space must start from 0.
  346. */
  347. #ifdef CONFIG_PCI
  348. /* controller 1, direct to uli, tgtid 3, Base address 20000 */
  349. #ifdef CONFIG_PCIE1
  350. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  351. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  352. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  353. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
  354. #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  355. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  356. #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  357. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  358. #endif
  359. /* controller 2, Slot 2, tgtid 2, Base address 201000 */
  360. #ifdef CONFIG_PCIE2
  361. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
  362. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  363. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
  364. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  365. #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  366. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  367. #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  368. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  369. #endif
  370. /* controller 3, Slot 1, tgtid 1, Base address 202000 */
  371. #ifdef CONFIG_PCIE3
  372. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  373. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  374. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  375. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  376. #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  377. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  378. #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  379. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  380. #endif
  381. /* controller 4, Base address 203000 */
  382. #ifdef CONFIG_PCIE4
  383. #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
  384. #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  385. #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
  386. #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  387. #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
  388. #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  389. #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  390. #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  391. #endif
  392. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  393. #endif /* CONFIG_PCI */
  394. /* SATA */
  395. #define CONFIG_FSL_SATA_V2
  396. #ifdef CONFIG_FSL_SATA_V2
  397. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  398. #define CONFIG_SATA1
  399. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  400. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  401. #define CONFIG_SATA2
  402. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  403. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  404. #define CONFIG_LBA48
  405. #endif
  406. /*
  407. * USB
  408. */
  409. #define CONFIG_HAS_FSL_DR_USB
  410. #ifdef CONFIG_HAS_FSL_DR_USB
  411. #ifdef CONFIG_USB_EHCI_HCD
  412. #define CONFIG_USB_EHCI_FSL
  413. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  414. #endif
  415. #endif
  416. #ifdef CONFIG_MMC
  417. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  418. #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
  419. #endif
  420. /* Qman/Bman */
  421. #ifndef CONFIG_NOBQFMAN
  422. #define CONFIG_SYS_BMAN_NUM_PORTALS 10
  423. #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  424. #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  425. #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  426. #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  427. #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  428. #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  429. #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  430. #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  431. CONFIG_SYS_BMAN_CENA_SIZE)
  432. #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  433. #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  434. #define CONFIG_SYS_QMAN_NUM_PORTALS 10
  435. #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  436. #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  437. #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  438. #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  439. #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  440. #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  441. #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  442. #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  443. CONFIG_SYS_QMAN_CENA_SIZE)
  444. #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  445. #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  446. #define CONFIG_SYS_DPAA_FMAN
  447. #define CONFIG_SYS_DPAA_PME
  448. /* Default address of microcode for the Linux Fman driver */
  449. #if defined(CONFIG_SPIFLASH)
  450. /*
  451. * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  452. * env, so we got 0x110000.
  453. */
  454. #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  455. #elif defined(CONFIG_SDCARD)
  456. /*
  457. * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  458. * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  459. * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  460. */
  461. #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  462. #elif defined(CONFIG_MTD_RAW_NAND)
  463. #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  464. #else
  465. #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  466. #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
  467. #endif
  468. #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  469. #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  470. #endif /* CONFIG_NOBQFMAN */
  471. #ifdef CONFIG_SYS_DPAA_FMAN
  472. #define CONFIG_PHYLIB_10G
  473. #define CONFIG_PHY_VITESSE
  474. #define CONFIG_PHY_REALTEK
  475. #define CONFIG_PHY_TERANETICS
  476. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  477. #define SGMII_CARD_PORT2_PHY_ADDR 0x10
  478. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  479. #define SGMII_CARD_PORT4_PHY_ADDR 0x11
  480. #endif
  481. #ifdef CONFIG_FMAN_ENET
  482. #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
  483. #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
  484. #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
  485. #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
  486. #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
  487. #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
  488. #define CONFIG_ETHPRIME "FM1@DTSEC1"
  489. #endif
  490. /* Enable VSC9953 L2 Switch driver */
  491. #define CONFIG_VSC9953
  492. #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
  493. #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
  494. /*
  495. * Dynamic MTD Partition support with mtdparts
  496. */
  497. /*
  498. * Environment
  499. */
  500. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  501. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  502. /*
  503. * Miscellaneous configurable options
  504. */
  505. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  506. /*
  507. * For booting Linux, the board info and command line data
  508. * have to be in the first 64 MB of memory, since this is
  509. * the maximum mapped by the Linux kernel during initialization.
  510. */
  511. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  512. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  513. #ifdef CONFIG_CMD_KGDB
  514. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  515. #endif
  516. /*
  517. * Environment Configuration
  518. */
  519. #define CONFIG_ROOTPATH "/opt/nfsroot"
  520. #define CONFIG_BOOTFILE "uImage"
  521. #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  522. /* default location for tftp and bootm */
  523. #define CONFIG_LOADADDR 1000000
  524. #define __USB_PHY_TYPE utmi
  525. #define CONFIG_EXTRA_ENV_SETTINGS \
  526. "hwconfig=fsl_ddr:bank_intlv=auto;" \
  527. "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  528. "netdev=eth0\0" \
  529. "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
  530. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  531. "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  532. "tftpflash=tftpboot $loadaddr $uboot && " \
  533. "protect off $ubootaddr +$filesize && " \
  534. "erase $ubootaddr +$filesize && " \
  535. "cp.b $loadaddr $ubootaddr $filesize && " \
  536. "protect on $ubootaddr +$filesize && " \
  537. "cmp.b $loadaddr $ubootaddr $filesize\0" \
  538. "consoledev=ttyS0\0" \
  539. "ramdiskaddr=2000000\0" \
  540. "ramdiskfile=t1040qds/ramdisk.uboot\0" \
  541. "fdtaddr=1e00000\0" \
  542. "fdtfile=t1040qds/t1040qds.dtb\0" \
  543. "bdev=sda3\0"
  544. #define CONFIG_LINUX \
  545. "setenv bootargs root=/dev/ram rw " \
  546. "console=$consoledev,$baudrate $othbootargs;" \
  547. "setenv ramdiskaddr 0x02000000;" \
  548. "setenv fdtaddr 0x00c00000;" \
  549. "setenv loadaddr 0x1000000;" \
  550. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  551. #define CONFIG_HDBOOT \
  552. "setenv bootargs root=/dev/$bdev rw " \
  553. "console=$consoledev,$baudrate $othbootargs;" \
  554. "tftp $loadaddr $bootfile;" \
  555. "tftp $fdtaddr $fdtfile;" \
  556. "bootm $loadaddr - $fdtaddr"
  557. #define CONFIG_NFSBOOTCOMMAND \
  558. "setenv bootargs root=/dev/nfs rw " \
  559. "nfsroot=$serverip:$rootpath " \
  560. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  561. "console=$consoledev,$baudrate $othbootargs;" \
  562. "tftp $loadaddr $bootfile;" \
  563. "tftp $fdtaddr $fdtfile;" \
  564. "bootm $loadaddr - $fdtaddr"
  565. #define CONFIG_RAMBOOTCOMMAND \
  566. "setenv bootargs root=/dev/ram rw " \
  567. "console=$consoledev,$baudrate $othbootargs;" \
  568. "tftp $ramdiskaddr $ramdiskfile;" \
  569. "tftp $loadaddr $bootfile;" \
  570. "tftp $fdtaddr $fdtfile;" \
  571. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  572. #define CONFIG_BOOTCOMMAND CONFIG_LINUX
  573. #include <asm/fsl_secure_boot.h>
  574. #endif /* __CONFIG_H */