config_mpc85xx.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef _ASM_MPC85xx_CONFIG_H_
  6. #define _ASM_MPC85xx_CONFIG_H_
  7. /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
  8. /*
  9. * This macro should be removed when we no longer care about backwards
  10. * compatibility with older operating systems.
  11. */
  12. #define CONFIG_PPC_SPINTABLE_COMPATIBLE
  13. #include <fsl_ddrc_version.h>
  14. /* IP endianness */
  15. #define CONFIG_SYS_FSL_IFC_BE
  16. #define CONFIG_SYS_FSL_SFP_BE
  17. #define CONFIG_SYS_FSL_SEC_MON_BE
  18. #if defined(CONFIG_ARCH_MPC8548)
  19. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  20. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  21. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  22. #define CONFIG_SYS_FSL_RMU
  23. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  24. #elif defined(CONFIG_ARCH_MPC8568)
  25. #define QE_MURAM_SIZE 0x10000UL
  26. #define MAX_QE_RISC 2
  27. #define QE_NUM_OF_SNUM 28
  28. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  29. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  30. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  31. #define CONFIG_SYS_FSL_RMU
  32. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  33. #elif defined(CONFIG_ARCH_MPC8569)
  34. #define QE_MURAM_SIZE 0x20000UL
  35. #define MAX_QE_RISC 4
  36. #define QE_NUM_OF_SNUM 46
  37. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  38. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  39. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  40. #define CONFIG_SYS_FSL_RMU
  41. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  42. #elif defined(CONFIG_ARCH_P1010)
  43. #define CONFIG_FSL_SDHC_V2_3
  44. #define CONFIG_TSECV2
  45. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  46. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  47. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  48. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  49. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  50. #define CONFIG_ESDHC_HC_BLK_ADDR
  51. /* P1011 is single core version of P1020 */
  52. #elif defined(CONFIG_ARCH_P1011)
  53. #define CONFIG_TSECV2
  54. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  55. #elif defined(CONFIG_ARCH_P1020)
  56. #define CONFIG_TSECV2
  57. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  58. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  59. #endif
  60. #elif defined(CONFIG_ARCH_P1021)
  61. #define CONFIG_TSECV2
  62. #define QE_MURAM_SIZE 0x6000UL
  63. #define MAX_QE_RISC 1
  64. #define QE_NUM_OF_SNUM 28
  65. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  66. #elif defined(CONFIG_ARCH_P1022)
  67. #define CONFIG_TSECV2
  68. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  69. #elif defined(CONFIG_ARCH_P1023)
  70. #define CONFIG_SYS_NUM_FMAN 1
  71. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  72. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  73. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  74. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  75. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  76. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  77. /* P1024 is lower end variant of P1020 */
  78. #elif defined(CONFIG_ARCH_P1024)
  79. #define CONFIG_TSECV2
  80. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  81. /* P1025 is lower end variant of P1021 */
  82. #elif defined(CONFIG_ARCH_P1025)
  83. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  84. #define CONFIG_TSECV2
  85. #define QE_MURAM_SIZE 0x6000UL
  86. #define MAX_QE_RISC 1
  87. #define QE_NUM_OF_SNUM 28
  88. #elif defined(CONFIG_ARCH_P2020)
  89. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  90. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  91. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  92. #define CONFIG_SYS_FSL_RMU
  93. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  94. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  95. #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
  96. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  97. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  98. #define CONFIG_SYS_NUM_FMAN 1
  99. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  100. #define CONFIG_SYS_NUM_FM1_10GEC 1
  101. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  102. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  103. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  104. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  105. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  106. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  107. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  108. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  109. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  110. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  111. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  112. #elif defined(CONFIG_ARCH_P3041)
  113. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  114. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  115. #define CONFIG_SYS_NUM_FMAN 1
  116. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  117. #define CONFIG_SYS_NUM_FM1_10GEC 1
  118. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  119. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  120. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  121. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  122. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  123. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  124. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  125. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  126. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  127. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  128. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  129. #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
  130. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  131. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  132. #define CONFIG_SYS_NUM_FMAN 2
  133. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  134. #define CONFIG_SYS_NUM_FM2_DTSEC 4
  135. #define CONFIG_SYS_NUM_FM1_10GEC 1
  136. #define CONFIG_SYS_NUM_FM2_10GEC 1
  137. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  138. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  139. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  140. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  141. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  142. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  143. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  144. #define CONFIG_SYS_FSL_RMU
  145. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  146. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
  147. #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
  148. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  149. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  150. #define CONFIG_SYS_NUM_FMAN 1
  151. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  152. #define CONFIG_SYS_NUM_FM1_10GEC 1
  153. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  154. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  155. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  156. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  157. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  158. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  159. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  160. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  161. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  162. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  163. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
  164. #elif defined(CONFIG_ARCH_P5040)
  165. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  166. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  167. #define CONFIG_SYS_NUM_FMAN 2
  168. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  169. #define CONFIG_SYS_NUM_FM1_10GEC 1
  170. #define CONFIG_SYS_NUM_FM2_DTSEC 5
  171. #define CONFIG_SYS_NUM_FM2_10GEC 1
  172. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  173. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  174. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  175. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  176. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  177. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  178. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  179. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  180. #elif defined(CONFIG_ARCH_BSC9131)
  181. #define CONFIG_FSL_SDHC_V2_3
  182. #define CONFIG_TSECV2
  183. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  184. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  185. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  186. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  187. #define CONFIG_NAND_FSL_IFC
  188. #define CONFIG_ESDHC_HC_BLK_ADDR
  189. #elif defined(CONFIG_ARCH_BSC9132)
  190. #define CONFIG_FSL_SDHC_V2_3
  191. #define CONFIG_TSECV2
  192. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  193. #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
  194. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  195. #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
  196. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  197. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  198. #define CONFIG_NAND_FSL_IFC
  199. #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
  200. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  201. #define CONFIG_ESDHC_HC_BLK_ADDR
  202. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  203. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  204. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  205. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  206. #ifdef CONFIG_ARCH_T4240
  207. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
  208. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  209. #define CONFIG_SYS_NUM_FM1_10GEC 2
  210. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  211. #define CONFIG_SYS_NUM_FM2_10GEC 2
  212. #else
  213. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  214. #define CONFIG_SYS_NUM_FM1_10GEC 1
  215. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  216. #define CONFIG_SYS_NUM_FM2_10GEC 1
  217. #if defined(CONFIG_ARCH_T4160)
  218. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  219. #endif
  220. #endif
  221. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  222. #define CONFIG_SYS_FSL_SRDS_1
  223. #define CONFIG_SYS_FSL_SRDS_2
  224. #define CONFIG_SYS_FSL_SRDS_3
  225. #define CONFIG_SYS_FSL_SRDS_4
  226. #define CONFIG_SYS_NUM_FMAN 2
  227. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  228. #define CONFIG_SYS_PME_CLK 0
  229. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  230. #define CONFIG_SYS_FMAN_V3
  231. #define CONFIG_SYS_FM1_CLK 3
  232. #define CONFIG_SYS_FM2_CLK 3
  233. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  234. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  235. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  236. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  237. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  238. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  239. #define CONFIG_SYS_FSL_SRIO_LIODN
  240. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  241. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  242. #define CONFIG_SYS_FSL_SFP_VER_3_0
  243. #define CONFIG_SYS_FSL_PCI_VER_3_X
  244. #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
  245. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  246. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  247. #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
  248. #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
  249. #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
  250. #define CONFIG_SYS_FSL_SRDS_1
  251. #define CONFIG_SYS_FSL_SRDS_2
  252. #define CONFIG_SYS_MAPLE
  253. #define CONFIG_SYS_CPRI
  254. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  255. #define CONFIG_SYS_NUM_FMAN 1
  256. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  257. #define CONFIG_SYS_FM1_CLK 0
  258. #define CONFIG_SYS_CPRI_CLK 3
  259. #define CONFIG_SYS_ULB_CLK 4
  260. #define CONFIG_SYS_ETVPE_CLK 1
  261. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  262. #define CONFIG_SYS_FMAN_V3
  263. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  264. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  265. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  266. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  267. #define CONFIG_SYS_FSL_SFP_VER_3_0
  268. #ifdef CONFIG_ARCH_B4860
  269. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  270. #define CONFIG_MAX_DSP_CPUS 12
  271. #define CONFIG_NUM_DSP_CPUS 6
  272. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
  273. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  274. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  275. #define CONFIG_SYS_NUM_FM1_10GEC 2
  276. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  277. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  278. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  279. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  280. #define CONFIG_SYS_FSL_SRIO_LIODN
  281. #else
  282. #define CONFIG_MAX_DSP_CPUS 2
  283. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
  284. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
  285. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
  286. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  287. #define CONFIG_SYS_NUM_FM1_10GEC 0
  288. #endif
  289. #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
  290. #define CONFIG_E5500
  291. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  292. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  293. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  294. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  295. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  296. #define CONFIG_SYS_FSL_SRDS_1
  297. #define CONFIG_SYS_NUM_FMAN 1
  298. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  299. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  300. #define CONFIG_PME_PLAT_CLK_DIV 2
  301. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  302. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  303. #define CONFIG_SYS_FMAN_V3
  304. #define CONFIG_FM_PLAT_CLK_DIV 1
  305. #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
  306. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  307. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  308. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  309. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  310. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  311. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  312. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  313. #define QE_MURAM_SIZE 0x6000UL
  314. #define MAX_QE_RISC 1
  315. #define QE_NUM_OF_SNUM 28
  316. #define CONFIG_SYS_FSL_SFP_VER_3_0
  317. #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
  318. #define CONFIG_E5500
  319. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  320. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  321. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  322. #define CONFIG_SYS_FMAN_V3
  323. #define CONFIG_SYS_FSL_NUM_CC_PLL 2
  324. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  325. #define CONFIG_SYS_FSL_SRDS_1
  326. #define CONFIG_SYS_NUM_FMAN 1
  327. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  328. #define CONFIG_SYS_NUM_FM1_10GEC 1
  329. #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  330. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  331. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  332. #define CONFIG_SYS_FM1_CLK 0
  333. #define CONFIG_QBMAN_CLK_DIV 1
  334. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  335. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  336. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  337. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  338. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  339. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  340. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  341. #define QE_MURAM_SIZE 0x6000UL
  342. #define MAX_QE_RISC 1
  343. #define QE_NUM_OF_SNUM 28
  344. #define CONFIG_SYS_FSL_SFP_VER_3_0
  345. #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  346. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  347. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  348. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  349. #define CONFIG_SYS_FSL_QMAN_V3
  350. #define CONFIG_SYS_NUM_FMAN 1
  351. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  352. #define CONFIG_SYS_FSL_SRDS_1
  353. #define CONFIG_SYS_FSL_PCI_VER_3_X
  354. #if defined(CONFIG_ARCH_T2080)
  355. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  356. #define CONFIG_SYS_NUM_FM1_10GEC 4
  357. #define CONFIG_SYS_FSL_SRDS_2
  358. #define CONFIG_SYS_FSL_SRIO_LIODN
  359. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  360. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  361. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  362. #elif defined(CONFIG_ARCH_T2081)
  363. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  364. #define CONFIG_SYS_NUM_FM1_10GEC 2
  365. #endif
  366. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  367. #define CONFIG_PME_PLAT_CLK_DIV 1
  368. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  369. #define CONFIG_SYS_FM1_CLK 0
  370. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  371. #define CONFIG_SYS_FMAN_V3
  372. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  373. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  374. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  375. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  376. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  377. #define CONFIG_SYS_FSL_SFP_VER_3_0
  378. #define CONFIG_SYS_FSL_ISBC_VER 2
  379. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  380. #define CONFIG_SYS_FSL_SFP_VER_3_0
  381. #elif defined(CONFIG_ARCH_C29X)
  382. #define CONFIG_FSL_SDHC_V2_3
  383. #define CONFIG_TSECV2_1
  384. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  385. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
  386. #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
  387. #endif
  388. #if !defined(CONFIG_ARCH_C29X)
  389. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  390. #endif
  391. #endif /* _ASM_MPC85xx_CONFIG_H_ */