pci.h 21 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * aloong with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef _PCI_H
  27. #define _PCI_H
  28. /*
  29. * Under PCI, each device has 256 bytes of configuration address space,
  30. * of which the first 64 bytes are standardized as follows:
  31. */
  32. #define PCI_VENDOR_ID 0x00 /* 16 bits */
  33. #define PCI_DEVICE_ID 0x02 /* 16 bits */
  34. #define PCI_COMMAND 0x04 /* 16 bits */
  35. #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
  36. #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
  37. #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
  38. #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
  39. #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
  40. #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
  41. #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
  42. #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
  43. #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
  44. #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
  45. #define PCI_STATUS 0x06 /* 16 bits */
  46. #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
  47. #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
  48. #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
  49. #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
  50. #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
  51. #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
  52. #define PCI_STATUS_DEVSEL_FAST 0x000
  53. #define PCI_STATUS_DEVSEL_MEDIUM 0x200
  54. #define PCI_STATUS_DEVSEL_SLOW 0x400
  55. #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  56. #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  57. #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  58. #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  59. #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  60. #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
  61. revision */
  62. #define PCI_REVISION_ID 0x08 /* Revision ID */
  63. #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
  64. #define PCI_CLASS_DEVICE 0x0a /* Device class */
  65. #define PCI_CLASS_CODE 0x0b /* Device class code */
  66. #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
  67. #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
  68. #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
  69. #define PCI_HEADER_TYPE 0x0e /* 8 bits */
  70. #define PCI_HEADER_TYPE_NORMAL 0
  71. #define PCI_HEADER_TYPE_BRIDGE 1
  72. #define PCI_HEADER_TYPE_CARDBUS 2
  73. #define PCI_BIST 0x0f /* 8 bits */
  74. #define PCI_BIST_CODE_MASK 0x0f /* Return result */
  75. #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
  76. #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
  77. /*
  78. * Base addresses specify locations in memory or I/O space.
  79. * Decoded size can be determined by writing a value of
  80. * 0xffffffff to the register, and reading it back. Only
  81. * 1 bits are decoded.
  82. */
  83. #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
  84. #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
  85. #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
  86. #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
  87. #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
  88. #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
  89. #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
  90. #define PCI_BASE_ADDRESS_SPACE_IO 0x01
  91. #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  92. #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  93. #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
  94. #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
  95. #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
  96. #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
  97. #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
  98. #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
  99. /* bit 1 is reserved if address_space = 1 */
  100. /* Header type 0 (normal devices) */
  101. #define PCI_CARDBUS_CIS 0x28
  102. #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  103. #define PCI_SUBSYSTEM_ID 0x2e
  104. #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
  105. #define PCI_ROM_ADDRESS_ENABLE 0x01
  106. #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
  107. #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
  108. /* 0x35-0x3b are reserved */
  109. #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
  110. #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
  111. #define PCI_MIN_GNT 0x3e /* 8 bits */
  112. #define PCI_MAX_LAT 0x3f /* 8 bits */
  113. /* Header type 1 (PCI-to-PCI bridges) */
  114. #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
  115. #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
  116. #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
  117. #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
  118. #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
  119. #define PCI_IO_LIMIT 0x1d
  120. #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
  121. #define PCI_IO_RANGE_TYPE_16 0x00
  122. #define PCI_IO_RANGE_TYPE_32 0x01
  123. #define PCI_IO_RANGE_MASK ~0x0f
  124. #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
  125. #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
  126. #define PCI_MEMORY_LIMIT 0x22
  127. #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
  128. #define PCI_MEMORY_RANGE_MASK ~0x0f
  129. #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
  130. #define PCI_PREF_MEMORY_LIMIT 0x26
  131. #define PCI_PREF_RANGE_TYPE_MASK 0x0f
  132. #define PCI_PREF_RANGE_TYPE_32 0x00
  133. #define PCI_PREF_RANGE_TYPE_64 0x01
  134. #define PCI_PREF_RANGE_MASK ~0x0f
  135. #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
  136. #define PCI_PREF_LIMIT_UPPER32 0x2c
  137. #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
  138. #define PCI_IO_LIMIT_UPPER16 0x32
  139. /* 0x34 same as for htype 0 */
  140. /* 0x35-0x3b is reserved */
  141. #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
  142. /* 0x3c-0x3d are same as for htype 0 */
  143. #define PCI_BRIDGE_CONTROL 0x3e
  144. #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
  145. #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
  146. #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
  147. #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
  148. #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
  149. #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
  150. #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
  151. /* From 440ep */
  152. #define PCI_ERREN 0x48 /* Error Enable */
  153. #define PCI_ERRSTS 0x49 /* Error Status */
  154. #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
  155. #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
  156. #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
  157. #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
  158. #define PCI_CAPID 0x58 /* Capability Identifier */
  159. #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
  160. #define PCI_PMC 0x5A /* Power Management Capabilities */
  161. #define PCI_PMCSR 0x5C /* Power Management Control Status */
  162. #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
  163. #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
  164. #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
  165. /* Header type 2 (CardBus bridges) */
  166. #define PCI_CB_CAPABILITY_LIST 0x14
  167. /* 0x15 reserved */
  168. #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
  169. #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
  170. #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
  171. #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
  172. #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
  173. #define PCI_CB_MEMORY_BASE_0 0x1c
  174. #define PCI_CB_MEMORY_LIMIT_0 0x20
  175. #define PCI_CB_MEMORY_BASE_1 0x24
  176. #define PCI_CB_MEMORY_LIMIT_1 0x28
  177. #define PCI_CB_IO_BASE_0 0x2c
  178. #define PCI_CB_IO_BASE_0_HI 0x2e
  179. #define PCI_CB_IO_LIMIT_0 0x30
  180. #define PCI_CB_IO_LIMIT_0_HI 0x32
  181. #define PCI_CB_IO_BASE_1 0x34
  182. #define PCI_CB_IO_BASE_1_HI 0x36
  183. #define PCI_CB_IO_LIMIT_1 0x38
  184. #define PCI_CB_IO_LIMIT_1_HI 0x3a
  185. #define PCI_CB_IO_RANGE_MASK ~0x03
  186. /* 0x3c-0x3d are same as for htype 0 */
  187. #define PCI_CB_BRIDGE_CONTROL 0x3e
  188. #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
  189. #define PCI_CB_BRIDGE_CTL_SERR 0x02
  190. #define PCI_CB_BRIDGE_CTL_ISA 0x04
  191. #define PCI_CB_BRIDGE_CTL_VGA 0x08
  192. #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
  193. #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
  194. #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
  195. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
  196. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  197. #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
  198. #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
  199. #define PCI_CB_SUBSYSTEM_ID 0x42
  200. #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
  201. /* 0x48-0x7f reserved */
  202. /* Capability lists */
  203. #define PCI_CAP_LIST_ID 0 /* Capability ID */
  204. #define PCI_CAP_ID_PM 0x01 /* Power Management */
  205. #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
  206. #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
  207. #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
  208. #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
  209. #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
  210. #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
  211. #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
  212. #define PCI_CAP_SIZEOF 4
  213. /* Power Management Registers */
  214. #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
  215. #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
  216. #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
  217. #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
  218. #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
  219. #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
  220. #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
  221. #define PCI_PM_CTRL 4 /* PM control and status register */
  222. #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
  223. #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
  224. #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
  225. #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
  226. #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
  227. #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
  228. #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
  229. #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
  230. #define PCI_PM_DATA_REGISTER 7 /* (??) */
  231. #define PCI_PM_SIZEOF 8
  232. /* AGP registers */
  233. #define PCI_AGP_VERSION 2 /* BCD version number */
  234. #define PCI_AGP_RFU 3 /* Rest of capability flags */
  235. #define PCI_AGP_STATUS 4 /* Status register */
  236. #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
  237. #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
  238. #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
  239. #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
  240. #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
  241. #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
  242. #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
  243. #define PCI_AGP_COMMAND 8 /* Control register */
  244. #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
  245. #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
  246. #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
  247. #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
  248. #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
  249. #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
  250. #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
  251. #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
  252. #define PCI_AGP_SIZEOF 12
  253. /* Slot Identification */
  254. #define PCI_SID_ESR 2 /* Expansion Slot Register */
  255. #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
  256. #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
  257. #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
  258. /* Message Signalled Interrupts registers */
  259. #define PCI_MSI_FLAGS 2 /* Various flags */
  260. #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
  261. #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
  262. #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
  263. #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
  264. #define PCI_MSI_RFU 3 /* Rest of capability flags */
  265. #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
  266. #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  267. #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
  268. #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
  269. #define PCI_MAX_PCI_DEVICES 32
  270. #define PCI_MAX_PCI_FUNCTIONS 8
  271. /* Include the ID list */
  272. #include <pci_ids.h>
  273. struct pci_region {
  274. unsigned long bus_start; /* Start on the bus */
  275. unsigned long phys_start; /* Start in physical address space */
  276. unsigned long size; /* Size */
  277. unsigned long flags; /* Resource flags */
  278. unsigned long bus_lower;
  279. };
  280. #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
  281. #define PCI_REGION_IO 0x00000001 /* PCI IO space */
  282. #define PCI_REGION_TYPE 0x00000001
  283. #define PCI_REGION_MEMORY 0x00000100 /* System memory */
  284. #define PCI_REGION_RO 0x00000200 /* Read-only memory */
  285. extern __inline__ void pci_set_region(struct pci_region *reg,
  286. unsigned long bus_start,
  287. unsigned long phys_start,
  288. unsigned long size,
  289. unsigned long flags) {
  290. reg->bus_start = bus_start;
  291. reg->phys_start = phys_start;
  292. reg->size = size;
  293. reg->flags = flags;
  294. }
  295. typedef int pci_dev_t;
  296. #define PCI_BUS(d) (((d) >> 16) & 0xff)
  297. #define PCI_DEV(d) (((d) >> 11) & 0x1f)
  298. #define PCI_FUNC(d) (((d) >> 8) & 0x7)
  299. #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
  300. #define PCI_ANY_ID (~0)
  301. struct pci_device_id {
  302. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  303. };
  304. struct pci_controller;
  305. struct pci_config_table {
  306. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  307. unsigned int class; /* Class ID, or PCI_ANY_ID */
  308. unsigned int bus; /* Bus number, or PCI_ANY_ID */
  309. unsigned int dev; /* Device number, or PCI_ANY_ID */
  310. unsigned int func; /* Function number, or PCI_ANY_ID */
  311. void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
  312. struct pci_config_table *);
  313. unsigned long priv[3];
  314. };
  315. extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
  316. struct pci_config_table *);
  317. extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
  318. struct pci_config_table *);
  319. #define MAX_PCI_REGIONS 7
  320. /*
  321. * Structure of a PCI controller (host bridge)
  322. */
  323. struct pci_controller {
  324. struct pci_controller *next;
  325. int first_busno;
  326. int last_busno;
  327. volatile unsigned int *cfg_addr;
  328. volatile unsigned char *cfg_data;
  329. struct pci_region regions[MAX_PCI_REGIONS];
  330. int region_count;
  331. struct pci_config_table *config_table;
  332. void (*fixup_irq)(struct pci_controller *, pci_dev_t);
  333. /* Low-level architecture-dependent routines */
  334. int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
  335. int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
  336. int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
  337. int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
  338. int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
  339. int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
  340. /* Used by auto config */
  341. struct pci_region *pci_mem, *pci_io;
  342. /* Used by ppc405 autoconfig*/
  343. struct pci_region *pci_fb;
  344. int current_busno;
  345. };
  346. extern __inline__ void pci_set_ops(struct pci_controller *hose,
  347. int (*read_byte)(struct pci_controller*,
  348. pci_dev_t, int where, u8 *),
  349. int (*read_word)(struct pci_controller*,
  350. pci_dev_t, int where, u16 *),
  351. int (*read_dword)(struct pci_controller*,
  352. pci_dev_t, int where, u32 *),
  353. int (*write_byte)(struct pci_controller*,
  354. pci_dev_t, int where, u8),
  355. int (*write_word)(struct pci_controller*,
  356. pci_dev_t, int where, u16),
  357. int (*write_dword)(struct pci_controller*,
  358. pci_dev_t, int where, u32)) {
  359. hose->read_byte = read_byte;
  360. hose->read_word = read_word;
  361. hose->read_dword = read_dword;
  362. hose->write_byte = write_byte;
  363. hose->write_word = write_word;
  364. hose->write_dword = write_dword;
  365. }
  366. extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
  367. extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
  368. unsigned long addr, unsigned long flags);
  369. extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
  370. unsigned long addr, unsigned long flags);
  371. #define pci_phys_to_bus(dev, addr, flags) \
  372. pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  373. #define pci_bus_to_phys(dev, addr, flags) \
  374. pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  375. #define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
  376. #define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
  377. #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
  378. #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
  379. extern int pci_hose_read_config_byte(struct pci_controller *hose,
  380. pci_dev_t dev, int where, u8 *val);
  381. extern int pci_hose_read_config_word(struct pci_controller *hose,
  382. pci_dev_t dev, int where, u16 *val);
  383. extern int pci_hose_read_config_dword(struct pci_controller *hose,
  384. pci_dev_t dev, int where, u32 *val);
  385. extern int pci_hose_write_config_byte(struct pci_controller *hose,
  386. pci_dev_t dev, int where, u8 val);
  387. extern int pci_hose_write_config_word(struct pci_controller *hose,
  388. pci_dev_t dev, int where, u16 val);
  389. extern int pci_hose_write_config_dword(struct pci_controller *hose,
  390. pci_dev_t dev, int where, u32 val);
  391. extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
  392. extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
  393. extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
  394. extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
  395. extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
  396. extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
  397. extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
  398. pci_dev_t dev, int where, u8 *val);
  399. extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
  400. pci_dev_t dev, int where, u16 *val);
  401. extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
  402. pci_dev_t dev, int where, u8 val);
  403. extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
  404. pci_dev_t dev, int where, u16 val);
  405. extern void pci_register_hose(struct pci_controller* hose);
  406. extern struct pci_controller* pci_bus_to_hose(int bus);
  407. extern int pci_hose_scan(struct pci_controller *hose);
  408. extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
  409. extern void pciauto_region_init(struct pci_region* res);
  410. extern void pciauto_region_align(struct pci_region *res, unsigned long size);
  411. extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
  412. extern void pciauto_setup_device(struct pci_controller *hose,
  413. pci_dev_t dev, int bars_num,
  414. struct pci_region *mem,
  415. struct pci_region *io);
  416. int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  417. extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
  418. extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
  419. extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
  420. int wanted_prog_if, int index);
  421. extern int pci_hose_config_device(struct pci_controller *hose,
  422. pci_dev_t dev,
  423. unsigned long io,
  424. unsigned long mem,
  425. unsigned long command);
  426. #ifdef CONFIG_MPC824X
  427. extern void pci_mpc824x_init (struct pci_controller *hose);
  428. #endif
  429. #endif /* _PCI_H */