processor.h 44 KB

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  1. #ifndef __ASM_PPC_PROCESSOR_H
  2. #define __ASM_PPC_PROCESSOR_H
  3. /*
  4. * Default implementation of macro that returns current
  5. * instruction pointer ("program counter").
  6. */
  7. #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  8. #include <linux/config.h>
  9. #include <asm/ptrace.h>
  10. #include <asm/types.h>
  11. /* Machine State Register (MSR) Fields */
  12. #ifdef CONFIG_PPC64BRIDGE
  13. #define MSR_SF (1<<63)
  14. #define MSR_ISF (1<<61)
  15. #endif /* CONFIG_PPC64BRIDGE */
  16. #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
  17. #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
  18. #define MSR_SPE (1<<25) /* Enable SPE(e500) */
  19. #define MSR_POW (1<<18) /* Enable Power Management */
  20. #define MSR_WE (1<<18) /* Wait State Enable */
  21. #define MSR_TGPR (1<<17) /* TLB Update registers in use */
  22. #define MSR_CE (1<<17) /* Critical Interrupt Enable */
  23. #define MSR_ILE (1<<16) /* Interrupt Little Endian */
  24. #define MSR_EE (1<<15) /* External Interrupt Enable */
  25. #define MSR_PR (1<<14) /* Problem State / Privilege Level */
  26. #define MSR_FP (1<<13) /* Floating Point enable */
  27. #define MSR_ME (1<<12) /* Machine Check Enable */
  28. #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
  29. #define MSR_SE (1<<10) /* Single Step */
  30. #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
  31. #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
  32. #define MSR_BE (1<<9) /* Branch Trace */
  33. #define MSR_DE (1<<9) /* Debug Exception Enable */
  34. #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
  35. #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
  36. #define MSR_IR (1<<5) /* Instruction Relocate */
  37. #define MSR_IS (1<<5) /* Book E Instruction space */
  38. #define MSR_DR (1<<4) /* Data Relocate */
  39. #define MSR_DS (1<<4) /* Book E Data space */
  40. #define MSR_PE (1<<3) /* Protection Enable */
  41. #define MSR_PX (1<<2) /* Protection Exclusive Mode */
  42. #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
  43. #define MSR_RI (1<<1) /* Recoverable Exception */
  44. #define MSR_LE (1<<0) /* Little Endian */
  45. #ifdef CONFIG_APUS_FAST_EXCEPT
  46. #define MSR_ MSR_ME|MSR_IP|MSR_RI
  47. #else
  48. #define MSR_ MSR_ME|MSR_RI
  49. #endif
  50. #ifndef CONFIG_E500
  51. #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
  52. #else
  53. #define MSR_KERNEL MSR_ME
  54. #endif
  55. #define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
  56. /* Floating Point Status and Control Register (FPSCR) Fields */
  57. #define FPSCR_FX 0x80000000 /* FPU exception summary */
  58. #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
  59. #define FPSCR_VX 0x20000000 /* Invalid operation summary */
  60. #define FPSCR_OX 0x10000000 /* Overflow exception summary */
  61. #define FPSCR_UX 0x08000000 /* Underflow exception summary */
  62. #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
  63. #define FPSCR_XX 0x02000000 /* Inexact exception summary */
  64. #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
  65. #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
  66. #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
  67. #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
  68. #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
  69. #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
  70. #define FPSCR_FR 0x00040000 /* Fraction rounded */
  71. #define FPSCR_FI 0x00020000 /* Fraction inexact */
  72. #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
  73. #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
  74. #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
  75. #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
  76. #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
  77. #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
  78. #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
  79. #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
  80. #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
  81. #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
  82. #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
  83. #define FPSCR_RN 0x00000003 /* FPU rounding control */
  84. /* Special Purpose Registers (SPRNs)*/
  85. #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
  86. #define SPRN_CTR 0x009 /* Count Register */
  87. #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
  88. #ifndef CONFIG_BOOKE
  89. #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
  90. #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
  91. #else
  92. #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
  93. #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
  94. #endif /* CONFIG_BOOKE */
  95. #define SPRN_DAR 0x013 /* Data Address Register */
  96. #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
  97. #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
  98. #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
  99. #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
  100. #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
  101. #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
  102. #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
  103. #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
  104. #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
  105. #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
  106. #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
  107. #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
  108. #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
  109. #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
  110. #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
  111. #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
  112. #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
  113. #define DBCR_EDM 0x80000000
  114. #define DBCR_IDM 0x40000000
  115. #define DBCR_RST(x) (((x) & 0x3) << 28)
  116. #define DBCR_RST_NONE 0
  117. #define DBCR_RST_CORE 1
  118. #define DBCR_RST_CHIP 2
  119. #define DBCR_RST_SYSTEM 3
  120. #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
  121. #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
  122. #define DBCR_EDE 0x02000000 /* Exception Debug Event */
  123. #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
  124. #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
  125. #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
  126. #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
  127. #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
  128. #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
  129. #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
  130. #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
  131. #define DAC_BYTE 0
  132. #define DAC_HALF 1
  133. #define DAC_WORD 2
  134. #define DAC_QUAD 3
  135. #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
  136. #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
  137. #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
  138. #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
  139. #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
  140. #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
  141. #define DBCR_SIA 0x00000008 /* Second IAC Enable */
  142. #define DBCR_SDA 0x00000004 /* Second DAC Enable */
  143. #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
  144. #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
  145. #ifndef CONFIG_BOOKE
  146. #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
  147. #else
  148. #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
  149. #endif /* CONFIG_BOOKE */
  150. #ifndef CONFIG_BOOKE
  151. #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
  152. #define SPRN_DBSR 0x3F0 /* Debug Status Register */
  153. #else
  154. #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
  155. #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
  156. #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
  157. #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
  158. #endif /* CONFIG_BOOKE */
  159. #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
  160. #define DCCR_NOCACHE 0 /* Noncacheable */
  161. #define DCCR_CACHE 1 /* Cacheable */
  162. #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
  163. #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
  164. #define DCWR_COPY 0 /* Copy-back */
  165. #define DCWR_WRITE 1 /* Write-through */
  166. #ifndef CONFIG_BOOKE
  167. #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
  168. #else
  169. #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
  170. #endif /* CONFIG_BOOKE */
  171. #define SPRN_DEC 0x016 /* Decrement Register */
  172. #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
  173. #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
  174. #define SPRN_EAR 0x11A /* External Address Register */
  175. #ifndef CONFIG_BOOKE
  176. #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
  177. #else
  178. #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
  179. #endif /* CONFIG_BOOKE */
  180. #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
  181. #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
  182. #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
  183. #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
  184. #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
  185. #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
  186. #define ESR_PTR 0x02000000 /* Program Exception - Trap */
  187. #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
  188. #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
  189. #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
  190. #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
  191. #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
  192. #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
  193. #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
  194. #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
  195. #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
  196. #define HID0_SBCLK (1<<27)
  197. #define HID0_EICE (1<<26)
  198. #define HID0_ECLK (1<<25)
  199. #define HID0_PAR (1<<24)
  200. #define HID0_DOZE (1<<23)
  201. #define HID0_NAP (1<<22)
  202. #define HID0_SLEEP (1<<21)
  203. #define HID0_DPM (1<<20)
  204. #define HID0_ICE (1<<15) /* Instruction Cache Enable */
  205. #define HID0_DCE (1<<14) /* Data Cache Enable */
  206. #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
  207. #define HID0_DLOCK (1<<12) /* Data Cache Lock */
  208. #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
  209. #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
  210. #define HID0_DCI HID0_DCFI
  211. #define HID0_SPD (1<<9) /* Speculative disable */
  212. #define HID0_SGE (1<<7) /* Store Gathering Enable */
  213. #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
  214. #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
  215. #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
  216. #define HID0_ABE (1<<3) /* Address Broadcast Enable */
  217. #define HID0_BHTE (1<<2) /* Branch History Table Enable */
  218. #define HID0_BTCD (1<<1) /* Branch target cache disable */
  219. #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
  220. #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
  221. #ifndef CONFIG_BOOKE
  222. #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
  223. #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
  224. #else
  225. #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
  226. #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
  227. #endif /* CONFIG_BOOKE */
  228. #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
  229. #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
  230. #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
  231. #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
  232. #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
  233. #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
  234. #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
  235. #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
  236. #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
  237. #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
  238. #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
  239. #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
  240. #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
  241. #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
  242. #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
  243. #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
  244. #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
  245. #define ICCR_NOCACHE 0 /* Noncacheable */
  246. #define ICCR_CACHE 1 /* Cacheable */
  247. #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
  248. #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
  249. #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
  250. #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
  251. #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
  252. #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
  253. #define SPRN_LR 0x008 /* Link Register */
  254. #define SPRN_MBAR 0x137 /* System memory base address */
  255. #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
  256. #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
  257. #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
  258. #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
  259. #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
  260. #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
  261. #ifndef CONFIG_BOOKE
  262. #define SPRN_PID 0x3B1 /* Process ID */
  263. #define SPRN_PIR 0x3FF /* Processor Identification Register */
  264. #else
  265. #define SPRN_PID 0x030 /* Book E Process ID */
  266. #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
  267. #endif /* CONFIG_BOOKE */
  268. #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
  269. #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
  270. #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
  271. #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
  272. #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
  273. #define SPRN_PVR 0x11F /* Processor Version Register */
  274. #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
  275. #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
  276. #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
  277. #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
  278. #define SGR_NORMAL 0
  279. #define SGR_GUARDED 1
  280. #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
  281. #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
  282. #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
  283. #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
  284. #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
  285. #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
  286. #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
  287. #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
  288. #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
  289. #ifdef CONFIG_BOOKE
  290. #define SPRN_SVR 0x3FF /* System Version Register */
  291. #else
  292. #define SPRN_SVR 0x11E /* System Version Register */
  293. #endif
  294. #define SPRN_TBHI 0x3DC /* Time Base High */
  295. #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
  296. #define SPRN_TBLO 0x3DD /* Time Base Low */
  297. #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
  298. #define SPRN_TBRL 0x10D /* Time Base Read Lower Register */
  299. #define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
  300. #define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
  301. #define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
  302. #ifndef CONFIG_BOOKE
  303. #define SPRN_TCR 0x3DA /* Timer Control Register */
  304. #else
  305. #define SPRN_TCR 0x154 /* Book E Timer Control Register */
  306. #endif /* CONFIG_BOOKE */
  307. #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
  308. #define WP_2_17 0 /* 2^17 clocks */
  309. #define WP_2_21 1 /* 2^21 clocks */
  310. #define WP_2_25 2 /* 2^25 clocks */
  311. #define WP_2_29 3 /* 2^29 clocks */
  312. #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
  313. #define WRC_NONE 0 /* No reset will occur */
  314. #define WRC_CORE 1 /* Core reset will occur */
  315. #define WRC_CHIP 2 /* Chip reset will occur */
  316. #define WRC_SYSTEM 3 /* System reset will occur */
  317. #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
  318. #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
  319. #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
  320. #define FP_2_9 0 /* 2^9 clocks */
  321. #define FP_2_13 1 /* 2^13 clocks */
  322. #define FP_2_17 2 /* 2^17 clocks */
  323. #define FP_2_21 3 /* 2^21 clocks */
  324. #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
  325. #define TCR_ARE 0x00400000 /* Auto Reload Enable */
  326. #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
  327. #define THRM1_TIN (1<<0)
  328. #define THRM1_TIV (1<<1)
  329. #define THRM1_THRES (0x7f<<2)
  330. #define THRM1_TID (1<<29)
  331. #define THRM1_TIE (1<<30)
  332. #define THRM1_V (1<<31)
  333. #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
  334. #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
  335. #define THRM3_E (1<<31)
  336. #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
  337. #ifndef CONFIG_BOOKE
  338. #define SPRN_TSR 0x3D8 /* Timer Status Register */
  339. #else
  340. #define SPRN_TSR 0x150 /* Book E Timer Status Register */
  341. #endif /* CONFIG_BOOKE */
  342. #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
  343. #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
  344. #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
  345. #define WRS_NONE 0 /* No WDT reset occurred */
  346. #define WRS_CORE 1 /* WDT forced core reset */
  347. #define WRS_CHIP 2 /* WDT forced chip reset */
  348. #define WRS_SYSTEM 3 /* WDT forced system reset */
  349. #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
  350. #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
  351. #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
  352. #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
  353. #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
  354. #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
  355. #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
  356. #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
  357. #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
  358. #define SPRN_XER 0x001 /* Fixed Point Exception Register */
  359. #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
  360. /* Book E definitions */
  361. #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
  362. #define SPRN_CSRR0 0x03A /* Critical SRR0 */
  363. #define SPRN_CSRR1 0x03B /* Critical SRR0 */
  364. #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
  365. #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
  366. #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
  367. #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
  368. #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
  369. #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
  370. #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
  371. #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
  372. #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
  373. #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
  374. #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
  375. #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
  376. #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
  377. #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
  378. #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
  379. #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
  380. #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
  381. #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
  382. #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
  383. #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
  384. #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
  385. #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
  386. #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
  387. #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
  388. #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
  389. #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
  390. #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
  391. #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
  392. #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
  393. #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
  394. #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
  395. /* e500 definitions */
  396. #define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
  397. #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
  398. #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
  399. #define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
  400. #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
  401. #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
  402. #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
  403. #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
  404. #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
  405. #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
  406. #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
  407. #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
  408. #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
  409. #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
  410. #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
  411. #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
  412. #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
  413. #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
  414. #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
  415. #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
  416. #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
  417. #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
  418. #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
  419. #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
  420. #define SPRN_PID1 0x279 /* Process ID Register 1 */
  421. #define SPRN_PID2 0x27a /* Process ID Register 2 */
  422. #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
  423. #define ESR_ST 0x00800000 /* Store Operation */
  424. /* Short-hand versions for a number of the above SPRNs */
  425. #define CTR SPRN_CTR /* Counter Register */
  426. #define DAR SPRN_DAR /* Data Address Register */
  427. #define DABR SPRN_DABR /* Data Address Breakpoint Register */
  428. #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
  429. #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
  430. #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
  431. #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
  432. #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
  433. #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
  434. #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
  435. #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
  436. #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
  437. #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
  438. #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
  439. #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
  440. #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
  441. #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
  442. #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
  443. #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
  444. #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
  445. #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
  446. #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
  447. #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
  448. #define DBSR SPRN_DBSR /* Debug Status Register */
  449. #define DCMP SPRN_DCMP /* Data TLB Compare Register */
  450. #define DEC SPRN_DEC /* Decrement Register */
  451. #define DMISS SPRN_DMISS /* Data TLB Miss Register */
  452. #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
  453. #define EAR SPRN_EAR /* External Address Register */
  454. #define ESR SPRN_ESR /* Exception Syndrome Register */
  455. #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
  456. #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
  457. #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
  458. #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
  459. #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
  460. #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
  461. #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
  462. #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
  463. #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
  464. #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
  465. #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
  466. #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
  467. #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
  468. #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
  469. #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
  470. #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
  471. #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
  472. #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
  473. #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
  474. #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
  475. #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
  476. #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
  477. #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
  478. #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
  479. #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
  480. #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
  481. #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
  482. #define LR SPRN_LR
  483. #define MBAR SPRN_MBAR /* System memory base address */
  484. #if defined(CONFIG_E500)
  485. #define PIR SPRN_PIR
  486. #endif
  487. #define SVR SPRN_SVR /* System-On-Chip Version Register */
  488. #define PVR SPRN_PVR /* Processor Version */
  489. #define RPA SPRN_RPA /* Required Physical Address Register */
  490. #define SDR1 SPRN_SDR1 /* MMU hash base register */
  491. #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
  492. #define SPR1 SPRN_SPRG1
  493. #define SPR2 SPRN_SPRG2
  494. #define SPR3 SPRN_SPRG3
  495. #define SPRG0 SPRN_SPRG0
  496. #define SPRG1 SPRN_SPRG1
  497. #define SPRG2 SPRN_SPRG2
  498. #define SPRG3 SPRN_SPRG3
  499. #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
  500. #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
  501. #define SVR SPRN_SVR /* System Version Register */
  502. #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
  503. #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
  504. #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
  505. #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
  506. #define TCR SPRN_TCR /* Timer Control Register */
  507. #define TSR SPRN_TSR /* Timer Status Register */
  508. #define ICTC 1019
  509. #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
  510. #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
  511. #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
  512. #define XER SPRN_XER
  513. #define DECAR SPRN_DECAR
  514. #define CSRR0 SPRN_CSRR0
  515. #define CSRR1 SPRN_CSRR1
  516. #define IVPR SPRN_IVPR
  517. #define USPRG0 SPRN_USPRG0
  518. #define SPRG4R SPRN_SPRG4R
  519. #define SPRG5R SPRN_SPRG5R
  520. #define SPRG6R SPRN_SPRG6R
  521. #define SPRG7R SPRN_SPRG7R
  522. #define SPRG4W SPRN_SPRG4W
  523. #define SPRG5W SPRN_SPRG5W
  524. #define SPRG6W SPRN_SPRG6W
  525. #define SPRG7W SPRN_SPRG7W
  526. #define DEAR SPRN_DEAR
  527. #define DBCR2 SPRN_DBCR2
  528. #define IAC3 SPRN_IAC3
  529. #define IAC4 SPRN_IAC4
  530. #define DVC1 SPRN_DVC1
  531. #define DVC2 SPRN_DVC2
  532. #define IVOR0 SPRN_IVOR0
  533. #define IVOR1 SPRN_IVOR1
  534. #define IVOR2 SPRN_IVOR2
  535. #define IVOR3 SPRN_IVOR3
  536. #define IVOR4 SPRN_IVOR4
  537. #define IVOR5 SPRN_IVOR5
  538. #define IVOR6 SPRN_IVOR6
  539. #define IVOR7 SPRN_IVOR7
  540. #define IVOR8 SPRN_IVOR8
  541. #define IVOR9 SPRN_IVOR9
  542. #define IVOR10 SPRN_IVOR10
  543. #define IVOR11 SPRN_IVOR11
  544. #define IVOR12 SPRN_IVOR12
  545. #define IVOR13 SPRN_IVOR13
  546. #define IVOR14 SPRN_IVOR14
  547. #define IVOR15 SPRN_IVOR15
  548. #define IVOR32 SPRN_IVOR32
  549. #define IVOR33 SPRN_IVOR33
  550. #define IVOR34 SPRN_IVOR34
  551. #define IVOR35 SPRN_IVOR35
  552. #define MCSRR0 SPRN_MCSRR0
  553. #define MCSRR1 SPRN_MCSRR1
  554. #define L1CSR0 SPRN_L1CSR0
  555. #define L1CSR1 SPRN_L1CSR1
  556. #define MCSR SPRN_MCSR
  557. #define MMUCSR0 SPRN_MMUCSR0
  558. #define BUCSR SPRN_BUCSR
  559. #define PID0 SPRN_PID
  560. #define PID1 SPRN_PID1
  561. #define PID2 SPRN_PID2
  562. #define MAS0 SPRN_MAS0
  563. #define MAS1 SPRN_MAS1
  564. #define MAS2 SPRN_MAS2
  565. #define MAS3 SPRN_MAS3
  566. #define MAS4 SPRN_MAS4
  567. #define MAS5 SPRN_MAS5
  568. #define MAS6 SPRN_MAS6
  569. /* Device Control Registers */
  570. #define DCRN_BEAR 0x090 /* Bus Error Address Register */
  571. #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
  572. #define BESR_DSES 0x80000000 /* Data-Side Error Status */
  573. #define BESR_DMES 0x40000000 /* DMA Error Status */
  574. #define BESR_RWS 0x20000000 /* Read/Write Status */
  575. #define BESR_ETMASK 0x1C000000 /* Error Type */
  576. #define ET_PROT 0
  577. #define ET_PARITY 1
  578. #define ET_NCFG 2
  579. #define ET_BUSERR 4
  580. #define ET_BUSTO 6
  581. #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
  582. #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
  583. #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
  584. #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
  585. #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
  586. #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
  587. #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
  588. #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
  589. #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
  590. #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
  591. #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
  592. #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
  593. #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
  594. #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
  595. #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
  596. #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
  597. #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
  598. #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
  599. #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
  600. #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
  601. #define DCRN_DMASR 0x0E0 /* DMA Status Register */
  602. #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
  603. #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
  604. #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
  605. #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
  606. #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
  607. #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
  608. #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
  609. #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
  610. #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
  611. #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
  612. #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
  613. #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
  614. #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
  615. #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
  616. #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
  617. #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
  618. #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
  619. #define IOCR_E0TE 0x80000000
  620. #define IOCR_E0LP 0x40000000
  621. #define IOCR_E1TE 0x20000000
  622. #define IOCR_E1LP 0x10000000
  623. #define IOCR_E2TE 0x08000000
  624. #define IOCR_E2LP 0x04000000
  625. #define IOCR_E3TE 0x02000000
  626. #define IOCR_E3LP 0x01000000
  627. #define IOCR_E4TE 0x00800000
  628. #define IOCR_E4LP 0x00400000
  629. #define IOCR_EDT 0x00080000
  630. #define IOCR_SOR 0x00040000
  631. #define IOCR_EDO 0x00008000
  632. #define IOCR_2XC 0x00004000
  633. #define IOCR_ATC 0x00002000
  634. #define IOCR_SPD 0x00001000
  635. #define IOCR_BEM 0x00000800
  636. #define IOCR_PTD 0x00000400
  637. #define IOCR_ARE 0x00000080
  638. #define IOCR_DRC 0x00000020
  639. #define IOCR_RDM(x) (((x) & 0x3) << 3)
  640. #define IOCR_TCS 0x00000004
  641. #define IOCR_SCS 0x00000002
  642. #define IOCR_SPC 0x00000001
  643. /* System-On-Chip Version Register */
  644. /* System-On-Chip Version Register (SVR) field extraction */
  645. #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
  646. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
  647. #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
  648. #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
  649. #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
  650. #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
  651. #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
  652. #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
  653. #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
  654. /* System-On-Chip Version Numbers (version field only) */
  655. #define SVR_MPC5200 0x8011
  656. /* Processor Version Register */
  657. /* Processor Version Register (PVR) field extraction */
  658. #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
  659. #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
  660. /*
  661. * IBM has further subdivided the standard PowerPC 16-bit version and
  662. * revision subfields of the PVR for the PowerPC 403s into the following:
  663. */
  664. #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
  665. #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
  666. #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
  667. #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
  668. #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
  669. #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
  670. /* Processor Version Numbers */
  671. #define PVR_403GA 0x00200000
  672. #define PVR_403GB 0x00200100
  673. #define PVR_403GC 0x00200200
  674. #define PVR_403GCX 0x00201400
  675. #define PVR_405GP 0x40110000
  676. #define PVR_405GP_RB 0x40110040
  677. #define PVR_405GP_RC 0x40110082
  678. #define PVR_405GP_RD 0x401100C4
  679. #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
  680. #define PVR_405CR_RA 0x40110041
  681. #define PVR_405CR_RB 0x401100C5
  682. #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
  683. #define PVR_405EP_RA 0x51210950
  684. #define PVR_405GPR_RB 0x50910951
  685. #define PVR_440GP_RB 0x40120440
  686. #define PVR_440GP_RC 0x40120481
  687. #define PVR_440EP_RA 0x42221850
  688. #define PVR_440EP_RB 0x422218D3
  689. #define PVR_440GX_RA 0x51B21850
  690. #define PVR_440GX_RB 0x51B21851
  691. #define PVR_440GX_RC 0x51B21892
  692. #define PVR_405EP_RB 0x51210950
  693. #define PVR_601 0x00010000
  694. #define PVR_602 0x00050000
  695. #define PVR_603 0x00030000
  696. #define PVR_603e 0x00060000
  697. #define PVR_603ev 0x00070000
  698. #define PVR_603r 0x00071000
  699. #define PVR_604 0x00040000
  700. #define PVR_604e 0x00090000
  701. #define PVR_604r 0x000A0000
  702. #define PVR_620 0x00140000
  703. #define PVR_740 0x00080000
  704. #define PVR_750 PVR_740
  705. #define PVR_740P 0x10080000
  706. #define PVR_750P PVR_740P
  707. #define PVR_7400 0x000C0000
  708. #define PVR_7410 0x800C0000
  709. #define PVR_7450 0x80000000
  710. #define PVR_85xx 0x80200000
  711. #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
  712. #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
  713. /*
  714. * For the 8xx processors, all of them report the same PVR family for
  715. * the PowerPC core. The various versions of these processors must be
  716. * differentiated by the version number in the Communication Processor
  717. * Module (CPM).
  718. */
  719. #define PVR_821 0x00500000
  720. #define PVR_823 PVR_821
  721. #define PVR_850 PVR_821
  722. #define PVR_860 PVR_821
  723. #define PVR_7400 0x000C0000
  724. #define PVR_8240 0x00810100
  725. /*
  726. * PowerQUICC II family processors report different PVR values depending
  727. * on silicon process (HiP3, HiP4, HiP7, etc.)
  728. */
  729. #define PVR_8260 PVR_8240
  730. #define PVR_8260_HIP3 0x00810101
  731. #define PVR_8260_HIP4 0x80811014
  732. #define PVR_8260_HIP7 0x80822011
  733. #define PVR_8260_HIP7R1 0x80822013
  734. #define PVR_8260_HIP7RA 0x80822014
  735. /*
  736. * System Version Register
  737. */
  738. /* System Version Register (SVR) field extraction */
  739. #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
  740. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
  741. #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
  742. #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
  743. #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
  744. #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
  745. /*
  746. * SVR_VER() Version Values
  747. */
  748. #define SVR_8540 0x8030
  749. #define SVR_8560 0x8070
  750. #define SVR_8555 0x8079
  751. #define SVR_8541 0x807A
  752. /* I am just adding a single entry for 8260 boards. I think we may be
  753. * able to combine mbx, fads, rpxlite, bseip, and classic into a single
  754. * generic 8xx as well. The boards containing these processors are either
  755. * identical at the processor level (due to the high integration) or so
  756. * wildly different that testing _machine at run time is best replaced by
  757. * conditional compilation by board type (found in their respective .h file).
  758. * -- Dan
  759. */
  760. #define _MACH_prep 0x00000001
  761. #define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
  762. #define _MACH_chrp 0x00000004 /* chrp machine */
  763. #define _MACH_mbx 0x00000008 /* Motorola MBX board */
  764. #define _MACH_apus 0x00000010 /* amiga with phase5 powerup */
  765. #define _MACH_fads 0x00000020 /* Motorola FADS board */
  766. #define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */
  767. #define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */
  768. #define _MACH_yk 0x00000100 /* Motorola Yellowknife */
  769. #define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
  770. #define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
  771. #define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
  772. #define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */
  773. #define _MACH_8260 0x00002000 /* Generic 8260 */
  774. #define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
  775. #define _MACH_tqm860 0x00008000 /* TQM860/L */
  776. #define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
  777. #define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
  778. /* see residual.h for these */
  779. #define _PREP_Motorola 0x01 /* motorola prep */
  780. #define _PREP_Firm 0x02 /* firmworks prep */
  781. #define _PREP_IBM 0x00 /* ibm prep */
  782. #define _PREP_Bull 0x03 /* bull prep */
  783. #define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */
  784. /*
  785. * Radstone board types
  786. */
  787. #define RS_SYS_TYPE_PPC1 0
  788. #define RS_SYS_TYPE_PPC2 1
  789. #define RS_SYS_TYPE_PPC1a 2
  790. #define RS_SYS_TYPE_PPC2a 3
  791. #define RS_SYS_TYPE_PPC4 4
  792. #define RS_SYS_TYPE_PPC4a 5
  793. #define RS_SYS_TYPE_PPC2ep 6
  794. /* these are arbitrary */
  795. #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
  796. #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
  797. #define _GLOBAL(n)\
  798. .globl n;\
  799. n:
  800. /* Macros for setting and retrieving special purpose registers */
  801. #define stringify(s) tostring(s)
  802. #define tostring(s) #s
  803. #define mfdcr(rn) ({unsigned int rval; \
  804. asm volatile("mfdcr %0," stringify(rn) \
  805. : "=r" (rval)); rval;})
  806. #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
  807. #define mfmsr() ({unsigned int rval; \
  808. asm volatile("mfmsr %0" : "=r" (rval)); rval;})
  809. #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
  810. #define mfspr(rn) ({unsigned int rval; \
  811. asm volatile("mfspr %0," stringify(rn) \
  812. : "=r" (rval)); rval;})
  813. #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
  814. #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
  815. /* Segment Registers */
  816. #define SR0 0
  817. #define SR1 1
  818. #define SR2 2
  819. #define SR3 3
  820. #define SR4 4
  821. #define SR5 5
  822. #define SR6 6
  823. #define SR7 7
  824. #define SR8 8
  825. #define SR9 9
  826. #define SR10 10
  827. #define SR11 11
  828. #define SR12 12
  829. #define SR13 13
  830. #define SR14 14
  831. #define SR15 15
  832. #ifndef __ASSEMBLY__
  833. #ifndef CONFIG_MACH_SPECIFIC
  834. extern int _machine;
  835. extern int have_of;
  836. #endif /* CONFIG_MACH_SPECIFIC */
  837. /* what kind of prep workstation we are */
  838. extern int _prep_type;
  839. /*
  840. * This is used to identify the board type from a given PReP board
  841. * vendor. Board revision is also made available.
  842. */
  843. extern unsigned char ucSystemType;
  844. extern unsigned char ucBoardRev;
  845. extern unsigned char ucBoardRevMaj, ucBoardRevMin;
  846. struct task_struct;
  847. void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
  848. void release_thread(struct task_struct *);
  849. /*
  850. * Create a new kernel thread.
  851. */
  852. extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
  853. /*
  854. * Bus types
  855. */
  856. #define EISA_bus 0
  857. #define EISA_bus__is_a_macro /* for versions in ksyms.c */
  858. #define MCA_bus 0
  859. #define MCA_bus__is_a_macro /* for versions in ksyms.c */
  860. /* Lazy FPU handling on uni-processor */
  861. extern struct task_struct *last_task_used_math;
  862. extern struct task_struct *last_task_used_altivec;
  863. /*
  864. * this is the minimum allowable io space due to the location
  865. * of the io areas on prep (first one at 0x80000000) but
  866. * as soon as I get around to remapping the io areas with the BATs
  867. * to match the mac we can raise this. -- Cort
  868. */
  869. #define TASK_SIZE (0x80000000UL)
  870. /* This decides where the kernel will search for a free chunk of vm
  871. * space during mmap's.
  872. */
  873. #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
  874. typedef struct {
  875. unsigned long seg;
  876. } mm_segment_t;
  877. struct thread_struct {
  878. unsigned long ksp; /* Kernel stack pointer */
  879. unsigned long wchan; /* Event task is sleeping on */
  880. struct pt_regs *regs; /* Pointer to saved register state */
  881. mm_segment_t fs; /* for get_fs() validation */
  882. void *pgdir; /* root of page-table tree */
  883. signed long last_syscall;
  884. double fpr[32]; /* Complete floating point set */
  885. unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
  886. unsigned long fpscr; /* Floating point status */
  887. #ifdef CONFIG_ALTIVEC
  888. vector128 vr[32]; /* Complete AltiVec set */
  889. vector128 vscr; /* AltiVec status */
  890. unsigned long vrsave;
  891. #endif /* CONFIG_ALTIVEC */
  892. };
  893. #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
  894. #define INIT_THREAD { \
  895. INIT_SP, /* ksp */ \
  896. 0, /* wchan */ \
  897. (struct pt_regs *)INIT_SP - 1, /* regs */ \
  898. KERNEL_DS, /*fs*/ \
  899. swapper_pg_dir, /* pgdir */ \
  900. 0, /* last_syscall */ \
  901. {0}, 0, 0 \
  902. }
  903. /*
  904. * Note: the vm_start and vm_end fields here should *not*
  905. * be in kernel space. (Could vm_end == vm_start perhaps?)
  906. */
  907. #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
  908. PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
  909. 1, NULL, NULL }
  910. /*
  911. * Return saved PC of a blocked thread. For now, this is the "user" PC
  912. */
  913. static inline unsigned long thread_saved_pc(struct thread_struct *t)
  914. {
  915. return (t->regs) ? t->regs->nip : 0;
  916. }
  917. #define copy_segments(tsk, mm) do { } while (0)
  918. #define release_segments(mm) do { } while (0)
  919. #define forget_segments() do { } while (0)
  920. unsigned long get_wchan(struct task_struct *p);
  921. #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
  922. #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
  923. /*
  924. * NOTE! The task struct and the stack go together
  925. */
  926. #define THREAD_SIZE (2*PAGE_SIZE)
  927. #define alloc_task_struct() \
  928. ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
  929. #define free_task_struct(p) free_pages((unsigned long)(p),1)
  930. #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
  931. /* in process.c - for early bootup debug -- Cort */
  932. int ll_printk(const char *, ...);
  933. void ll_puts(const char *);
  934. #define init_task (init_task_union.task)
  935. #define init_stack (init_task_union.stack)
  936. /* In misc.c */
  937. void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
  938. #endif /* ndef ASSEMBLY*/
  939. #ifdef CONFIG_MACH_SPECIFIC
  940. #if defined(CONFIG_8xx)
  941. #define _machine _MACH_8xx
  942. #define have_of 0
  943. #elif defined(CONFIG_OAK)
  944. #define _machine _MACH_oak
  945. #define have_of 0
  946. #elif defined(CONFIG_WALNUT)
  947. #define _machine _MACH_walnut
  948. #define have_of 0
  949. #elif defined(CONFIG_APUS)
  950. #define _machine _MACH_apus
  951. #define have_of 0
  952. #elif defined(CONFIG_GEMINI)
  953. #define _machine _MACH_gemini
  954. #define have_of 0
  955. #elif defined(CONFIG_8260)
  956. #define _machine _MACH_8260
  957. #define have_of 0
  958. #elif defined(CONFIG_SANDPOINT)
  959. #define _machine _MACH_sandpoint
  960. #elif defined(CONFIG_HIDDEN_DRAGON)
  961. #define _machine _MACH_hidden_dragon
  962. #define have_of 0
  963. #else
  964. #error "Machine not defined correctly"
  965. #endif
  966. #endif /* CONFIG_MACH_SPECIFIC */
  967. #endif /* __ASM_PPC_PROCESSOR_H */