440gx_enet.h 15 KB

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  1. /*----------------------------------------------------------------------------+
  2. |
  3. | This source code has been made available to you by IBM on an AS-IS
  4. | basis. Anyone receiving this source is licensed under IBM
  5. | copyrights to use it in any way he or she deems fit, including
  6. | copying it, modifying it, compiling it, and redistributing it either
  7. | with or without modifications. No license under IBM patents or
  8. | patent applications is to be implied by the copyright license.
  9. |
  10. | Any user of this software should understand that IBM cannot provide
  11. | technical support for this software and will not be responsible for
  12. | any consequences resulting from the use of this software.
  13. |
  14. | Any person who transfers this source code or any derivative work
  15. | must include the IBM copyright notice, this paragraph, and the
  16. | preceding two paragraphs in the transferred software.
  17. |
  18. | COPYRIGHT I B M CORPORATION 1999
  19. | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  20. +----------------------------------------------------------------------------*/
  21. /*----------------------------------------------------------------------------+
  22. |
  23. | File Name: enetemac.h
  24. |
  25. | Function: Header file for the EMAC3 macro on the 405GP.
  26. |
  27. | Author: Mark Wisner
  28. |
  29. | Change Activity-
  30. |
  31. | Date Description of Change BY
  32. | --------- --------------------- ---
  33. | 29-Apr-99 Created MKW
  34. |
  35. +----------------------------------------------------------------------------*/
  36. /*----------------------------------------------------------------------------+
  37. | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  38. | ported to handle 440GP and 440GX multiple EMACs
  39. +----------------------------------------------------------------------------*/
  40. #ifndef _emacgx_enet_h_
  41. #define _emacgx_enet_h_
  42. #if defined(CONFIG_440)
  43. #include <net.h>
  44. #include "405_mal.h"
  45. /*-----------------------------------------------------------------------------+
  46. | General enternet defines. 802 frames are not supported.
  47. +-----------------------------------------------------------------------------*/
  48. #define ENET_ADDR_LENGTH 6
  49. #define ENET_ARPTYPE 0x806
  50. #define ARP_REQUEST 1
  51. #define ARP_REPLY 2
  52. #define ENET_IPTYPE 0x800
  53. #define ARP_CACHE_SIZE 5
  54. #define NUM_TX_BUFF 1
  55. #define NUM_RX_BUFF PKTBUFSRX
  56. struct enet_frame {
  57. unsigned char dest_addr[ENET_ADDR_LENGTH];
  58. unsigned char source_addr[ENET_ADDR_LENGTH];
  59. unsigned short type;
  60. unsigned char enet_data[1];
  61. };
  62. struct arp_entry {
  63. unsigned long inet_address;
  64. unsigned char mac_address[ENET_ADDR_LENGTH];
  65. unsigned long valid;
  66. unsigned long sec;
  67. unsigned long nsec;
  68. };
  69. /* Statistic Areas */
  70. #define MAX_ERR_LOG 10
  71. typedef struct emac_stats_st{ /* Statistic Block */
  72. int data_len_err;
  73. int rx_frames;
  74. int rx;
  75. int rx_prot_err;
  76. int int_err;
  77. int pkts_tx;
  78. int pkts_rx;
  79. int pkts_handled;
  80. short tx_err_log[MAX_ERR_LOG];
  81. short rx_err_log[MAX_ERR_LOG];
  82. } EMAC_STATS_ST, *EMAC_STATS_PST;
  83. /* Structure containing variables used by the shared code (440gx_enet.c) */
  84. typedef struct emac_440gx_hw_st {
  85. uint32_t hw_addr; /* EMAC offset */
  86. uint32_t tah_addr; /* TAH offset */
  87. uint32_t phy_id;
  88. uint32_t phy_addr;
  89. uint32_t original_fc;
  90. uint32_t txcw;
  91. uint32_t autoneg_failed;
  92. uint32_t emac_ier;
  93. volatile mal_desc_t *tx;
  94. volatile mal_desc_t *rx;
  95. bd_t *bis; /* for eth_init upon mal error */
  96. mal_desc_t *alloc_tx_buf;
  97. mal_desc_t *alloc_rx_buf;
  98. char *txbuf_ptr;
  99. uint16_t devnum;
  100. int get_link_status;
  101. int tbi_compatibility_en;
  102. int tbi_compatibility_on;
  103. int fc_send_xon;
  104. int report_tx_early;
  105. int first_init;
  106. int tx_err_index;
  107. int rx_err_index;
  108. int rx_slot; /* MAL Receive Slot */
  109. int rx_i_index; /* Receive Interrupt Queue Index */
  110. int rx_u_index; /* Receive User Queue Index */
  111. int tx_slot; /* MAL Transmit Slot */
  112. int tx_i_index; /* Transmit Interrupt Queue Index */
  113. int tx_u_index; /* Transmit User Queue Index */
  114. int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
  115. int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
  116. int is_receiving; /* sync with eth interrupt */
  117. int print_speed; /* print speed message upon start */
  118. EMAC_STATS_ST stats;
  119. } EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST;
  120. #if defined(CONFIG_440_GX)
  121. #define EMAC_NUM_DEV 4
  122. #elif defined(CONFIG_440) && !defined(CONFIG_440_GX)
  123. #define EMAC_NUM_DEV 2
  124. #else
  125. #warning Bad configuration
  126. #endif
  127. /*ZMII Bridge Register addresses */
  128. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  129. #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
  130. #else
  131. #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
  132. #endif
  133. #define ZMII_FER (ZMII_BASE)
  134. #define ZMII_SSR (ZMII_BASE + 4)
  135. #define ZMII_SMIISR (ZMII_BASE + 8)
  136. #define ZMII_RMII 0x22000000
  137. #define ZMII_MDI0 0x80000000
  138. /* ZMII FER Register Bit Definitions */
  139. #define ZMII_FER_MDI (0x8)
  140. #define ZMII_FER_SMII (0x4)
  141. #define ZMII_FER_RMII (0x2)
  142. #define ZMII_FER_MII (0x1)
  143. #define ZMII_FER_RSVD11 (0x00200000)
  144. #define ZMII_FER_RSVD10 (0x00100000)
  145. #define ZMII_FER_RSVD14_31 (0x0003FFFF)
  146. #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
  147. /* ZMII Speed Selection Register Bit Definitions */
  148. #define ZMII_SSR_SCI (0x4)
  149. #define ZMII_SSR_FSS (0x2)
  150. #define ZMII_SSR_SP (0x1)
  151. #define ZMII_SSR_RSVD16_31 (0x0000FFFF)
  152. #define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16)
  153. /* ZMII SMII Status Register Bit Definitions */
  154. #define ZMII_SMIISR_E1 (0x80)
  155. #define ZMII_SMIISR_EC (0x40)
  156. #define ZMII_SMIISR_EN (0x20)
  157. #define ZMII_SMIISR_EJ (0x10)
  158. #define ZMII_SMIISR_EL (0x08)
  159. #define ZMII_SMIISR_ED (0x04)
  160. #define ZMII_SMIISR_ES (0x02)
  161. #define ZMII_SMIISR_EF (0x01)
  162. #define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
  163. /* RGMII Register Addresses */
  164. #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
  165. #define RGMII_FER (RGMII_BASE + 0x00)
  166. #define RGMII_SSR (RGMII_BASE + 0x04)
  167. /* RGMII Function Enable (FER) Register Bit Definitions */
  168. /* Note: for EMAC 2 and 3 only, 440GX only */
  169. #define RGMII_FER_DIS (0x00)
  170. #define RGMII_FER_RTBI (0x04)
  171. #define RGMII_FER_RGMII (0x05)
  172. #define RGMII_FER_TBI (0x06)
  173. #define RGMII_FER_GMII (0x07)
  174. #define RGMII_FER_V(__x) ((__x - 2) * 4)
  175. /* RGMII Speed Selection Register Bit Definitions */
  176. #define RGMII_SSR_SP_10MBPS (0x00)
  177. #define RGMII_SSR_SP_100MBPS (0x02)
  178. #define RGMII_SSR_SP_1000MBPS (0x04)
  179. #define RGMII_SSR_V(__x) ((__x -2) * 8)
  180. /*---------------------------------------------------------------------------+
  181. | TCP/IP Acceleration Hardware (TAH) 440GX Only
  182. +---------------------------------------------------------------------------*/
  183. #if defined(CONFIG_440_GX)
  184. #define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
  185. #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
  186. #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
  187. #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
  188. #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
  189. #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
  190. #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
  191. #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
  192. #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
  193. #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
  194. /* TAH Revision */
  195. #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
  196. #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
  197. #define TAH_REV_RN_V (8)
  198. #define TAH_REV_BN_V (0)
  199. /* TAH Mode Register */
  200. #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
  201. #define TAH_MR_SR (0x40000000) /* Software reset */
  202. #define TAH_MR_ST (0x3F000000) /* Send Threshold */
  203. #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
  204. #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
  205. #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
  206. #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
  207. #define TAH_MR_ST_V (20)
  208. #define TAH_MR_TFS_V (17)
  209. #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
  210. #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
  211. #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
  212. #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
  213. #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
  214. /* TAH Segment Size Registers 0:5 */
  215. #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
  216. #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
  217. #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
  218. /* TAH Transmit Status Register */
  219. #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
  220. #define TAH_TSR_UH (0x40000000) /* Unrecognized header */
  221. #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
  222. #define TAH_TSR_IPOP (0x10000000) /* IP option present */
  223. #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
  224. #define TAH_TSR_ILTS (0x04000000) /* IP length too short */
  225. #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
  226. #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
  227. #define TAH_TSR_TFP (0x00800000) /* TCP flags present */
  228. #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
  229. #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
  230. #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
  231. #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
  232. #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
  233. #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
  234. #endif /* CONFIG_440_GX */
  235. /* Ethernet MAC Regsiter Addresses */
  236. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  237. #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
  238. #else
  239. #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
  240. #endif
  241. #define EMAC_M0 (EMAC_BASE)
  242. #define EMAC_M1 (EMAC_BASE + 4)
  243. #define EMAC_TXM0 (EMAC_BASE + 8)
  244. #define EMAC_TXM1 (EMAC_BASE + 12)
  245. #define EMAC_RXM (EMAC_BASE + 16)
  246. #define EMAC_ISR (EMAC_BASE + 20)
  247. #define EMAC_IER (EMAC_BASE + 24)
  248. #define EMAC_IAH (EMAC_BASE + 28)
  249. #define EMAC_IAL (EMAC_BASE + 32)
  250. #define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
  251. #define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
  252. #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
  253. #define EMAC_IND_HASH_1 (EMAC_BASE + 48)
  254. #define EMAC_IND_HASH_2 (EMAC_BASE + 52)
  255. #define EMAC_IND_HASH_3 (EMAC_BASE + 56)
  256. #define EMAC_IND_HASH_4 (EMAC_BASE + 60)
  257. #define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
  258. #define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
  259. #define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
  260. #define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
  261. #define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
  262. #define EMAC_LST_SRC_HI (EMAC_BASE + 84)
  263. #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
  264. #define EMAC_STACR (EMAC_BASE + 92)
  265. #define EMAC_TRTR (EMAC_BASE + 96)
  266. #define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
  267. /* bit definitions */
  268. /* MODE REG 0 */
  269. #define EMAC_M0_RXI (0x80000000)
  270. #define EMAC_M0_TXI (0x40000000)
  271. #define EMAC_M0_SRST (0x20000000)
  272. #define EMAC_M0_TXE (0x10000000)
  273. #define EMAC_M0_RXE (0x08000000)
  274. #define EMAC_M0_WKE (0x04000000)
  275. /* MODE Reg 1 */
  276. #define EMAC_M1_FDE (0x80000000)
  277. #define EMAC_M1_ILE (0x40000000)
  278. #define EMAC_M1_VLE (0x20000000)
  279. #define EMAC_M1_EIFC (0x10000000)
  280. #define EMAC_M1_APP (0x08000000)
  281. #define EMAC_M1_RSVD (0x06000000)
  282. #define EMAC_M1_IST (0x01000000)
  283. #define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
  284. #define EMAC_M1_MF_100MBPS (0x00400000)
  285. #define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */
  286. #define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */
  287. #define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */
  288. #define EMAC_M1_RFS_2K (0x00100000)
  289. #define EMAC_M1_RFS_1K (0x00080000)
  290. #define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */
  291. #define EMAC_M1_TX_FIFO_8K (0x00040000)
  292. #define EMAC_M1_TX_FIFO_4K (0x00030000)
  293. #define EMAC_M1_TX_FIFO_2K (0x00020000)
  294. #define EMAC_M1_TX_FIFO_1K (0x00010000)
  295. #define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
  296. #define EMAC_M1_MWSW (0x00007000)
  297. #define EMAC_M1_JUMBO_ENABLE (0x00000800)
  298. #define EMAC_M1_IPPA (0x000007c0)
  299. #define EMAC_M1_OBCI_GT100 (0x00000020)
  300. #define EMAC_M1_OBCI_100 (0x00000018)
  301. #define EMAC_M1_OBCI_83 (0x00000010)
  302. #define EMAC_M1_OBCI_66 (0x00000008)
  303. #define EMAC_M1_RSVD1 (0x00000007)
  304. /* Transmit Mode Register 0 */
  305. #define EMAC_TXM0_GNP0 (0x80000000)
  306. #define EMAC_TXM0_GNP1 (0x40000000)
  307. #define EMAC_TXM0_GNPD (0x20000000)
  308. #define EMAC_TXM0_FC (0x10000000)
  309. /* Receive Mode Register */
  310. #define EMAC_RMR_SP (0x80000000)
  311. #define EMAC_RMR_SFCS (0x40000000)
  312. #define EMAC_RMR_ARRP (0x20000000)
  313. #define EMAC_RMR_ARP (0x10000000)
  314. #define EMAC_RMR_AROP (0x08000000)
  315. #define EMAC_RMR_ARPI (0x04000000)
  316. #define EMAC_RMR_PPP (0x02000000)
  317. #define EMAC_RMR_PME (0x01000000)
  318. #define EMAC_RMR_PMME (0x00800000)
  319. #define EMAC_RMR_IAE (0x00400000)
  320. #define EMAC_RMR_MIAE (0x00200000)
  321. #define EMAC_RMR_BAE (0x00100000)
  322. #define EMAC_RMR_MAE (0x00080000)
  323. /* Interrupt Status & enable Regs */
  324. #define EMAC_ISR_OVR (0x02000000)
  325. #define EMAC_ISR_PP (0x01000000)
  326. #define EMAC_ISR_BP (0x00800000)
  327. #define EMAC_ISR_RP (0x00400000)
  328. #define EMAC_ISR_SE (0x00200000)
  329. #define EMAC_ISR_SYE (0x00100000)
  330. #define EMAC_ISR_BFCS (0x00080000)
  331. #define EMAC_ISR_PTLE (0x00040000)
  332. #define EMAC_ISR_ORE (0x00020000)
  333. #define EMAC_ISR_IRE (0x00010000)
  334. #define EMAC_ISR_DBDM (0x00000200)
  335. #define EMAC_ISR_DB0 (0x00000100)
  336. #define EMAC_ISR_SE0 (0x00000080)
  337. #define EMAC_ISR_TE0 (0x00000040)
  338. #define EMAC_ISR_DB1 (0x00000020)
  339. #define EMAC_ISR_SE1 (0x00000010)
  340. #define EMAC_ISR_TE1 (0x00000008)
  341. #define EMAC_ISR_MOS (0x00000002)
  342. #define EMAC_ISR_MOF (0x00000001)
  343. /* STA CONTROL REG */
  344. #define EMAC_STACR_OC (0x00008000)
  345. #define EMAC_STACR_PHYE (0x00004000)
  346. #define EMAC_STACR_WRITE (0x00002000)
  347. #define EMAC_STACR_READ (0x00001000)
  348. #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
  349. #define EMAC_STACR_CLK_66MHZ (0x00000400)
  350. #define EMAC_STACR_CLK_100MHZ (0x00000C00)
  351. /* Transmit Request Threshold Register */
  352. #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
  353. #define EMAC_TRTR_192 (0x10000000)
  354. #define EMAC_TRTR_128 (0x01000000)
  355. /* the follwing defines are for the MadMAL status and control registers. */
  356. /* For bits 0..5 look at the mal.h file */
  357. #define EMAC_TX_CTRL_GFCS (0x0200)
  358. #define EMAC_TX_CTRL_GP (0x0100)
  359. #define EMAC_TX_CTRL_ISA (0x0080)
  360. #define EMAC_TX_CTRL_RSA (0x0040)
  361. #define EMAC_TX_CTRL_IVT (0x0020)
  362. #define EMAC_TX_CTRL_RVT (0x0010)
  363. #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
  364. #define EMAC_TX_ST_BFCS (0x0200)
  365. #define EMAC_TX_ST_BPP (0x0100)
  366. #define EMAC_TX_ST_LCS (0x0080)
  367. #define EMAC_TX_ST_ED (0x0040)
  368. #define EMAC_TX_ST_EC (0x0020)
  369. #define EMAC_TX_ST_LC (0x0010)
  370. #define EMAC_TX_ST_MC (0x0008)
  371. #define EMAC_TX_ST_SC (0x0004)
  372. #define EMAC_TX_ST_UR (0x0002)
  373. #define EMAC_TX_ST_SQE (0x0001)
  374. #define EMAC_TX_ST_DEFAULT (0x03F3)
  375. /* madmal receive status / Control bits */
  376. #define EMAC_RX_ST_OE (0x0200)
  377. #define EMAC_RX_ST_PP (0x0100)
  378. #define EMAC_RX_ST_BP (0x0080)
  379. #define EMAC_RX_ST_RP (0x0040)
  380. #define EMAC_RX_ST_SE (0x0020)
  381. #define EMAC_RX_ST_AE (0x0010)
  382. #define EMAC_RX_ST_BFCS (0x0008)
  383. #define EMAC_RX_ST_PTL (0x0004)
  384. #define EMAC_RX_ST_ORE (0x0002)
  385. #define EMAC_RX_ST_IRE (0x0001)
  386. /* all the errors we care about */
  387. #define EMAC_RX_ERRORS (0x03FF)
  388. #endif /* CONFIG_440 */
  389. #endif /* _enetLib_h_ */