usb_ohci.c 43 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the PPC 440.
  3. *
  4. * (C) Copyright 2003-2004
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * (C) Copyright 2004
  8. * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
  9. *
  10. * Note: Much of this code has been derived from Linux 2.4
  11. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  12. * (C) Copyright 2000-2002 David Brownell
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - this driver is intended for use with USB Mass Storage Devices
  36. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  37. */
  38. #include <common.h>
  39. #ifdef CONFIG_USB_OHCI
  40. #include <malloc.h>
  41. #include <usb.h>
  42. #include "usb_ohci.h"
  43. #include "usbdev.h"
  44. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  45. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  46. #undef DEBUG
  47. #undef SHOW_INFO
  48. #undef OHCI_FILL_TRACE
  49. /* For initializing controller (mask in an HCFS mode too) */
  50. #define OHCI_CONTROL_INIT \
  51. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  52. #define readl(a) (*((vu_long *)(a)))
  53. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  54. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  55. #ifdef DEBUG
  56. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  57. #else
  58. #define dbg(format, arg...) do {} while(0)
  59. #endif /* DEBUG */
  60. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  61. #ifdef SHOW_INFO
  62. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  63. #else
  64. #define info(format, arg...) do {} while(0)
  65. #endif
  66. #define m16_swap(x) swap_16(x)
  67. #define m32_swap(x) swap_32(x)
  68. #if 1
  69. #define ohci_cpu_to_le16(x) (x)
  70. #define ohci_cpu_to_le32(x) (x)
  71. #else
  72. #define ohci_cpu_to_le16(x) swap_16(x)
  73. #define ohci_cpu_to_le32(x) swap_32(x)
  74. #endif
  75. /* global ohci_t */
  76. static ohci_t gohci;
  77. /* this must be aligned to a 256 byte boundary */
  78. struct ohci_hcca ghcca[1];
  79. /* a pointer to the aligned storage */
  80. struct ohci_hcca *phcca;
  81. /* this allocates EDs for all possible endpoints */
  82. struct ohci_device ohci_dev;
  83. /* urb_priv */
  84. urb_priv_t urb_priv;
  85. /* RHSC flag */
  86. int got_rhsc;
  87. /* device which was disconnected */
  88. struct usb_device *devgone;
  89. /*-------------------------------------------------------------------------*/
  90. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  91. * The erratum (#4) description is incorrect. AMD's workaround waits
  92. * till some bits (mostly reserved) are clear; ok for all revs.
  93. */
  94. #define OHCI_QUIRK_AMD756 0xabcd
  95. #define read_roothub(hc, register, mask) ({ \
  96. u32 temp = readl (&hc->regs->roothub.register); \
  97. if (hc->flags & OHCI_QUIRK_AMD756) \
  98. while (temp & mask) \
  99. temp = readl (&hc->regs->roothub.register); \
  100. temp; })
  101. static u32 roothub_a(struct ohci *hc)
  102. {
  103. return read_roothub(hc, a, 0xfc0fe000);
  104. }
  105. static inline u32 roothub_b(struct ohci *hc)
  106. {
  107. return readl(&hc->regs->roothub.b);
  108. }
  109. static inline u32 roothub_status(struct ohci *hc)
  110. {
  111. return readl(&hc->regs->roothub.status);
  112. }
  113. static u32 roothub_portstatus(struct ohci *hc, int i)
  114. {
  115. return read_roothub(hc, portstatus[i], 0xffe0fce0);
  116. }
  117. /* forward declaration */
  118. static int hc_interrupt(void);
  119. static void
  120. td_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  121. int transfer_len, struct devrequest *setup, urb_priv_t * urb,
  122. int interval);
  123. /*-------------------------------------------------------------------------*
  124. * URB support functions
  125. *-------------------------------------------------------------------------*/
  126. /* free HCD-private data associated with this URB */
  127. static void urb_free_priv(urb_priv_t * urb)
  128. {
  129. int i;
  130. int last;
  131. struct td *td;
  132. last = urb->length - 1;
  133. if (last >= 0) {
  134. for (i = 0; i <= last; i++) {
  135. td = urb->td[i];
  136. if (td) {
  137. td->usb_dev = NULL;
  138. urb->td[i] = NULL;
  139. }
  140. }
  141. }
  142. }
  143. /*-------------------------------------------------------------------------*/
  144. #ifdef DEBUG
  145. static int sohci_get_current_frame_number(struct usb_device *dev);
  146. /* debug| print the main components of an URB
  147. * small: 0) header + data packets 1) just header */
  148. static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
  149. int transfer_len, struct devrequest *setup, char *str,
  150. int small)
  151. {
  152. urb_priv_t *purb = &urb_priv;
  153. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  154. str,
  155. sohci_get_current_frame_number(dev),
  156. usb_pipedevice(pipe),
  157. usb_pipeendpoint(pipe),
  158. usb_pipeout(pipe) ? 'O' : 'I',
  159. usb_pipetype(pipe) < 2 ? (usb_pipeint(pipe) ? "INTR" : "ISOC") :
  160. (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
  161. purb->actual_length, transfer_len, dev->status);
  162. #ifdef OHCI_VERBOSE_DEBUG
  163. if (!small) {
  164. int i, len;
  165. if (usb_pipecontrol(pipe)) {
  166. printf(__FILE__ ": cmd(8):");
  167. for (i = 0; i < 8; i++)
  168. printf(" %02x", ((__u8 *) setup)[i]);
  169. printf("\n");
  170. }
  171. if (transfer_len > 0 && buffer) {
  172. printf(__FILE__ ": data(%d/%d):",
  173. purb->actual_length, transfer_len);
  174. len = usb_pipeout(pipe) ?
  175. transfer_len : purb->actual_length;
  176. for (i = 0; i < 16 && i < len; i++)
  177. printf(" %02x", ((__u8 *) buffer)[i]);
  178. printf("%s\n", i < len ? "..." : "");
  179. }
  180. }
  181. #endif
  182. }
  183. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  184. void ep_print_int_eds(ohci_t * ohci, char *str)
  185. {
  186. int i, j;
  187. __u32 *ed_p;
  188. for (i = 0; i < 32; i++) {
  189. j = 5;
  190. ed_p = &(ohci->hcca->int_table[i]);
  191. if (*ed_p == 0)
  192. continue;
  193. printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  194. while (*ed_p != 0 && j--) {
  195. ed_t *ed = (ed_t *) ohci_cpu_to_le32(ed_p);
  196. printf(" ed: %4x;", ed->hwINFO);
  197. ed_p = &ed->hwNextED;
  198. }
  199. printf("\n");
  200. }
  201. }
  202. static void ohci_dump_intr_mask(char *label, __u32 mask)
  203. {
  204. dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  205. label,
  206. mask,
  207. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  208. (mask & OHCI_INTR_OC) ? " OC" : "",
  209. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  210. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  211. (mask & OHCI_INTR_UE) ? " UE" : "",
  212. (mask & OHCI_INTR_RD) ? " RD" : "",
  213. (mask & OHCI_INTR_SF) ? " SF" : "",
  214. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  215. (mask & OHCI_INTR_SO) ? " SO" : "");
  216. }
  217. static void maybe_print_eds(char *label, __u32 value)
  218. {
  219. ed_t *edp = (ed_t *) value;
  220. if (value) {
  221. dbg("%s %08x", label, value);
  222. dbg("%08x", edp->hwINFO);
  223. dbg("%08x", edp->hwTailP);
  224. dbg("%08x", edp->hwHeadP);
  225. dbg("%08x", edp->hwNextED);
  226. }
  227. }
  228. static char *hcfs2string(int state)
  229. {
  230. switch (state) {
  231. case OHCI_USB_RESET:
  232. return "reset";
  233. case OHCI_USB_RESUME:
  234. return "resume";
  235. case OHCI_USB_OPER:
  236. return "operational";
  237. case OHCI_USB_SUSPEND:
  238. return "suspend";
  239. }
  240. return "?";
  241. }
  242. /* dump control and status registers */
  243. static void ohci_dump_status(ohci_t * controller)
  244. {
  245. struct ohci_regs *regs = controller->regs;
  246. __u32 temp;
  247. temp = readl(&regs->revision) & 0xff;
  248. if (temp != 0x10)
  249. dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
  250. temp = readl(&regs->control);
  251. dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  252. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  253. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  254. (temp & OHCI_CTRL_IR) ? " IR" : "",
  255. hcfs2string(temp & OHCI_CTRL_HCFS),
  256. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  257. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  258. (temp & OHCI_CTRL_IE) ? " IE" : "",
  259. (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
  260. temp = readl(&regs->cmdstatus);
  261. dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  262. (temp & OHCI_SOC) >> 16,
  263. (temp & OHCI_OCR) ? " OCR" : "",
  264. (temp & OHCI_BLF) ? " BLF" : "",
  265. (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
  266. ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
  267. ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
  268. maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
  269. maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
  270. maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
  271. maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
  272. maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
  273. maybe_print_eds("donehead", readl(&regs->donehead));
  274. }
  275. static void ohci_dump_roothub(ohci_t * controller, int verbose)
  276. {
  277. __u32 temp, ndp, i;
  278. temp = roothub_a(controller);
  279. ndp = (temp & RH_A_NDP);
  280. if (verbose) {
  281. dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  282. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  283. (temp & RH_A_NOCP) ? " NOCP" : "",
  284. (temp & RH_A_OCPM) ? " OCPM" : "",
  285. (temp & RH_A_DT) ? " DT" : "",
  286. (temp & RH_A_NPS) ? " NPS" : "",
  287. (temp & RH_A_PSM) ? " PSM" : "", ndp);
  288. temp = roothub_b(controller);
  289. dbg("roothub.b: %08x PPCM=%04x DR=%04x",
  290. temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
  291. );
  292. temp = roothub_status(controller);
  293. dbg("roothub.status: %08x%s%s%s%s%s%s",
  294. temp,
  295. (temp & RH_HS_CRWE) ? " CRWE" : "",
  296. (temp & RH_HS_OCIC) ? " OCIC" : "",
  297. (temp & RH_HS_LPSC) ? " LPSC" : "",
  298. (temp & RH_HS_DRWE) ? " DRWE" : "",
  299. (temp & RH_HS_OCI) ? " OCI" : "",
  300. (temp & RH_HS_LPS) ? " LPS" : "");
  301. }
  302. for (i = 0; i < ndp; i++) {
  303. temp = roothub_portstatus(controller, i);
  304. dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  305. i,
  306. temp,
  307. (temp & RH_PS_PRSC) ? " PRSC" : "",
  308. (temp & RH_PS_OCIC) ? " OCIC" : "",
  309. (temp & RH_PS_PSSC) ? " PSSC" : "",
  310. (temp & RH_PS_PESC) ? " PESC" : "",
  311. (temp & RH_PS_CSC) ? " CSC" : "",
  312. (temp & RH_PS_LSDA) ? " LSDA" : "",
  313. (temp & RH_PS_PPS) ? " PPS" : "",
  314. (temp & RH_PS_PRS) ? " PRS" : "",
  315. (temp & RH_PS_POCI) ? " POCI" : "",
  316. (temp & RH_PS_PSS) ? " PSS" : "",
  317. (temp & RH_PS_PES) ? " PES" : "",
  318. (temp & RH_PS_CCS) ? " CCS" : "");
  319. }
  320. }
  321. static void ohci_dump(ohci_t * controller, int verbose)
  322. {
  323. dbg("OHCI controller usb-%s state", controller->slot_name);
  324. /* dumps some of the state we know about */
  325. ohci_dump_status(controller);
  326. if (verbose)
  327. ep_print_int_eds(controller, "hcca");
  328. dbg("hcca frame #%04x", controller->hcca->frame_no);
  329. ohci_dump_roothub(controller, 1);
  330. }
  331. #endif /* DEBUG */
  332. /*-------------------------------------------------------------------------*
  333. * Interface functions (URB)
  334. *-------------------------------------------------------------------------*/
  335. /* get a transfer request */
  336. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  337. int transfer_len, struct devrequest *setup, int interval)
  338. {
  339. ohci_t *ohci;
  340. ed_t *ed;
  341. urb_priv_t *purb_priv;
  342. int i, size = 0;
  343. ohci = &gohci;
  344. /* when controller's hung, permit only roothub cleanup attempts
  345. * such as powering down ports */
  346. if (ohci->disabled) {
  347. err("sohci_submit_job: EPIPE");
  348. return -1;
  349. }
  350. /* every endpoint has a ed, locate and fill it */
  351. if (!(ed = ep_add_ed(dev, pipe))) {
  352. err("sohci_submit_job: ENOMEM");
  353. return -1;
  354. }
  355. /* for the private part of the URB we need the number of TDs (size) */
  356. switch (usb_pipetype(pipe)) {
  357. case PIPE_BULK: /* one TD for every 4096 Byte */
  358. size = (transfer_len - 1) / 4096 + 1;
  359. break;
  360. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  361. size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
  362. break;
  363. }
  364. if (size >= (N_URB_TD - 1)) {
  365. err("need %d TDs, only have %d", size, N_URB_TD);
  366. return -1;
  367. }
  368. purb_priv = &urb_priv;
  369. purb_priv->pipe = pipe;
  370. /* fill the private part of the URB */
  371. purb_priv->length = size;
  372. purb_priv->ed = ed;
  373. purb_priv->actual_length = 0;
  374. /* allocate the TDs */
  375. /* note that td[0] was allocated in ep_add_ed */
  376. for (i = 0; i < size; i++) {
  377. purb_priv->td[i] = td_alloc(dev);
  378. if (!purb_priv->td[i]) {
  379. purb_priv->length = i;
  380. urb_free_priv(purb_priv);
  381. err("sohci_submit_job: ENOMEM");
  382. return -1;
  383. }
  384. }
  385. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  386. urb_free_priv(purb_priv);
  387. err("sohci_submit_job: EINVAL");
  388. return -1;
  389. }
  390. /* link the ed into a chain if is not already */
  391. if (ed->state != ED_OPER)
  392. ep_link(ohci, ed);
  393. /* fill the TDs and link it to the ed */
  394. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
  395. interval);
  396. return 0;
  397. }
  398. /*-------------------------------------------------------------------------*/
  399. #ifdef DEBUG
  400. /* tell us the current USB frame number */
  401. static int sohci_get_current_frame_number(struct usb_device *usb_dev)
  402. {
  403. ohci_t *ohci = &gohci;
  404. return ohci_cpu_to_le16(ohci->hcca->frame_no);
  405. }
  406. #endif
  407. /*-------------------------------------------------------------------------*
  408. * ED handling functions
  409. *-------------------------------------------------------------------------*/
  410. /* link an ed into one of the HC chains */
  411. static int ep_link(ohci_t * ohci, ed_t * edi)
  412. {
  413. volatile ed_t *ed = edi;
  414. ed->state = ED_OPER;
  415. switch (ed->type) {
  416. case PIPE_CONTROL:
  417. ed->hwNextED = 0;
  418. if (ohci->ed_controltail == NULL) {
  419. writel(ed, &ohci->regs->ed_controlhead);
  420. } else {
  421. ohci->ed_controltail->hwNextED =
  422. ohci_cpu_to_le32((unsigned long)ed);
  423. }
  424. ed->ed_prev = ohci->ed_controltail;
  425. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  426. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  427. ohci->hc_control |= OHCI_CTRL_CLE;
  428. writel(ohci->hc_control, &ohci->regs->control);
  429. }
  430. ohci->ed_controltail = edi;
  431. break;
  432. case PIPE_BULK:
  433. ed->hwNextED = 0;
  434. if (ohci->ed_bulktail == NULL) {
  435. writel(ed, &ohci->regs->ed_bulkhead);
  436. } else {
  437. ohci->ed_bulktail->hwNextED =
  438. ohci_cpu_to_le32((unsigned long)ed);
  439. }
  440. ed->ed_prev = ohci->ed_bulktail;
  441. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  442. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  443. ohci->hc_control |= OHCI_CTRL_BLE;
  444. writel(ohci->hc_control, &ohci->regs->control);
  445. }
  446. ohci->ed_bulktail = edi;
  447. break;
  448. }
  449. return 0;
  450. }
  451. /*-------------------------------------------------------------------------*/
  452. /* unlink an ed from one of the HC chains.
  453. * just the link to the ed is unlinked.
  454. * the link from the ed still points to another operational ed or 0
  455. * so the HC can eventually finish the processing of the unlinked ed */
  456. static int ep_unlink(ohci_t * ohci, ed_t * edi)
  457. {
  458. volatile ed_t *ed = edi;
  459. ed->hwINFO |= ohci_cpu_to_le32(OHCI_ED_SKIP);
  460. switch (ed->type) {
  461. case PIPE_CONTROL:
  462. if (ed->ed_prev == NULL) {
  463. if (!ed->hwNextED) {
  464. ohci->hc_control &= ~OHCI_CTRL_CLE;
  465. writel(ohci->hc_control, &ohci->regs->control);
  466. }
  467. writel(ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)),
  468. &ohci->regs->ed_controlhead);
  469. } else {
  470. ed->ed_prev->hwNextED = ed->hwNextED;
  471. }
  472. if (ohci->ed_controltail == ed) {
  473. ohci->ed_controltail = ed->ed_prev;
  474. } else {
  475. ((ed_t *)
  476. ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)))->
  477. ed_prev = ed->ed_prev;
  478. }
  479. break;
  480. case PIPE_BULK:
  481. if (ed->ed_prev == NULL) {
  482. if (!ed->hwNextED) {
  483. ohci->hc_control &= ~OHCI_CTRL_BLE;
  484. writel(ohci->hc_control, &ohci->regs->control);
  485. }
  486. writel(ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)),
  487. &ohci->regs->ed_bulkhead);
  488. } else {
  489. ed->ed_prev->hwNextED = ed->hwNextED;
  490. }
  491. if (ohci->ed_bulktail == ed) {
  492. ohci->ed_bulktail = ed->ed_prev;
  493. } else {
  494. ((ed_t *)
  495. ohci_cpu_to_le32(*((__u32 *) & ed->hwNextED)))->
  496. ed_prev = ed->ed_prev;
  497. }
  498. break;
  499. }
  500. ed->state = ED_UNLINK;
  501. return 0;
  502. }
  503. /*-------------------------------------------------------------------------*/
  504. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  505. * but the USB stack is a little bit stateless so we do it at every transaction
  506. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  507. * in all other cases the state is left unchanged
  508. * the ed info fields are setted anyway even though most of them should not change */
  509. static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
  510. {
  511. td_t *td;
  512. ed_t *ed_ret;
  513. volatile ed_t *ed;
  514. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
  515. (usb_pipecontrol(pipe) ? 0 :
  516. usb_pipeout(pipe))];
  517. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  518. err("ep_add_ed: pending delete");
  519. /* pending delete request */
  520. return NULL;
  521. }
  522. if (ed->state == ED_NEW) {
  523. ed->hwINFO = ohci_cpu_to_le32(OHCI_ED_SKIP); /* skip ed */
  524. /* dummy td; end of td list for ed */
  525. td = td_alloc(usb_dev);
  526. ed->hwTailP = ohci_cpu_to_le32((unsigned long)td);
  527. ed->hwHeadP = ed->hwTailP;
  528. ed->state = ED_UNLINK;
  529. ed->type = usb_pipetype(pipe);
  530. ohci_dev.ed_cnt++;
  531. }
  532. ed->hwINFO = ohci_cpu_to_le32(usb_pipedevice(pipe)
  533. | usb_pipeendpoint(pipe) << 7
  534. | (usb_pipeisoc(pipe) ? 0x8000 : 0)
  535. | (usb_pipecontrol(pipe) ? 0
  536. : (usb_pipeout(pipe) ? 0x800 : 0x1000))
  537. | usb_pipeslow(pipe) << 13 |
  538. usb_maxpacket(usb_dev, pipe) << 16);
  539. return ed_ret;
  540. }
  541. /*-------------------------------------------------------------------------*
  542. * TD handling functions
  543. *-------------------------------------------------------------------------*/
  544. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  545. static void td_fill(ohci_t * ohci, unsigned int info,
  546. void *data, int len,
  547. struct usb_device *dev, int index, urb_priv_t * urb_priv)
  548. {
  549. volatile td_t *td, *td_pt;
  550. #ifdef OHCI_FILL_TRACE
  551. int i;
  552. #endif
  553. if (index > urb_priv->length) {
  554. err("index > length");
  555. return;
  556. }
  557. /* use this td as the next dummy */
  558. td_pt = urb_priv->td[index];
  559. td_pt->hwNextTD = 0;
  560. /* fill the old dummy TD */
  561. td = urb_priv->td[index] =
  562. (td_t *) (ohci_cpu_to_le32(urb_priv->ed->hwTailP) & ~0xf);
  563. td->ed = urb_priv->ed;
  564. td->next_dl_td = NULL;
  565. td->index = index;
  566. td->data = (__u32) data;
  567. #ifdef OHCI_FILL_TRACE
  568. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK)
  569. && usb_pipeout(urb_priv->pipe)) {
  570. for (i = 0; i < len; i++)
  571. printf("td->data[%d] %#2x ", i,
  572. ((unsigned char *)td->data)[i]);
  573. printf("\n");
  574. }
  575. #endif
  576. if (!len)
  577. data = 0;
  578. td->hwINFO = ohci_cpu_to_le32(info);
  579. td->hwCBP = ohci_cpu_to_le32((unsigned long)data);
  580. if (data)
  581. td->hwBE = ohci_cpu_to_le32((unsigned long)(data + len - 1));
  582. else
  583. td->hwBE = 0;
  584. td->hwNextTD = ohci_cpu_to_le32((unsigned long)td_pt);
  585. td->hwPSW[0] = ohci_cpu_to_le16(((__u32) data & 0x0FFF) | 0xE000);
  586. /* append to queue */
  587. td->ed->hwTailP = td->hwNextTD;
  588. }
  589. /*-------------------------------------------------------------------------*/
  590. /* prepare all TDs of a transfer */
  591. static void td_submit_job(struct usb_device *dev, unsigned long pipe,
  592. void *buffer, int transfer_len,
  593. struct devrequest *setup, urb_priv_t * urb,
  594. int interval)
  595. {
  596. ohci_t *ohci = &gohci;
  597. int data_len = transfer_len;
  598. void *data;
  599. int cnt = 0;
  600. __u32 info = 0;
  601. unsigned int toggle = 0;
  602. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  603. if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  604. toggle = TD_T_TOGGLE;
  605. } else {
  606. toggle = TD_T_DATA0;
  607. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
  608. 1);
  609. }
  610. urb->td_cnt = 0;
  611. if (data_len)
  612. data = buffer;
  613. else
  614. data = 0;
  615. switch (usb_pipetype(pipe)) {
  616. case PIPE_BULK:
  617. info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
  618. while (data_len > 4096) {
  619. td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
  620. 4096, dev, cnt, urb);
  621. data += 4096;
  622. data_len -= 4096;
  623. cnt++;
  624. }
  625. info = usb_pipeout(pipe) ?
  626. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN;
  627. td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
  628. data_len, dev, cnt, urb);
  629. cnt++;
  630. if (!ohci->sleeping)
  631. writel(OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  632. break;
  633. case PIPE_CONTROL:
  634. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  635. td_fill(ohci, info, setup, 8, dev, cnt++, urb);
  636. if (data_len > 0) {
  637. info = usb_pipeout(pipe) ?
  638. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R
  639. | TD_DP_IN | TD_T_DATA1;
  640. /* NOTE: mishandles transfers >8K, some >4K */
  641. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  642. }
  643. info = usb_pipeout(pipe) ?
  644. TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT |
  645. TD_T_DATA1;
  646. td_fill(ohci, info, data, 0, dev, cnt++, urb);
  647. if (!ohci->sleeping)
  648. writel(OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  649. break;
  650. }
  651. if (urb->length != cnt)
  652. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  653. }
  654. /*-------------------------------------------------------------------------*
  655. * Done List handling functions
  656. *-------------------------------------------------------------------------*/
  657. /* calculate the transfer length and update the urb */
  658. static void dl_transfer_length(td_t * td)
  659. {
  660. __u32 tdINFO, tdBE, tdCBP;
  661. urb_priv_t *lurb_priv = &urb_priv;
  662. tdINFO = ohci_cpu_to_le32(td->hwINFO);
  663. tdBE = ohci_cpu_to_le32(td->hwBE);
  664. tdCBP = ohci_cpu_to_le32(td->hwCBP);
  665. if (!(usb_pipetype(lurb_priv->pipe) == PIPE_CONTROL &&
  666. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  667. if (tdBE != 0) {
  668. if (td->hwCBP == 0)
  669. lurb_priv->actual_length += tdBE - td->data + 1;
  670. else
  671. lurb_priv->actual_length += tdCBP - td->data;
  672. }
  673. }
  674. }
  675. /*-------------------------------------------------------------------------*/
  676. /* replies to the request have to be on a FIFO basis so
  677. * we reverse the reversed done-list */
  678. static td_t *dl_reverse_done_list(ohci_t * ohci)
  679. {
  680. __u32 td_list_hc;
  681. td_t *td_rev = NULL;
  682. td_t *td_list = NULL;
  683. urb_priv_t *lurb_priv = NULL;
  684. td_list_hc = ohci_cpu_to_le32(ohci->hcca->done_head) & 0xfffffff0;
  685. ohci->hcca->done_head = 0;
  686. while (td_list_hc) {
  687. td_list = (td_t *) td_list_hc;
  688. if (TD_CC_GET(ohci_cpu_to_le32(td_list->hwINFO))) {
  689. lurb_priv = &urb_priv;
  690. dbg(" USB-error/status: %x : %p",
  691. TD_CC_GET(ohci_cpu_to_le32(td_list->hwINFO)),
  692. td_list);
  693. if (td_list->ed->hwHeadP & ohci_cpu_to_le32(0x1)) {
  694. if (lurb_priv
  695. && ((td_list->index + 1) <
  696. lurb_priv->length)) {
  697. td_list->ed->hwHeadP =
  698. (lurb_priv->
  699. td[lurb_priv->length -
  700. 1]->
  701. hwNextTD &
  702. ohci_cpu_to_le32(0xfffffff0)) |
  703. (td_list->ed->
  704. hwHeadP & ohci_cpu_to_le32(0x2));
  705. lurb_priv->td_cnt +=
  706. lurb_priv->length - td_list->index -
  707. 1;
  708. } else
  709. td_list->ed->hwHeadP &=
  710. ohci_cpu_to_le32(0xfffffff2);
  711. }
  712. #ifdef CONFIG_MPC5200
  713. td_list->hwNextTD = 0;
  714. #endif
  715. }
  716. td_list->next_dl_td = td_rev;
  717. td_rev = td_list;
  718. td_list_hc = ohci_cpu_to_le32(td_list->hwNextTD) & 0xfffffff0;
  719. }
  720. return td_list;
  721. }
  722. /*-------------------------------------------------------------------------*/
  723. /* td done list */
  724. static int dl_done_list(ohci_t * ohci, td_t * td_list)
  725. {
  726. td_t *td_list_next = NULL;
  727. ed_t *ed;
  728. int cc = 0;
  729. int stat = 0xff;
  730. /* urb_t *urb; */
  731. urb_priv_t *lurb_priv;
  732. __u32 tdINFO, edHeadP, edTailP;
  733. while (td_list) {
  734. td_list_next = td_list->next_dl_td;
  735. lurb_priv = &urb_priv;
  736. tdINFO = ohci_cpu_to_le32(td_list->hwINFO);
  737. ed = td_list->ed;
  738. dl_transfer_length(td_list);
  739. /* error code of transfer */
  740. cc = TD_CC_GET(tdINFO);
  741. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  742. if ((ed->state & (ED_OPER | ED_UNLINK))
  743. && (lurb_priv->state != URB_DEL)) {
  744. dbg("ConditionCode %#x", cc);
  745. stat = cc_to_error[cc];
  746. }
  747. }
  748. if (ed->state != ED_NEW) {
  749. edHeadP = ohci_cpu_to_le32(ed->hwHeadP) & 0xfffffff0;
  750. edTailP = ohci_cpu_to_le32(ed->hwTailP);
  751. /* unlink eds if they are not busy */
  752. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  753. ep_unlink(ohci, ed);
  754. }
  755. td_list = td_list_next;
  756. }
  757. return stat;
  758. }
  759. /*-------------------------------------------------------------------------*
  760. * Virtual Root Hub
  761. *-------------------------------------------------------------------------*/
  762. /* Device descriptor */
  763. static __u8 root_hub_dev_des[] = {
  764. 0x12, /* __u8 bLength; */
  765. 0x01, /* __u8 bDescriptorType; Device */
  766. 0x10, /* __u16 bcdUSB; v1.1 */
  767. 0x01,
  768. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  769. 0x00, /* __u8 bDeviceSubClass; */
  770. 0x00, /* __u8 bDeviceProtocol; */
  771. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  772. 0x00, /* __u16 idVendor; */
  773. 0x00,
  774. 0x00, /* __u16 idProduct; */
  775. 0x00,
  776. 0x00, /* __u16 bcdDevice; */
  777. 0x00,
  778. 0x00, /* __u8 iManufacturer; */
  779. 0x01, /* __u8 iProduct; */
  780. 0x00, /* __u8 iSerialNumber; */
  781. 0x01 /* __u8 bNumConfigurations; */
  782. };
  783. /* Configuration descriptor */
  784. static __u8 root_hub_config_des[] = {
  785. 0x09, /* __u8 bLength; */
  786. 0x02, /* __u8 bDescriptorType; Configuration */
  787. 0x19, /* __u16 wTotalLength; */
  788. 0x00,
  789. 0x01, /* __u8 bNumInterfaces; */
  790. 0x01, /* __u8 bConfigurationValue; */
  791. 0x00, /* __u8 iConfiguration; */
  792. 0x40, /* __u8 bmAttributes;
  793. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  794. 0x00, /* __u8 MaxPower; */
  795. /* interface */
  796. 0x09, /* __u8 if_bLength; */
  797. 0x04, /* __u8 if_bDescriptorType; Interface */
  798. 0x00, /* __u8 if_bInterfaceNumber; */
  799. 0x00, /* __u8 if_bAlternateSetting; */
  800. 0x01, /* __u8 if_bNumEndpoints; */
  801. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  802. 0x00, /* __u8 if_bInterfaceSubClass; */
  803. 0x00, /* __u8 if_bInterfaceProtocol; */
  804. 0x00, /* __u8 if_iInterface; */
  805. /* endpoint */
  806. 0x07, /* __u8 ep_bLength; */
  807. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  808. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  809. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  810. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  811. 0x00,
  812. 0xff /* __u8 ep_bInterval; 255 ms */
  813. };
  814. static unsigned char root_hub_str_index0[] = {
  815. 0x04, /* __u8 bLength; */
  816. 0x03, /* __u8 bDescriptorType; String-descriptor */
  817. 0x09, /* __u8 lang ID */
  818. 0x04, /* __u8 lang ID */
  819. };
  820. static unsigned char root_hub_str_index1[] = {
  821. 28, /* __u8 bLength; */
  822. 0x03, /* __u8 bDescriptorType; String-descriptor */
  823. 'O', /* __u8 Unicode */
  824. 0, /* __u8 Unicode */
  825. 'H', /* __u8 Unicode */
  826. 0, /* __u8 Unicode */
  827. 'C', /* __u8 Unicode */
  828. 0, /* __u8 Unicode */
  829. 'I', /* __u8 Unicode */
  830. 0, /* __u8 Unicode */
  831. ' ', /* __u8 Unicode */
  832. 0, /* __u8 Unicode */
  833. 'R', /* __u8 Unicode */
  834. 0, /* __u8 Unicode */
  835. 'o', /* __u8 Unicode */
  836. 0, /* __u8 Unicode */
  837. 'o', /* __u8 Unicode */
  838. 0, /* __u8 Unicode */
  839. 't', /* __u8 Unicode */
  840. 0, /* __u8 Unicode */
  841. ' ', /* __u8 Unicode */
  842. 0, /* __u8 Unicode */
  843. 'H', /* __u8 Unicode */
  844. 0, /* __u8 Unicode */
  845. 'u', /* __u8 Unicode */
  846. 0, /* __u8 Unicode */
  847. 'b', /* __u8 Unicode */
  848. 0, /* __u8 Unicode */
  849. };
  850. /* Hub class-specific descriptor is constructed dynamically */
  851. /*-------------------------------------------------------------------------*/
  852. #define OK(x) len = (x); break
  853. #ifdef DEBUG
  854. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  855. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  856. #else
  857. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  858. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  859. #endif
  860. #define RD_RH_STAT roothub_status(&gohci)
  861. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  862. /* request to virtual root hub */
  863. int rh_check_port_status(ohci_t * controller)
  864. {
  865. __u32 temp, ndp, i;
  866. int res;
  867. res = -1;
  868. temp = roothub_a(controller);
  869. ndp = (temp & RH_A_NDP);
  870. for (i = 0; i < ndp; i++) {
  871. temp = roothub_portstatus(controller, i);
  872. /* check for a device disconnect */
  873. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  874. (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
  875. res = i;
  876. break;
  877. }
  878. }
  879. return res;
  880. }
  881. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  882. void *buffer, int transfer_len,
  883. struct devrequest *cmd)
  884. {
  885. void *data = buffer;
  886. int leni = transfer_len;
  887. int len = 0;
  888. int stat = 0;
  889. __u32 datab[4];
  890. __u8 *data_buf = (__u8 *) datab;
  891. __u16 bmRType_bReq;
  892. __u16 wValue;
  893. __u16 wIndex;
  894. __u16 wLength;
  895. #ifdef DEBUG
  896. urb_priv.actual_length = 0;
  897. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
  898. usb_pipein(pipe));
  899. #endif
  900. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  901. info("Root-Hub submit IRQ: NOT implemented");
  902. return 0;
  903. }
  904. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  905. wValue = m16_swap(cmd->value);
  906. wIndex = m16_swap(cmd->index);
  907. wLength = m16_swap(cmd->length);
  908. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  909. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  910. switch (bmRType_bReq) {
  911. /* Request Destination:
  912. without flags: Device,
  913. RH_INTERFACE: interface,
  914. RH_ENDPOINT: endpoint,
  915. RH_CLASS means HUB here,
  916. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  917. */
  918. case RH_GET_STATUS:
  919. *(__u16 *) data_buf = m16_swap(1);
  920. OK(2);
  921. case RH_GET_STATUS | RH_INTERFACE:
  922. *(__u16 *) data_buf = m16_swap(0);
  923. OK(2);
  924. case RH_GET_STATUS | RH_ENDPOINT:
  925. *(__u16 *) data_buf = m16_swap(0);
  926. OK(2);
  927. case RH_GET_STATUS | RH_CLASS:
  928. *(__u32 *) data_buf =
  929. m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  930. OK(4);
  931. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  932. *(__u32 *) data_buf = m32_swap(RD_RH_PORTSTAT);
  933. OK(4);
  934. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  935. switch (wValue) {
  936. case (RH_ENDPOINT_STALL):
  937. OK(0);
  938. }
  939. break;
  940. case RH_CLEAR_FEATURE | RH_CLASS:
  941. switch (wValue) {
  942. case RH_C_HUB_LOCAL_POWER:
  943. OK(0);
  944. case (RH_C_HUB_OVER_CURRENT):
  945. WR_RH_STAT(RH_HS_OCIC);
  946. OK(0);
  947. }
  948. break;
  949. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  950. switch (wValue) {
  951. case (RH_PORT_ENABLE):
  952. WR_RH_PORTSTAT(RH_PS_CCS);
  953. OK(0);
  954. case (RH_PORT_SUSPEND):
  955. WR_RH_PORTSTAT(RH_PS_POCI);
  956. OK(0);
  957. case (RH_PORT_POWER):
  958. WR_RH_PORTSTAT(RH_PS_LSDA);
  959. OK(0);
  960. case (RH_C_PORT_CONNECTION):
  961. WR_RH_PORTSTAT(RH_PS_CSC);
  962. OK(0);
  963. case (RH_C_PORT_ENABLE):
  964. WR_RH_PORTSTAT(RH_PS_PESC);
  965. OK(0);
  966. case (RH_C_PORT_SUSPEND):
  967. WR_RH_PORTSTAT(RH_PS_PSSC);
  968. OK(0);
  969. case (RH_C_PORT_OVER_CURRENT):
  970. WR_RH_PORTSTAT(RH_PS_OCIC);
  971. OK(0);
  972. case (RH_C_PORT_RESET):
  973. WR_RH_PORTSTAT(RH_PS_PRSC);
  974. OK(0);
  975. }
  976. break;
  977. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  978. switch (wValue) {
  979. case (RH_PORT_SUSPEND):
  980. WR_RH_PORTSTAT(RH_PS_PSS);
  981. OK(0);
  982. case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
  983. if (RD_RH_PORTSTAT & RH_PS_CCS)
  984. WR_RH_PORTSTAT(RH_PS_PRS);
  985. OK(0);
  986. case (RH_PORT_POWER):
  987. WR_RH_PORTSTAT(RH_PS_PPS);
  988. OK(0);
  989. case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
  990. if (RD_RH_PORTSTAT & RH_PS_CCS)
  991. WR_RH_PORTSTAT(RH_PS_PES);
  992. OK(0);
  993. }
  994. break;
  995. case RH_SET_ADDRESS:
  996. gohci.rh.devnum = wValue;
  997. OK(0);
  998. case RH_GET_DESCRIPTOR:
  999. switch ((wValue & 0xff00) >> 8) {
  1000. case (0x01): /* device descriptor */
  1001. len = min_t(unsigned int,
  1002. leni,
  1003. min_t(unsigned int,
  1004. sizeof(root_hub_dev_des), wLength));
  1005. data_buf = root_hub_dev_des;
  1006. OK(len);
  1007. case (0x02): /* configuration descriptor */
  1008. len = min_t(unsigned int,
  1009. leni,
  1010. min_t(unsigned int,
  1011. sizeof(root_hub_config_des),
  1012. wLength));
  1013. data_buf = root_hub_config_des;
  1014. OK(len);
  1015. case (0x03): /* string descriptors */
  1016. if (wValue == 0x0300) {
  1017. len = min_t(unsigned int,
  1018. leni,
  1019. min_t(unsigned int,
  1020. sizeof(root_hub_str_index0),
  1021. wLength));
  1022. data_buf = root_hub_str_index0;
  1023. OK(len);
  1024. }
  1025. if (wValue == 0x0301) {
  1026. len = min_t(unsigned int,
  1027. leni,
  1028. min_t(unsigned int,
  1029. sizeof(root_hub_str_index1),
  1030. wLength));
  1031. data_buf = root_hub_str_index1;
  1032. OK(len);
  1033. }
  1034. default:
  1035. stat = USB_ST_STALLED;
  1036. }
  1037. break;
  1038. case RH_GET_DESCRIPTOR | RH_CLASS:
  1039. {
  1040. __u32 temp = roothub_a(&gohci);
  1041. data_buf[0] = 9; /* min length; */
  1042. data_buf[1] = 0x29;
  1043. data_buf[2] = temp & RH_A_NDP;
  1044. data_buf[3] = 0;
  1045. if (temp & RH_A_PSM) /* per-port power switching? */
  1046. data_buf[3] |= 0x1;
  1047. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1048. data_buf[3] |= 0x10;
  1049. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1050. data_buf[3] |= 0x8;
  1051. /* corresponds to data_buf[4-7] */
  1052. datab[1] = 0;
  1053. data_buf[5] = (temp & RH_A_POTPGT) >> 24;
  1054. temp = roothub_b(&gohci);
  1055. data_buf[7] = temp & RH_B_DR;
  1056. if (data_buf[2] < 7) {
  1057. data_buf[8] = 0xff;
  1058. } else {
  1059. data_buf[0] += 2;
  1060. data_buf[8] = (temp & RH_B_DR) >> 8;
  1061. data_buf[10] = data_buf[9] = 0xff;
  1062. }
  1063. len = min_t(unsigned int, leni,
  1064. min_t(unsigned int, data_buf[0], wLength));
  1065. OK(len);
  1066. }
  1067. case RH_GET_CONFIGURATION:
  1068. *(__u8 *) data_buf = 0x01;
  1069. OK(1);
  1070. case RH_SET_CONFIGURATION:
  1071. WR_RH_STAT(0x10000);
  1072. OK(0);
  1073. default:
  1074. dbg("unsupported root hub command");
  1075. stat = USB_ST_STALLED;
  1076. }
  1077. #ifdef DEBUG
  1078. ohci_dump_roothub(&gohci, 1);
  1079. #endif
  1080. len = min_t(int, len, leni);
  1081. if (data != data_buf)
  1082. memcpy(data, data_buf, len);
  1083. dev->act_len = len;
  1084. dev->status = stat;
  1085. #ifdef DEBUG
  1086. if (transfer_len)
  1087. urb_priv.actual_length = transfer_len;
  1088. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
  1089. 0 /*usb_pipein(pipe) */ );
  1090. #endif
  1091. return stat;
  1092. }
  1093. /*-------------------------------------------------------------------------*/
  1094. /* common code for handling submit messages - used for all but root hub */
  1095. /* accesses. */
  1096. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1097. int transfer_len, struct devrequest *setup, int interval)
  1098. {
  1099. int stat = 0;
  1100. int maxsize = usb_maxpacket(dev, pipe);
  1101. int timeout;
  1102. /* device pulled? Shortcut the action. */
  1103. if (devgone == dev) {
  1104. dev->status = USB_ST_CRC_ERR;
  1105. return 0;
  1106. }
  1107. #ifdef DEBUG
  1108. urb_priv.actual_length = 0;
  1109. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
  1110. usb_pipein(pipe));
  1111. #endif
  1112. if (!maxsize) {
  1113. err("submit_common_message: pipesize for pipe %lx is zero",
  1114. pipe);
  1115. return -1;
  1116. }
  1117. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
  1118. 0) {
  1119. err("sohci_submit_job failed");
  1120. return -1;
  1121. }
  1122. /* allow more time for a BULK device to react - some are slow */
  1123. #define BULK_TO 5000 /* timeout in milliseconds */
  1124. if (usb_pipetype(pipe) == PIPE_BULK)
  1125. timeout = BULK_TO;
  1126. else
  1127. timeout = 100;
  1128. /* wait for it to complete */
  1129. for (;;) {
  1130. /* check whether the controller is done */
  1131. stat = hc_interrupt();
  1132. if (stat < 0) {
  1133. stat = USB_ST_CRC_ERR;
  1134. break;
  1135. }
  1136. if (stat >= 0 && stat < 0xff) {
  1137. /* 0xff is returned for an SF-interrupt */
  1138. break;
  1139. }
  1140. if (--timeout) {
  1141. wait_ms(1);
  1142. } else {
  1143. err("CTL:TIMEOUT ");
  1144. stat = USB_ST_CRC_ERR;
  1145. break;
  1146. }
  1147. }
  1148. /* we got an Root Hub Status Change interrupt */
  1149. if (got_rhsc) {
  1150. #ifdef DEBUG
  1151. ohci_dump_roothub(&gohci, 1);
  1152. #endif
  1153. got_rhsc = 0;
  1154. /* abuse timeout */
  1155. timeout = rh_check_port_status(&gohci);
  1156. if (timeout >= 0) {
  1157. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1158. /* the called routine adds 1 to the passed value */
  1159. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1160. #endif
  1161. /*
  1162. * XXX
  1163. * This is potentially dangerous because it assumes
  1164. * that only one device is ever plugged in!
  1165. */
  1166. devgone = dev;
  1167. }
  1168. }
  1169. dev->status = stat;
  1170. dev->act_len = transfer_len;
  1171. #ifdef DEBUG
  1172. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
  1173. usb_pipein(pipe));
  1174. #endif
  1175. /* free TDs in urb_priv */
  1176. urb_free_priv(&urb_priv);
  1177. return 0;
  1178. }
  1179. /* submit routines called from usb.c */
  1180. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1181. int transfer_len)
  1182. {
  1183. info("submit_bulk_msg");
  1184. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1185. }
  1186. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1187. int transfer_len, struct devrequest *setup)
  1188. {
  1189. int maxsize = usb_maxpacket(dev, pipe);
  1190. info("submit_control_msg");
  1191. #ifdef DEBUG
  1192. urb_priv.actual_length = 0;
  1193. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
  1194. usb_pipein(pipe));
  1195. #endif
  1196. if (!maxsize) {
  1197. err("submit_control_message: pipesize for pipe %lx is zero",
  1198. pipe);
  1199. return -1;
  1200. }
  1201. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1202. gohci.rh.dev = dev;
  1203. /* root hub - redirect */
  1204. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1205. setup);
  1206. }
  1207. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1208. }
  1209. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1210. int transfer_len, int interval)
  1211. {
  1212. info("submit_int_msg");
  1213. return -1;
  1214. }
  1215. /*-------------------------------------------------------------------------*
  1216. * HC functions
  1217. *-------------------------------------------------------------------------*/
  1218. /* reset the HC and BUS */
  1219. static int hc_reset(ohci_t * ohci)
  1220. {
  1221. int timeout = 30;
  1222. int smm_timeout = 50; /* 0,5 sec */
  1223. if (readl(&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1224. writel(OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1225. info("USB HC TakeOver from SMM");
  1226. while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1227. wait_ms(10);
  1228. if (--smm_timeout == 0) {
  1229. err("USB HC TakeOver failed!");
  1230. return -1;
  1231. }
  1232. }
  1233. }
  1234. /* Disable HC interrupts */
  1235. writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1236. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1237. ohci->slot_name, readl(&ohci->regs->control));
  1238. /* Reset USB (needed by some controllers) */
  1239. ohci->hc_control = 0;
  1240. writel(ohci->hc_control, &ohci->regs->control);
  1241. /* HC Reset requires max 10 us delay */
  1242. writel(OHCI_HCR, &ohci->regs->cmdstatus);
  1243. while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1244. if (--timeout == 0) {
  1245. err("USB HC reset timed out!");
  1246. return -1;
  1247. }
  1248. udelay(1);
  1249. }
  1250. return 0;
  1251. }
  1252. /*-------------------------------------------------------------------------*/
  1253. /* Start an OHCI controller, set the BUS operational
  1254. * enable interrupts
  1255. * connect the virtual root hub */
  1256. static int hc_start(ohci_t * ohci)
  1257. {
  1258. __u32 mask;
  1259. unsigned int fminterval;
  1260. ohci->disabled = 1;
  1261. /* Tell the controller where the control and bulk lists are
  1262. * The lists are empty now. */
  1263. writel(0, &ohci->regs->ed_controlhead);
  1264. writel(0, &ohci->regs->ed_bulkhead);
  1265. writel((__u32) ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1266. fminterval = 0x2edf;
  1267. writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1268. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1269. writel(fminterval, &ohci->regs->fminterval);
  1270. writel(0x628, &ohci->regs->lsthresh);
  1271. /* start controller operations */
  1272. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1273. ohci->disabled = 0;
  1274. writel(ohci->hc_control, &ohci->regs->control);
  1275. /* disable all interrupts */
  1276. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1277. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1278. OHCI_INTR_OC | OHCI_INTR_MIE);
  1279. writel(mask, &ohci->regs->intrdisable);
  1280. /* clear all interrupts */
  1281. mask &= ~OHCI_INTR_MIE;
  1282. writel(mask, &ohci->regs->intrstatus);
  1283. /* Choose the interrupts we care about now - but w/o MIE */
  1284. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1285. writel(mask, &ohci->regs->intrenable);
  1286. #ifdef OHCI_USE_NPS
  1287. /* required for AMD-756 and some Mac platforms */
  1288. writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
  1289. &ohci->regs->roothub.a);
  1290. writel(RH_HS_LPSC, &ohci->regs->roothub.status);
  1291. #endif /* OHCI_USE_NPS */
  1292. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1293. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1294. mdelay((roothub_a(ohci) >> 23) & 0x1fe);
  1295. /* connect the virtual root hub */
  1296. ohci->rh.devnum = 0;
  1297. return 0;
  1298. }
  1299. /*-------------------------------------------------------------------------*/
  1300. /* an interrupt happens */
  1301. static int hc_interrupt(void)
  1302. {
  1303. ohci_t *ohci = &gohci;
  1304. struct ohci_regs *regs = ohci->regs;
  1305. int ints;
  1306. int stat = -1;
  1307. if ((ohci->hcca->done_head != 0)
  1308. && !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
  1309. ints = OHCI_INTR_WDH;
  1310. } else {
  1311. ints = readl(&regs->intrstatus);
  1312. }
  1313. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1314. if (ints & OHCI_INTR_RHSC) {
  1315. got_rhsc = 1;
  1316. }
  1317. if (ints & OHCI_INTR_UE) {
  1318. ohci->disabled++;
  1319. err("OHCI Unrecoverable Error, controller usb-%s disabled",
  1320. ohci->slot_name);
  1321. /* e.g. due to PCI Master/Target Abort */
  1322. #ifdef DEBUG
  1323. ohci_dump(ohci, 1);
  1324. #endif
  1325. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1326. /* Make some non-interrupt context restart the controller. */
  1327. /* Count and limit the retries though; either hardware or */
  1328. /* software errors can go forever... */
  1329. hc_reset(ohci);
  1330. return -1;
  1331. }
  1332. if (ints & OHCI_INTR_WDH) {
  1333. writel(OHCI_INTR_WDH, &regs->intrdisable);
  1334. stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
  1335. writel(OHCI_INTR_WDH, &regs->intrenable);
  1336. }
  1337. if (ints & OHCI_INTR_SO) {
  1338. dbg("USB Schedule overrun\n");
  1339. writel(OHCI_INTR_SO, &regs->intrenable);
  1340. stat = -1;
  1341. }
  1342. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1343. if (ints & OHCI_INTR_SF) {
  1344. unsigned int frame = ohci_cpu_to_le16(ohci->hcca->frame_no) & 1;
  1345. writel(OHCI_INTR_SF, &regs->intrdisable);
  1346. if (ohci->ed_rm_list[frame] != NULL)
  1347. writel(OHCI_INTR_SF, &regs->intrenable);
  1348. stat = 0xff;
  1349. }
  1350. writel(ints, &regs->intrstatus);
  1351. return stat;
  1352. }
  1353. /*-------------------------------------------------------------------------*/
  1354. /*-------------------------------------------------------------------------*/
  1355. /* De-allocate all resources.. */
  1356. static void hc_release_ohci(ohci_t * ohci)
  1357. {
  1358. dbg("USB HC release ohci usb-%s", ohci->slot_name);
  1359. if (!ohci->disabled)
  1360. hc_reset(ohci);
  1361. }
  1362. /*-------------------------------------------------------------------------*/
  1363. /*
  1364. * low level initalisation routine, called from usb.c
  1365. */
  1366. static char ohci_inited = 0;
  1367. int usb_lowlevel_init(void)
  1368. {
  1369. memset(&gohci, 0, sizeof(ohci_t));
  1370. memset(&urb_priv, 0, sizeof(urb_priv_t));
  1371. /* align the storage */
  1372. if ((__u32) & ghcca[0] & 0xff) {
  1373. err("HCCA not aligned!!");
  1374. return -1;
  1375. }
  1376. phcca = &ghcca[0];
  1377. info("aligned ghcca %p", phcca);
  1378. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1379. if ((__u32) & ohci_dev.ed[0] & 0x7) {
  1380. err("EDs not aligned!!");
  1381. return -1;
  1382. }
  1383. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1384. if ((__u32) gtd & 0x7) {
  1385. err("TDs not aligned!!");
  1386. return -1;
  1387. }
  1388. ptd = gtd;
  1389. gohci.hcca = phcca;
  1390. memset(phcca, 0, sizeof(struct ohci_hcca));
  1391. gohci.disabled = 1;
  1392. gohci.sleeping = 0;
  1393. gohci.irq = -1;
  1394. gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
  1395. gohci.flags = 0;
  1396. gohci.slot_name = "ppc440";
  1397. if (hc_reset(&gohci) < 0) {
  1398. hc_release_ohci(&gohci);
  1399. return -1;
  1400. }
  1401. if (hc_start(&gohci) < 0) {
  1402. err("can't start usb-%s", gohci.slot_name);
  1403. hc_release_ohci(&gohci);
  1404. return -1;
  1405. }
  1406. #ifdef DEBUG
  1407. ohci_dump(&gohci, 1);
  1408. #endif
  1409. ohci_inited = 1;
  1410. /* init the device driver */
  1411. usb_dev_init();
  1412. return 0;
  1413. }
  1414. int usb_lowlevel_stop(void)
  1415. {
  1416. /* this gets called really early - before the controller has */
  1417. /* even been initialized! */
  1418. if (!ohci_inited)
  1419. return 0;
  1420. /* TODO release any interrupts, etc. */
  1421. /* call hc_release_ohci() here ? */
  1422. hc_reset(&gohci);
  1423. return 0;
  1424. }
  1425. #endif /* CONFIG_USB_OHCI */