serial.c 30 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*------------------------------------------------------------------------------+ */
  24. /*
  25. * This source code has been made available to you by IBM on an AS-IS
  26. * basis. Anyone receiving this source is licensed under IBM
  27. * copyrights to use it in any way he or she deems fit, including
  28. * copying it, modifying it, compiling it, and redistributing it either
  29. * with or without modifications. No license under IBM patents or
  30. * patent applications is to be implied by the copyright license.
  31. *
  32. * Any user of this software should understand that IBM cannot provide
  33. * technical support for this software and will not be responsible for
  34. * any consequences resulting from the use of this software.
  35. *
  36. * Any person who transfers this source code or any derivative work
  37. * must include the IBM copyright notice, this paragraph, and the
  38. * preceding two paragraphs in the transferred software.
  39. *
  40. * COPYRIGHT I B M CORPORATION 1995
  41. * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  42. */
  43. /*------------------------------------------------------------------------------- */
  44. /*
  45. * Travis Sawyer 15 September 2004
  46. * Added CONFIG_SERIAL_MULTI support
  47. */
  48. #include <common.h>
  49. #include <commproc.h>
  50. #include <asm/processor.h>
  51. #include <watchdog.h>
  52. #include "vecnum.h"
  53. #ifdef CONFIG_SERIAL_MULTI
  54. #include <serial.h>
  55. #endif
  56. #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
  57. #include <malloc.h>
  58. #endif
  59. /*****************************************************************************/
  60. #ifdef CONFIG_IOP480
  61. #define SPU_BASE 0x40000000
  62. #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
  63. #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
  64. #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
  65. #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
  66. #define spu_BRateDivh 0x10 /* Baud rate divisor high */
  67. #define spu_BRateDivl 0x14 /* Baud rate divisor low */
  68. #define spu_CtlReg 0x18 /* Control Register */
  69. #define spu_RxCmd 0x1c /* Rx Command Register */
  70. #define spu_TxCmd 0x20 /* Tx Command Register */
  71. #define spu_RxBuff 0x24 /* Rx data buffer */
  72. #define spu_TxBuff 0x24 /* Tx data buffer */
  73. /*-----------------------------------------------------------------------------+
  74. | Line Status Register.
  75. +-----------------------------------------------------------------------------*/
  76. #define asyncLSRport1 0x40000000
  77. #define asyncLSRport1set 0x40000004
  78. #define asyncLSRDataReady 0x80
  79. #define asyncLSRFramingError 0x40
  80. #define asyncLSROverrunError 0x20
  81. #define asyncLSRParityError 0x10
  82. #define asyncLSRBreakInterrupt 0x08
  83. #define asyncLSRTxHoldEmpty 0x04
  84. #define asyncLSRTxShiftEmpty 0x02
  85. /*-----------------------------------------------------------------------------+
  86. | Handshake Status Register.
  87. +-----------------------------------------------------------------------------*/
  88. #define asyncHSRport1 0x40000008
  89. #define asyncHSRport1set 0x4000000c
  90. #define asyncHSRDsr 0x80
  91. #define asyncLSRCts 0x40
  92. /*-----------------------------------------------------------------------------+
  93. | Control Register.
  94. +-----------------------------------------------------------------------------*/
  95. #define asyncCRport1 0x40000018
  96. #define asyncCRNormal 0x00
  97. #define asyncCRLoopback 0x40
  98. #define asyncCRAutoEcho 0x80
  99. #define asyncCRDtr 0x20
  100. #define asyncCRRts 0x10
  101. #define asyncCRWordLength7 0x00
  102. #define asyncCRWordLength8 0x08
  103. #define asyncCRParityDisable 0x00
  104. #define asyncCRParityEnable 0x04
  105. #define asyncCREvenParity 0x00
  106. #define asyncCROddParity 0x02
  107. #define asyncCRStopBitsOne 0x00
  108. #define asyncCRStopBitsTwo 0x01
  109. #define asyncCRDisableDtrRts 0x00
  110. /*-----------------------------------------------------------------------------+
  111. | Receiver Command Register.
  112. +-----------------------------------------------------------------------------*/
  113. #define asyncRCRport1 0x4000001c
  114. #define asyncRCRDisable 0x00
  115. #define asyncRCREnable 0x80
  116. #define asyncRCRIntDisable 0x00
  117. #define asyncRCRIntEnabled 0x20
  118. #define asyncRCRDMACh2 0x40
  119. #define asyncRCRDMACh3 0x60
  120. #define asyncRCRErrorInt 0x10
  121. #define asyncRCRPauseEnable 0x08
  122. /*-----------------------------------------------------------------------------+
  123. | Transmitter Command Register.
  124. +-----------------------------------------------------------------------------*/
  125. #define asyncTCRport1 0x40000020
  126. #define asyncTCRDisable 0x00
  127. #define asyncTCREnable 0x80
  128. #define asyncTCRIntDisable 0x00
  129. #define asyncTCRIntEnabled 0x20
  130. #define asyncTCRDMACh2 0x40
  131. #define asyncTCRDMACh3 0x60
  132. #define asyncTCRTxEmpty 0x10
  133. #define asyncTCRErrorInt 0x08
  134. #define asyncTCRStopPause 0x04
  135. #define asyncTCRBreakGen 0x02
  136. /*-----------------------------------------------------------------------------+
  137. | Miscellanies defines.
  138. +-----------------------------------------------------------------------------*/
  139. #define asyncTxBufferport1 0x40000024
  140. #define asyncRxBufferport1 0x40000024
  141. #define asyncDLABLsbport1 0x40000014
  142. #define asyncDLABMsbport1 0x40000010
  143. #define asyncXOFFchar 0x13
  144. #define asyncXONchar 0x11
  145. /*
  146. * Minimal serial functions needed to use one of the SMC ports
  147. * as serial console interface.
  148. */
  149. int serial_init (void)
  150. {
  151. DECLARE_GLOBAL_DATA_PTR;
  152. volatile char val;
  153. unsigned short br_reg;
  154. br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
  155. /*
  156. * Init onboard UART
  157. */
  158. out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
  159. out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
  160. out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
  161. out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
  162. out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
  163. out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
  164. out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
  165. val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
  166. return (0);
  167. }
  168. void serial_setbrg (void)
  169. {
  170. DECLARE_GLOBAL_DATA_PTR;
  171. unsigned short br_reg;
  172. br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
  173. out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
  174. out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
  175. }
  176. void serial_putc (const char c)
  177. {
  178. if (c == '\n')
  179. serial_putc ('\r');
  180. /* load status from handshake register */
  181. if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
  182. out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
  183. out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
  184. while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
  185. if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
  186. out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
  187. }
  188. }
  189. void serial_puts (const char *s)
  190. {
  191. while (*s) {
  192. serial_putc (*s++);
  193. }
  194. }
  195. int serial_getc ()
  196. {
  197. unsigned char status = 0;
  198. while (1) {
  199. status = in8 (asyncLSRport1);
  200. if ((status & asyncLSRDataReady) != 0x0) {
  201. break;
  202. }
  203. if ((status & ( asyncLSRFramingError |
  204. asyncLSROverrunError |
  205. asyncLSRParityError |
  206. asyncLSRBreakInterrupt )) != 0) {
  207. (void) out8 (asyncLSRport1,
  208. asyncLSRFramingError |
  209. asyncLSROverrunError |
  210. asyncLSRParityError |
  211. asyncLSRBreakInterrupt );
  212. }
  213. }
  214. return (0x000000ff & (int) in8 (asyncRxBufferport1));
  215. }
  216. int serial_tstc ()
  217. {
  218. unsigned char status;
  219. status = in8 (asyncLSRport1);
  220. if ((status & asyncLSRDataReady) != 0x0) {
  221. return (1);
  222. }
  223. if ((status & ( asyncLSRFramingError |
  224. asyncLSROverrunError |
  225. asyncLSRParityError |
  226. asyncLSRBreakInterrupt )) != 0) {
  227. (void) out8 (asyncLSRport1,
  228. asyncLSRFramingError |
  229. asyncLSROverrunError |
  230. asyncLSRParityError |
  231. asyncLSRBreakInterrupt);
  232. }
  233. return 0;
  234. }
  235. #endif /* CONFIG_IOP480 */
  236. /*****************************************************************************/
  237. #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
  238. #if defined(CONFIG_440)
  239. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  240. #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
  241. #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
  242. #else
  243. #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
  244. #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
  245. #endif
  246. #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  247. #define CR0_MASK 0xdfffffff
  248. #define CR0_EXTCLK_ENA 0x00800000
  249. #define CR0_UDIV_POS 0
  250. #else
  251. #define CR0_MASK 0x3fff0000
  252. #define CR0_EXTCLK_ENA 0x00600000
  253. #define CR0_UDIV_POS 16
  254. #endif /* CONFIG_440_GX */
  255. #elif defined(CONFIG_405EP)
  256. #define UART0_BASE 0xef600300
  257. #define UART1_BASE 0xef600400
  258. #define UCR0_MASK 0x0000007f
  259. #define UCR1_MASK 0x00007f00
  260. #define UCR0_UDIV_POS 0
  261. #define UCR1_UDIV_POS 8
  262. #define UDIV_MAX 127
  263. #else /* CONFIG_405GP || CONFIG_405CR */
  264. #define UART0_BASE 0xef600300
  265. #define UART1_BASE 0xef600400
  266. #define CR0_MASK 0x00001fff
  267. #define CR0_EXTCLK_ENA 0x000000c0
  268. #define CR0_UDIV_POS 1
  269. #define UDIV_MAX 32
  270. #endif
  271. /* using serial port 0 or 1 as U-Boot console ? */
  272. #if defined(CONFIG_UART1_CONSOLE)
  273. #define ACTING_UART0_BASE UART1_BASE
  274. #define ACTING_UART1_BASE UART0_BASE
  275. #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  276. #define UART0_SDR sdr_uart1
  277. #define UART1_SDR sdr_uart0
  278. #endif /* CONFIG_440_GX */
  279. #else
  280. #define ACTING_UART0_BASE UART0_BASE
  281. #define ACTING_UART1_BASE UART1_BASE
  282. #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  283. #define UART0_SDR sdr_uart0
  284. #define UART1_SDR sdr_uart1
  285. #endif /* CONFIG_440_GX */
  286. #endif
  287. #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
  288. #error "External serial clock not supported on IBM PPC405EP!"
  289. #endif
  290. #define UART_RBR 0x00
  291. #define UART_THR 0x00
  292. #define UART_IER 0x01
  293. #define UART_IIR 0x02
  294. #define UART_FCR 0x02
  295. #define UART_LCR 0x03
  296. #define UART_MCR 0x04
  297. #define UART_LSR 0x05
  298. #define UART_MSR 0x06
  299. #define UART_SCR 0x07
  300. #define UART_DLL 0x00
  301. #define UART_DLM 0x01
  302. /*-----------------------------------------------------------------------------+
  303. | Line Status Register.
  304. +-----------------------------------------------------------------------------*/
  305. /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
  306. #define asyncLSRDataReady1 0x01
  307. #define asyncLSROverrunError1 0x02
  308. #define asyncLSRParityError1 0x04
  309. #define asyncLSRFramingError1 0x08
  310. #define asyncLSRBreakInterrupt1 0x10
  311. #define asyncLSRTxHoldEmpty1 0x20
  312. #define asyncLSRTxShiftEmpty1 0x40
  313. #define asyncLSRRxFifoError1 0x80
  314. /*-----------------------------------------------------------------------------+
  315. | Miscellanies defines.
  316. +-----------------------------------------------------------------------------*/
  317. /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
  318. /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
  319. #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
  320. /*-----------------------------------------------------------------------------+
  321. | Fifo
  322. +-----------------------------------------------------------------------------*/
  323. typedef struct {
  324. char *rx_buffer;
  325. ulong rx_put;
  326. ulong rx_get;
  327. } serial_buffer_t;
  328. volatile static serial_buffer_t buf_info;
  329. #endif
  330. #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
  331. static void serial_divs (int baudrate, unsigned long *pudiv,
  332. unsigned short *pbdiv )
  333. {
  334. sys_info_t sysinfo;
  335. unsigned long div; /* total divisor udiv * bdiv */
  336. unsigned long umin; /* minimum udiv */
  337. unsigned short diff; /* smallest diff */
  338. unsigned long udiv; /* best udiv */
  339. unsigned short idiff; /* current diff */
  340. unsigned short ibdiv; /* current bdiv */
  341. unsigned long i;
  342. unsigned long est; /* current estimate */
  343. get_sys_info( &sysinfo );
  344. udiv = 32; /* Assume lowest possible serial clk */
  345. div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
  346. umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
  347. diff = 32; /* highest possible */
  348. /* i is the test udiv value -- start with the largest
  349. * possible (32) to minimize serial clock and constrain
  350. * search to umin.
  351. */
  352. for( i = 32; i > umin; i-- ){
  353. ibdiv = div/i;
  354. est = i * ibdiv;
  355. idiff = (est > div) ? (est-div) : (div-est);
  356. if( idiff == 0 ){
  357. udiv = i;
  358. break; /* can't do better */
  359. }
  360. else if( idiff < diff ){
  361. udiv = i; /* best so far */
  362. diff = idiff; /* update lowest diff*/
  363. }
  364. }
  365. *pudiv = udiv;
  366. *pbdiv = div/udiv;
  367. }
  368. #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
  369. /*
  370. * Minimal serial functions needed to use one of the SMC ports
  371. * as serial console interface.
  372. */
  373. #if defined(CONFIG_440)
  374. #if defined(CONFIG_SERIAL_MULTI)
  375. int serial_init_dev (unsigned long dev_base)
  376. #else
  377. int serial_init(void)
  378. #endif
  379. {
  380. DECLARE_GLOBAL_DATA_PTR;
  381. unsigned long reg;
  382. unsigned long udiv;
  383. unsigned short bdiv;
  384. volatile char val;
  385. #ifdef CFG_EXT_SERIAL_CLOCK
  386. unsigned long tmp;
  387. #endif
  388. #if defined(CONFIG_440_GX)
  389. #if defined(CONFIG_SERIAL_MULTI)
  390. if (UART0_BASE == dev_base) {
  391. mfsdr(UART0_SDR,reg);
  392. reg &= ~CR0_MASK;
  393. } else {
  394. mfsdr(UART1_SDR,reg);
  395. reg &= ~CR0_MASK;
  396. }
  397. #else
  398. mfsdr(UART0_SDR,reg);
  399. reg &= ~CR0_MASK;
  400. #endif
  401. #else
  402. reg = mfdcr(cntrl0) & ~CR0_MASK;
  403. #endif /* CONFIG_440_GX */
  404. #ifdef CFG_EXT_SERIAL_CLOCK
  405. reg |= CR0_EXTCLK_ENA;
  406. udiv = 1;
  407. tmp = gd->baudrate * 16;
  408. bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
  409. #else
  410. /* For 440, the cpu clock is on divider chain A, UART on divider
  411. * chain B ... so cpu clock is irrelevant. Get the "optimized"
  412. * values that are subject to the 1/2 opb clock constraint
  413. */
  414. serial_divs (gd->baudrate, &udiv, &bdiv);
  415. #endif
  416. #if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  417. reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
  418. #if defined(CONFIG_SERIAL_MULTI)
  419. if (UART0_BASE == dev_base) {
  420. mtsdr (UART0_SDR,reg);
  421. } else {
  422. mtsdr (UART1_SDR,reg);
  423. }
  424. #else
  425. mtsdr (UART0_SDR,reg);
  426. #endif
  427. #else
  428. reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
  429. mtdcr (cntrl0, reg);
  430. #endif
  431. #if defined(CONFIG_SERIAL_MULTI)
  432. out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  433. out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  434. out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  435. out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  436. out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
  437. out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
  438. val = in8 (dev_base + UART_LSR); /* clear line status */
  439. val = in8 (dev_base + UART_RBR); /* read receive buffer */
  440. out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
  441. out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
  442. #else
  443. out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
  444. out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
  445. out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  446. out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  447. out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
  448. out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
  449. val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
  450. val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
  451. out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
  452. out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
  453. #endif
  454. return (0);
  455. }
  456. #else /* !defined(CONFIG_440) */
  457. #if defined(CONFIG_SERIAL_MULTI)
  458. int serial_init_dev (unsigned long dev_base)
  459. #else
  460. int serial_init (void)
  461. #endif
  462. {
  463. DECLARE_GLOBAL_DATA_PTR;
  464. unsigned long reg;
  465. unsigned long tmp;
  466. unsigned long clk;
  467. unsigned long udiv;
  468. unsigned short bdiv;
  469. volatile char val;
  470. #ifdef CONFIG_405EP
  471. reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
  472. clk = gd->cpu_clk;
  473. tmp = CFG_BASE_BAUD * 16;
  474. udiv = (clk + tmp / 2) / tmp;
  475. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  476. udiv = UDIV_MAX;
  477. reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
  478. reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
  479. mtdcr (cpc0_ucr, reg);
  480. #else /* CONFIG_405EP */
  481. reg = mfdcr(cntrl0) & ~CR0_MASK;
  482. #ifdef CFG_EXT_SERIAL_CLOCK
  483. clk = CFG_EXT_SERIAL_CLOCK;
  484. udiv = 1;
  485. reg |= CR0_EXTCLK_ENA;
  486. #else
  487. clk = gd->cpu_clk;
  488. #ifdef CFG_405_UART_ERRATA_59
  489. udiv = 31; /* Errata 59: stuck at 31 */
  490. #else
  491. tmp = CFG_BASE_BAUD * 16;
  492. udiv = (clk + tmp / 2) / tmp;
  493. if (udiv > UDIV_MAX) /* max. n bits for udiv */
  494. udiv = UDIV_MAX;
  495. #endif
  496. #endif
  497. reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
  498. mtdcr (cntrl0, reg);
  499. #endif /* CONFIG_405EP */
  500. tmp = gd->baudrate * udiv * 16;
  501. bdiv = (clk + tmp / 2) / tmp;
  502. #if defined(CONFIG_SERIAL_MULTI)
  503. out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  504. out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  505. out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  506. out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  507. out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
  508. out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
  509. val = in8 (dev_base + UART_LSR); /* clear line status */
  510. val = in8 (dev_base + UART_RBR); /* read receive buffer */
  511. out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
  512. out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
  513. #else
  514. out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
  515. out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
  516. out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  517. out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  518. out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
  519. out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
  520. val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
  521. val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
  522. out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
  523. out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
  524. #endif
  525. return (0);
  526. }
  527. #endif /* if defined(CONFIG_440) */
  528. #if defined(CONFIG_SERIAL_MULTI)
  529. void serial_setbrg_dev (unsigned long dev_base)
  530. #else
  531. void serial_setbrg (void)
  532. #endif
  533. {
  534. DECLARE_GLOBAL_DATA_PTR;
  535. unsigned long tmp;
  536. unsigned long clk;
  537. unsigned long udiv;
  538. unsigned short bdiv;
  539. #ifdef CFG_EXT_SERIAL_CLOCK
  540. clk = CFG_EXT_SERIAL_CLOCK;
  541. #else
  542. clk = gd->cpu_clk;
  543. #endif
  544. #ifdef CONFIG_405EP
  545. udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
  546. #else
  547. udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
  548. #endif /* CONFIG_405EP */
  549. tmp = gd->baudrate * udiv * 16;
  550. bdiv = (clk + tmp / 2) / tmp;
  551. #if defined(CONFIG_SERIAL_MULTI)
  552. out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
  553. out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
  554. out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  555. out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  556. #else
  557. out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
  558. out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
  559. out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
  560. out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
  561. #endif
  562. }
  563. #if defined(CONFIG_SERIAL_MULTI)
  564. void serial_putc_dev (unsigned long dev_base, const char c)
  565. #else
  566. void serial_putc (const char c)
  567. #endif
  568. {
  569. int i;
  570. if (c == '\n')
  571. #if defined(CONFIG_SERIAL_MULTI)
  572. serial_putc_dev (dev_base, '\r');
  573. #else
  574. serial_putc ('\r');
  575. #endif
  576. /* check THRE bit, wait for transmiter available */
  577. for (i = 1; i < 3500; i++) {
  578. #if defined(CONFIG_SERIAL_MULTI)
  579. if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
  580. #else
  581. if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
  582. #endif
  583. break;
  584. udelay (100);
  585. }
  586. #if defined(CONFIG_SERIAL_MULTI)
  587. out8 (dev_base + UART_THR, c); /* put character out */
  588. #else
  589. out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
  590. #endif
  591. }
  592. #if defined(CONFIG_SERIAL_MULTI)
  593. void serial_puts_dev (unsigned long dev_base, const char *s)
  594. #else
  595. void serial_puts (const char *s)
  596. #endif
  597. {
  598. while (*s) {
  599. #if defined(CONFIG_SERIAL_MULTI)
  600. serial_putc_dev (dev_base, *s++);
  601. #else
  602. serial_putc (*s++);
  603. #endif
  604. }
  605. }
  606. #if defined(CONFIG_SERIAL_MULTI)
  607. int serial_getc_dev (unsigned long dev_base)
  608. #else
  609. int serial_getc (void)
  610. #endif
  611. {
  612. unsigned char status = 0;
  613. while (1) {
  614. #if defined(CONFIG_HW_WATCHDOG)
  615. WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
  616. #endif /* CONFIG_HW_WATCHDOG */
  617. #if defined(CONFIG_SERIAL_MULTI)
  618. status = in8 (dev_base + UART_LSR);
  619. #else
  620. status = in8 (ACTING_UART0_BASE + UART_LSR);
  621. #endif
  622. if ((status & asyncLSRDataReady1) != 0x0) {
  623. break;
  624. }
  625. if ((status & ( asyncLSRFramingError1 |
  626. asyncLSROverrunError1 |
  627. asyncLSRParityError1 |
  628. asyncLSRBreakInterrupt1 )) != 0) {
  629. #if defined(CONFIG_SERIAL_MULTI)
  630. out8 (dev_base + UART_LSR,
  631. #else
  632. out8 (ACTING_UART0_BASE + UART_LSR,
  633. #endif
  634. asyncLSRFramingError1 |
  635. asyncLSROverrunError1 |
  636. asyncLSRParityError1 |
  637. asyncLSRBreakInterrupt1);
  638. }
  639. }
  640. #if defined(CONFIG_SERIAL_MULTI)
  641. return (0x000000ff & (int) in8 (dev_base));
  642. #else
  643. return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
  644. #endif
  645. }
  646. #if defined(CONFIG_SERIAL_MULTI)
  647. int serial_tstc_dev (unsigned long dev_base)
  648. #else
  649. int serial_tstc (void)
  650. #endif
  651. {
  652. unsigned char status;
  653. #if defined(CONFIG_SERIAL_MULTI)
  654. status = in8 (dev_base + UART_LSR);
  655. #else
  656. status = in8 (ACTING_UART0_BASE + UART_LSR);
  657. #endif
  658. if ((status & asyncLSRDataReady1) != 0x0) {
  659. return (1);
  660. }
  661. if ((status & ( asyncLSRFramingError1 |
  662. asyncLSROverrunError1 |
  663. asyncLSRParityError1 |
  664. asyncLSRBreakInterrupt1 )) != 0) {
  665. #if defined(CONFIG_SERIAL_MULTI)
  666. out8 (dev_base + UART_LSR,
  667. #else
  668. out8 (ACTING_UART0_BASE + UART_LSR,
  669. #endif
  670. asyncLSRFramingError1 |
  671. asyncLSROverrunError1 |
  672. asyncLSRParityError1 |
  673. asyncLSRBreakInterrupt1);
  674. }
  675. return 0;
  676. }
  677. #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
  678. void serial_isr (void *arg)
  679. {
  680. int space;
  681. int c;
  682. const int rx_get = buf_info.rx_get;
  683. int rx_put = buf_info.rx_put;
  684. if (rx_get <= rx_put) {
  685. space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
  686. } else {
  687. space = rx_get - rx_put;
  688. }
  689. while (serial_tstc_dev (ACTING_UART0_BASE)) {
  690. c = serial_getc_dev (ACTING_UART0_BASE);
  691. if (space) {
  692. buf_info.rx_buffer[rx_put++] = c;
  693. space--;
  694. }
  695. if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
  696. rx_put = 0;
  697. if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
  698. /* Stop flow by setting RTS inactive */
  699. out8 (ACTING_UART0_BASE + UART_MCR,
  700. in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
  701. }
  702. }
  703. buf_info.rx_put = rx_put;
  704. }
  705. void serial_buffered_init (void)
  706. {
  707. serial_puts ("Switching to interrupt driven serial input mode.\n");
  708. buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
  709. buf_info.rx_put = 0;
  710. buf_info.rx_get = 0;
  711. if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
  712. serial_puts ("Check CTS signal present on serial port: OK.\n");
  713. } else {
  714. serial_puts ("WARNING: CTS signal not present on serial port.\n");
  715. }
  716. irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
  717. serial_isr /*interrupt_handler_t *handler */ ,
  718. (void *) &buf_info /*void *arg */ );
  719. /* Enable "RX Data Available" Interrupt on UART */
  720. /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
  721. out8 (ACTING_UART0_BASE + UART_IER, 0x01);
  722. /* Set DTR active */
  723. out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
  724. /* Start flow by setting RTS active */
  725. out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
  726. /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
  727. out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
  728. }
  729. void serial_buffered_putc (const char c)
  730. {
  731. /* Wait for CTS */
  732. #if defined(CONFIG_HW_WATCHDOG)
  733. while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
  734. WATCHDOG_RESET ();
  735. #else
  736. while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
  737. #endif
  738. serial_putc (c);
  739. }
  740. void serial_buffered_puts (const char *s)
  741. {
  742. serial_puts (s);
  743. }
  744. int serial_buffered_getc (void)
  745. {
  746. int space;
  747. int c;
  748. int rx_get = buf_info.rx_get;
  749. int rx_put;
  750. #if defined(CONFIG_HW_WATCHDOG)
  751. while (rx_get == buf_info.rx_put)
  752. WATCHDOG_RESET ();
  753. #else
  754. while (rx_get == buf_info.rx_put);
  755. #endif
  756. c = buf_info.rx_buffer[rx_get++];
  757. if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
  758. rx_get = 0;
  759. buf_info.rx_get = rx_get;
  760. rx_put = buf_info.rx_put;
  761. if (rx_get <= rx_put) {
  762. space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
  763. } else {
  764. space = rx_get - rx_put;
  765. }
  766. if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
  767. /* Start flow by setting RTS active */
  768. out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
  769. }
  770. return c;
  771. }
  772. int serial_buffered_tstc (void)
  773. {
  774. return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
  775. }
  776. #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
  777. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  778. /*
  779. AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
  780. number 0 or number 1
  781. - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
  782. configuration has been already done
  783. - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
  784. configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
  785. */
  786. #if (CONFIG_KGDB_SER_INDEX & 2)
  787. void kgdb_serial_init (void)
  788. {
  789. DECLARE_GLOBAL_DATA_PTR;
  790. volatile char val;
  791. unsigned short br_reg;
  792. get_clocks ();
  793. br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
  794. 5) / 10;
  795. /*
  796. * Init onboard 16550 UART
  797. */
  798. out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
  799. out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
  800. out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
  801. out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
  802. out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
  803. out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
  804. val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
  805. val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
  806. out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
  807. out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
  808. }
  809. void putDebugChar (const char c)
  810. {
  811. if (c == '\n')
  812. serial_putc ('\r');
  813. out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
  814. /* check THRE bit, wait for transfer done */
  815. while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
  816. }
  817. void putDebugStr (const char *s)
  818. {
  819. while (*s) {
  820. serial_putc (*s++);
  821. }
  822. }
  823. int getDebugChar (void)
  824. {
  825. unsigned char status = 0;
  826. while (1) {
  827. status = in8 (ACTING_UART1_BASE + UART_LSR);
  828. if ((status & asyncLSRDataReady1) != 0x0) {
  829. break;
  830. }
  831. if ((status & ( asyncLSRFramingError1 |
  832. asyncLSROverrunError1 |
  833. asyncLSRParityError1 |
  834. asyncLSRBreakInterrupt1 )) != 0) {
  835. out8 (ACTING_UART1_BASE + UART_LSR,
  836. asyncLSRFramingError1 |
  837. asyncLSROverrunError1 |
  838. asyncLSRParityError1 |
  839. asyncLSRBreakInterrupt1);
  840. }
  841. }
  842. return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
  843. }
  844. void kgdb_interruptible (int yes)
  845. {
  846. return;
  847. }
  848. #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
  849. void kgdb_serial_init (void)
  850. {
  851. serial_printf ("[on serial] ");
  852. }
  853. void putDebugChar (int c)
  854. {
  855. serial_putc (c);
  856. }
  857. void putDebugStr (const char *str)
  858. {
  859. serial_puts (str);
  860. }
  861. int getDebugChar (void)
  862. {
  863. return serial_getc ();
  864. }
  865. void kgdb_interruptible (int yes)
  866. {
  867. return;
  868. }
  869. #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
  870. #endif /* CFG_CMD_KGDB */
  871. #if defined(CONFIG_SERIAL_MULTI)
  872. int serial0_init(void)
  873. {
  874. return (serial_init_dev(UART0_BASE));
  875. }
  876. int serial1_init(void)
  877. {
  878. return (serial_init_dev(UART1_BASE));
  879. }
  880. void serial0_setbrg (void)
  881. {
  882. serial_setbrg_dev(UART0_BASE);
  883. }
  884. void serial1_setbrg (void)
  885. {
  886. serial_setbrg_dev(UART1_BASE);
  887. }
  888. void serial0_putc(const char c)
  889. {
  890. serial_putc_dev(UART0_BASE,c);
  891. }
  892. void serial1_putc(const char c)
  893. {
  894. serial_putc_dev(UART1_BASE, c);
  895. }
  896. void serial0_puts(const char *s)
  897. {
  898. serial_puts_dev(UART0_BASE, s);
  899. }
  900. void serial1_puts(const char *s)
  901. {
  902. serial_puts_dev(UART1_BASE, s);
  903. }
  904. int serial0_getc(void)
  905. {
  906. return(serial_getc_dev(UART0_BASE));
  907. }
  908. int serial1_getc(void)
  909. {
  910. return(serial_getc_dev(UART1_BASE));
  911. }
  912. int serial0_tstc(void)
  913. {
  914. return (serial_tstc_dev(UART0_BASE));
  915. }
  916. int serial1_tstc(void)
  917. {
  918. return (serial_tstc_dev(UART1_BASE));
  919. }
  920. struct serial_device serial0_device =
  921. {
  922. "serial0",
  923. "UART0",
  924. serial0_init,
  925. serial0_setbrg,
  926. serial0_getc,
  927. serial0_tstc,
  928. serial0_putc,
  929. serial0_puts,
  930. };
  931. struct serial_device serial1_device =
  932. {
  933. "serial1",
  934. "UART1",
  935. serial1_init,
  936. serial1_setbrg,
  937. serial1_getc,
  938. serial1_tstc,
  939. serial1_putc,
  940. serial1_puts,
  941. };
  942. #endif /* CONFIG_SERIAL_MULTI */
  943. #endif /* CONFIG_405GP || CONFIG_405CR */