interrupts.c 12 KB

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  1. /*
  2. * (C) Copyright 2000-2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2002 (440 port)
  6. * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
  7. *
  8. * (C) Copyright 2003 (440GX port)
  9. * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <common.h>
  30. #include <watchdog.h>
  31. #include <command.h>
  32. #include <asm/processor.h>
  33. #include <ppc4xx.h>
  34. #include <ppc_asm.tmpl>
  35. #include <commproc.h>
  36. #include "vecnum.h"
  37. /****************************************************************************/
  38. /*
  39. * CPM interrupt vector functions.
  40. */
  41. struct irq_action {
  42. interrupt_handler_t *handler;
  43. void *arg;
  44. int count;
  45. };
  46. static struct irq_action irq_vecs[32];
  47. #if defined(CONFIG_440)
  48. static struct irq_action irq_vecs1[32]; /* For UIC1 */
  49. void uic1_interrupt( void * parms); /* UIC1 handler */
  50. #if defined(CONFIG_440_GX)
  51. static struct irq_action irq_vecs2[32]; /* For UIC2 */
  52. void uic0_interrupt( void * parms); /* UIC0 handler */
  53. void uic2_interrupt( void * parms); /* UIC2 handler */
  54. #endif /* CONFIG_440_GX */
  55. #endif /* CONFIG_440 */
  56. /****************************************************************************/
  57. #if defined(CONFIG_440)
  58. /* SPRN changed in 440 */
  59. static __inline__ void set_evpr(unsigned long val)
  60. {
  61. asm volatile("mtspr 0x03f,%0" : : "r" (val));
  62. }
  63. #else /* !defined(CONFIG_440) */
  64. static __inline__ void set_pit(unsigned long val)
  65. {
  66. asm volatile("mtpit %0" : : "r" (val));
  67. }
  68. static __inline__ void set_tcr(unsigned long val)
  69. {
  70. asm volatile("mttcr %0" : : "r" (val));
  71. }
  72. static __inline__ void set_evpr(unsigned long val)
  73. {
  74. asm volatile("mtevpr %0" : : "r" (val));
  75. }
  76. #endif /* defined(CONFIG_440 */
  77. /****************************************************************************/
  78. int interrupt_init_cpu (unsigned *decrementer_count)
  79. {
  80. DECLARE_GLOBAL_DATA_PTR;
  81. int vec;
  82. unsigned long val;
  83. /* decrementer is automatically reloaded */
  84. *decrementer_count = 0;
  85. /*
  86. * Mark all irqs as free
  87. */
  88. for (vec=0; vec<32; vec++) {
  89. irq_vecs[vec].handler = NULL;
  90. irq_vecs[vec].arg = NULL;
  91. irq_vecs[vec].count = 0;
  92. #if defined(CONFIG_440)
  93. irq_vecs1[vec].handler = NULL;
  94. irq_vecs1[vec].arg = NULL;
  95. irq_vecs1[vec].count = 0;
  96. #if defined(CONFIG_440_GX)
  97. irq_vecs2[vec].handler = NULL;
  98. irq_vecs2[vec].arg = NULL;
  99. irq_vecs2[vec].count = 0;
  100. #endif /* CONFIG_440_GX */
  101. #endif
  102. }
  103. #ifdef CONFIG_4xx
  104. /*
  105. * Init PIT
  106. */
  107. #if defined(CONFIG_440)
  108. val = mfspr( tcr );
  109. val &= (~0x04400000); /* clear DIS & ARE */
  110. mtspr( tcr, val );
  111. mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
  112. mtspr( decar, 0 ); /* clear reload */
  113. mtspr( tsr, 0x08000000 ); /* clear DEC status */
  114. val = gd->bd->bi_intfreq/1000; /* 1 msec */
  115. mtspr( decar, val ); /* Set auto-reload value */
  116. mtspr( dec, val ); /* Set inital val */
  117. #else
  118. set_pit(gd->bd->bi_intfreq / 1000);
  119. #endif
  120. #endif /* CONFIG_4xx */
  121. #ifdef CONFIG_ADCIOP
  122. /*
  123. * Init PIT
  124. */
  125. set_pit(66000);
  126. #endif
  127. /*
  128. * Enable PIT
  129. */
  130. val = mfspr(tcr);
  131. val |= 0x04400000;
  132. mtspr(tcr, val);
  133. /*
  134. * Set EVPR to 0
  135. */
  136. set_evpr(0x00000000);
  137. #if defined(CONFIG_440)
  138. #if !defined(CONFIG_440_GX)
  139. /* Install the UIC1 handlers */
  140. irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
  141. irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
  142. #endif
  143. #endif
  144. #if defined(CONFIG_440_GX)
  145. /* Take the GX out of compatibility mode
  146. * Travis Sawyer, 9 Mar 2004
  147. * NOTE: 440gx user manual inconsistency here
  148. * Compatibility mode and Ethernet Clock select are not
  149. * correct in the manual
  150. */
  151. mfsdr(sdr_mfr, val);
  152. val &= ~0x10000000;
  153. mtsdr(sdr_mfr,val);
  154. /* Enable UIC interrupts via UIC Base Enable Register */
  155. mtdcr(uicb0sr, UICB0_ALL);
  156. mtdcr(uicb0er, 0x54000000);
  157. /* None are critical */
  158. mtdcr(uicb0cr, 0);
  159. #endif
  160. return (0);
  161. }
  162. /****************************************************************************/
  163. /*
  164. * Handle external interrupts
  165. */
  166. #if defined(CONFIG_440_GX)
  167. void external_interrupt(struct pt_regs *regs)
  168. {
  169. ulong uic_msr;
  170. /*
  171. * Read masked interrupt status register to determine interrupt source
  172. */
  173. /* 440 GX uses base uic register */
  174. uic_msr = mfdcr(uicb0msr);
  175. if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
  176. uic0_interrupt(0);
  177. if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
  178. uic1_interrupt(0);
  179. if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
  180. uic2_interrupt(0);
  181. mtdcr(uicb0sr, uic_msr);
  182. return;
  183. } /* external_interrupt CONFIG_440_GX */
  184. #else
  185. void external_interrupt(struct pt_regs *regs)
  186. {
  187. ulong uic_msr;
  188. ulong msr_shift;
  189. int vec;
  190. /*
  191. * Read masked interrupt status register to determine interrupt source
  192. */
  193. uic_msr = mfdcr(uicmsr);
  194. msr_shift = uic_msr;
  195. vec = 0;
  196. while (msr_shift != 0) {
  197. if (msr_shift & 0x80000000) {
  198. /*
  199. * Increment irq counter (for debug purpose only)
  200. */
  201. irq_vecs[vec].count++;
  202. if (irq_vecs[vec].handler != NULL) {
  203. /* call isr */
  204. (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
  205. } else {
  206. mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
  207. printf ("Masking bogus interrupt vector 0x%x\n", vec);
  208. }
  209. /*
  210. * After servicing the interrupt, we have to remove the status indicator.
  211. */
  212. mtdcr(uicsr, (0x80000000 >> vec));
  213. }
  214. /*
  215. * Shift msr to next position and increment vector
  216. */
  217. msr_shift <<= 1;
  218. vec++;
  219. }
  220. }
  221. #endif
  222. #if defined(CONFIG_440_GX)
  223. /* Handler for UIC0 interrupt */
  224. void uic0_interrupt( void * parms)
  225. {
  226. ulong uic_msr;
  227. ulong msr_shift;
  228. int vec;
  229. /*
  230. * Read masked interrupt status register to determine interrupt source
  231. */
  232. uic_msr = mfdcr(uicmsr);
  233. msr_shift = uic_msr;
  234. vec = 0;
  235. while (msr_shift != 0) {
  236. if (msr_shift & 0x80000000) {
  237. /*
  238. * Increment irq counter (for debug purpose only)
  239. */
  240. irq_vecs[vec].count++;
  241. if (irq_vecs[vec].handler != NULL) {
  242. /* call isr */
  243. (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
  244. } else {
  245. mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
  246. printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec);
  247. }
  248. /*
  249. * After servicing the interrupt, we have to remove the status indicator.
  250. */
  251. mtdcr(uicsr, (0x80000000 >> vec));
  252. }
  253. /*
  254. * Shift msr to next position and increment vector
  255. */
  256. msr_shift <<= 1;
  257. vec++;
  258. }
  259. }
  260. #endif /* CONFIG_440_GX */
  261. #if defined(CONFIG_440)
  262. /* Handler for UIC1 interrupt */
  263. void uic1_interrupt( void * parms)
  264. {
  265. ulong uic1_msr;
  266. ulong msr_shift;
  267. int vec;
  268. /*
  269. * Read masked interrupt status register to determine interrupt source
  270. */
  271. uic1_msr = mfdcr(uic1msr);
  272. msr_shift = uic1_msr;
  273. vec = 0;
  274. while (msr_shift != 0) {
  275. if (msr_shift & 0x80000000) {
  276. /*
  277. * Increment irq counter (for debug purpose only)
  278. */
  279. irq_vecs1[vec].count++;
  280. if (irq_vecs1[vec].handler != NULL) {
  281. /* call isr */
  282. (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
  283. } else {
  284. mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
  285. printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
  286. }
  287. /*
  288. * After servicing the interrupt, we have to remove the status indicator.
  289. */
  290. mtdcr(uic1sr, (0x80000000 >> vec));
  291. }
  292. /*
  293. * Shift msr to next position and increment vector
  294. */
  295. msr_shift <<= 1;
  296. vec++;
  297. }
  298. }
  299. #endif /* defined(CONFIG_440) */
  300. #if defined(CONFIG_440_GX)
  301. /* Handler for UIC1 interrupt */
  302. void uic2_interrupt( void * parms)
  303. {
  304. ulong uic2_msr;
  305. ulong msr_shift;
  306. int vec;
  307. /*
  308. * Read masked interrupt status register to determine interrupt source
  309. */
  310. uic2_msr = mfdcr(uic2msr);
  311. msr_shift = uic2_msr;
  312. vec = 0;
  313. while (msr_shift != 0) {
  314. if (msr_shift & 0x80000000) {
  315. /*
  316. * Increment irq counter (for debug purpose only)
  317. */
  318. irq_vecs2[vec].count++;
  319. if (irq_vecs2[vec].handler != NULL) {
  320. /* call isr */
  321. (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg);
  322. } else {
  323. mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec));
  324. printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
  325. }
  326. /*
  327. * After servicing the interrupt, we have to remove the status indicator.
  328. */
  329. mtdcr(uic2sr, (0x80000000 >> vec));
  330. }
  331. /*
  332. * Shift msr to next position and increment vector
  333. */
  334. msr_shift <<= 1;
  335. vec++;
  336. }
  337. }
  338. #endif /* defined(CONFIG_440_GX) */
  339. /****************************************************************************/
  340. /*
  341. * Install and free a interrupt handler.
  342. */
  343. void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
  344. {
  345. struct irq_action *irqa = irq_vecs;
  346. int i = vec;
  347. #if defined(CONFIG_440)
  348. #if defined(CONFIG_440_GX)
  349. if ((vec > 31) && (vec < 64)) {
  350. i = vec - 32;
  351. irqa = irq_vecs1;
  352. } else if (vec > 63) {
  353. i = vec - 64;
  354. irqa = irq_vecs2;
  355. }
  356. #else /* CONFIG_440_GX */
  357. if (vec > 31) {
  358. i = vec - 32;
  359. irqa = irq_vecs1;
  360. }
  361. #endif /* CONFIG_440_GX */
  362. #endif /* CONFIG_440 */
  363. /*
  364. * print warning when replacing with a different irq vector
  365. */
  366. if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) {
  367. printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
  368. vec, (uint) handler, (uint) irqa[i].handler);
  369. }
  370. irqa[i].handler = handler;
  371. irqa[i].arg = arg;
  372. #if defined(CONFIG_440)
  373. #if defined(CONFIG_440_GX)
  374. if ((vec > 31) && (vec < 64))
  375. mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
  376. else if (vec > 63)
  377. mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i));
  378. else
  379. #endif /* CONFIG_440_GX */
  380. if (vec > 31)
  381. mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i));
  382. else
  383. #endif
  384. mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i));
  385. #if 0
  386. printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
  387. #endif
  388. }
  389. void irq_free_handler (int vec)
  390. {
  391. struct irq_action *irqa = irq_vecs;
  392. int i = vec;
  393. #if defined(CONFIG_440)
  394. #if defined(CONFIG_440_GX)
  395. if ((vec > 31) && (vec < 64)) {
  396. irqa = irq_vecs1;
  397. i = vec - 32;
  398. } else if (vec > 63) {
  399. irqa = irq_vecs2;
  400. i = vec - 64;
  401. }
  402. #endif /* CONFIG_440_GX */
  403. if (vec > 31) {
  404. irqa = irq_vecs1;
  405. i = vec - 32;
  406. }
  407. #endif
  408. #if 0
  409. printf ("Free interrupt for vector %d ==> %p\n",
  410. vec, irq_vecs[vec].handler);
  411. #endif
  412. #if defined(CONFIG_440)
  413. #if defined(CONFIG_440_GX)
  414. if ((vec > 31) && (vec < 64))
  415. mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
  416. else if (vec > 63)
  417. mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i));
  418. else
  419. #endif /* CONFIG_440_GX */
  420. if (vec > 31)
  421. mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i));
  422. else
  423. #endif
  424. mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i));
  425. irqa[i].handler = NULL;
  426. irqa[i].arg = NULL;
  427. }
  428. /****************************************************************************/
  429. void timer_interrupt_cpu (struct pt_regs *regs)
  430. {
  431. /* nothing to do here */
  432. return;
  433. }
  434. /****************************************************************************/
  435. #if (CONFIG_COMMANDS & CFG_CMD_IRQ)
  436. /*******************************************************************************
  437. *
  438. * irqinfo - print information about PCI devices
  439. *
  440. */
  441. int
  442. do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  443. {
  444. int vec;
  445. printf ("\nInterrupt-Information:\n");
  446. #if defined(CONFIG_440)
  447. printf ("\nUIC 0\n");
  448. #endif
  449. printf ("Nr Routine Arg Count\n");
  450. for (vec=0; vec<32; vec++) {
  451. if (irq_vecs[vec].handler != NULL) {
  452. printf ("%02d %08lx %08lx %d\n",
  453. vec,
  454. (ulong)irq_vecs[vec].handler,
  455. (ulong)irq_vecs[vec].arg,
  456. irq_vecs[vec].count);
  457. }
  458. }
  459. #if defined(CONFIG_440)
  460. printf ("\nUIC 1\n");
  461. printf ("Nr Routine Arg Count\n");
  462. for (vec=0; vec<32; vec++) {
  463. if (irq_vecs1[vec].handler != NULL)
  464. printf ("%02d %08lx %08lx %d\n",
  465. vec+31, (ulong)irq_vecs1[vec].handler,
  466. (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
  467. }
  468. printf("\n");
  469. #endif
  470. #if defined(CONFIG_440_GX)
  471. printf ("\nUIC 2\n");
  472. printf ("Nr Routine Arg Count\n");
  473. for (vec=0; vec<32; vec++) {
  474. if (irq_vecs2[vec].handler != NULL)
  475. printf ("%02d %08lx %08lx %d\n",
  476. vec+63, (ulong)irq_vecs2[vec].handler,
  477. (ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count);
  478. }
  479. printf("\n");
  480. #endif
  481. return 0;
  482. }
  483. #endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */