cpu_init.c 7.2 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <watchdog.h>
  25. #include <405gp_enet.h>
  26. #include <asm/processor.h>
  27. #include <ppc4xx.h>
  28. #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
  29. #ifdef CFG_INIT_DCACHE_CS
  30. # if (CFG_INIT_DCACHE_CS == 0)
  31. # define PBxAP pb0ap
  32. # define PBxCR pb0cr
  33. # if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
  34. # define PBxAP_VAL CFG_EBC_PB0AP
  35. # define PBxCR_VAL CFG_EBC_PB0CR
  36. # endif
  37. # endif
  38. # if (CFG_INIT_DCACHE_CS == 1)
  39. # define PBxAP pb1ap
  40. # define PBxCR pb1cr
  41. # if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
  42. # define PBxAP_VAL CFG_EBC_PB1AP
  43. # define PBxCR_VAL CFG_EBC_PB1CR
  44. # endif
  45. # endif
  46. # if (CFG_INIT_DCACHE_CS == 2)
  47. # define PBxAP pb2ap
  48. # define PBxCR pb2cr
  49. # if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
  50. # define PBxAP_VAL CFG_EBC_PB2AP
  51. # define PBxCR_VAL CFG_EBC_PB2CR
  52. # endif
  53. # endif
  54. # if (CFG_INIT_DCACHE_CS == 3)
  55. # define PBxAP pb3ap
  56. # define PBxCR pb3cr
  57. # if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
  58. # define PBxAP_VAL CFG_EBC_PB3AP
  59. # define PBxCR_VAL CFG_EBC_PB3CR
  60. # endif
  61. # endif
  62. # if (CFG_INIT_DCACHE_CS == 4)
  63. # define PBxAP pb4ap
  64. # define PBxCR pb4cr
  65. # if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
  66. # define PBxAP_VAL CFG_EBC_PB4AP
  67. # define PBxCR_VAL CFG_EBC_PB4CR
  68. # endif
  69. # endif
  70. # if (CFG_INIT_DCACHE_CS == 5)
  71. # define PBxAP pb5ap
  72. # define PBxCR pb5cr
  73. # if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
  74. # define PBxAP_VAL CFG_EBC_PB5AP
  75. # define PBxCR_VAL CFG_EBC_PB5CR
  76. # endif
  77. # endif
  78. # if (CFG_INIT_DCACHE_CS == 6)
  79. # define PBxAP pb6ap
  80. # define PBxCR pb6cr
  81. # if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
  82. # define PBxAP_VAL CFG_EBC_PB6AP
  83. # define PBxCR_VAL CFG_EBC_PB6CR
  84. # endif
  85. # endif
  86. # if (CFG_INIT_DCACHE_CS == 7)
  87. # define PBxAP pb7ap
  88. # define PBxCR pb7cr
  89. # if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
  90. # define PBxAP_VAL CFG_EBC_PB7AP
  91. # define PBxCR_VAL CFG_EBC_PB7CR
  92. # endif
  93. # endif
  94. #endif /* CFG_INIT_DCACHE_CS */
  95. /*
  96. * Breath some life into the CPU...
  97. *
  98. * Set up the memory map,
  99. * initialize a bunch of registers
  100. */
  101. void
  102. cpu_init_f (void)
  103. {
  104. #if defined(CONFIG_405EP)
  105. /*
  106. * GPIO0 setup (select GPIO or alternate function)
  107. */
  108. out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
  109. out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
  110. out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
  111. out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
  112. out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
  113. out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
  114. out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
  115. /*
  116. * Set EMAC noise filter bits
  117. */
  118. mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
  119. #endif /* CONFIG_405EP */
  120. /*
  121. * External Bus Controller (EBC) Setup
  122. */
  123. #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
  124. /*
  125. * Move the next instructions into icache, since these modify the flash
  126. * we are running from!
  127. */
  128. asm volatile(" bl 0f" ::: "lr");
  129. asm volatile("0: mflr 3" ::: "r3");
  130. asm volatile(" addi 4, 0, 14" ::: "r4");
  131. asm volatile(" mtctr 4" ::: "ctr");
  132. asm volatile("1: icbt 0, 3");
  133. asm volatile(" addi 3, 3, 32" ::: "r3");
  134. asm volatile(" bdnz 1b" ::: "ctr", "cr0");
  135. asm volatile(" addis 3, 0, 0x0" ::: "r3");
  136. asm volatile(" ori 3, 3, 0xA000" ::: "r3");
  137. asm volatile(" mtctr 3" ::: "ctr");
  138. asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
  139. mtebc(pb0ap, CFG_EBC_PB0AP);
  140. mtebc(pb0cr, CFG_EBC_PB0CR);
  141. #endif
  142. #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
  143. mtebc(pb1ap, CFG_EBC_PB1AP);
  144. mtebc(pb1cr, CFG_EBC_PB1CR);
  145. #endif
  146. #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
  147. mtebc(pb2ap, CFG_EBC_PB2AP);
  148. mtebc(pb2cr, CFG_EBC_PB2CR);
  149. #endif
  150. #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
  151. mtebc(pb3ap, CFG_EBC_PB3AP);
  152. mtebc(pb3cr, CFG_EBC_PB3CR);
  153. #endif
  154. #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
  155. mtebc(pb4ap, CFG_EBC_PB4AP);
  156. mtebc(pb4cr, CFG_EBC_PB4CR);
  157. #endif
  158. #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
  159. mtebc(pb5ap, CFG_EBC_PB5AP);
  160. mtebc(pb5cr, CFG_EBC_PB5CR);
  161. #endif
  162. #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
  163. mtebc(pb6ap, CFG_EBC_PB6AP);
  164. mtebc(pb6cr, CFG_EBC_PB6CR);
  165. #endif
  166. #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
  167. mtebc(pb7ap, CFG_EBC_PB7AP);
  168. mtebc(pb7cr, CFG_EBC_PB7CR);
  169. #endif
  170. #if defined(CONFIG_WATCHDOG)
  171. unsigned long val;
  172. val = mfspr(tcr);
  173. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  174. val |= 0xb8000000; /* generate system reset after 1.34 seconds */
  175. #else
  176. val |= 0xf0000000; /* generate system reset after 2.684 seconds */
  177. #endif
  178. mtspr(tcr, val);
  179. val = mfspr(tsr);
  180. val |= 0x80000000; /* enable watchdog timer */
  181. mtspr(tsr, val);
  182. reset_4xx_watchdog();
  183. #endif /* CONFIG_WATCHDOG */
  184. }
  185. /*
  186. * initialize higher level parts of CPU like time base and timers
  187. */
  188. int cpu_init_r (void)
  189. {
  190. #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
  191. DECLARE_GLOBAL_DATA_PTR;
  192. bd_t *bd = gd->bd;
  193. unsigned long reg;
  194. #if defined(CONFIG_405GP)
  195. uint pvr = get_pvr();
  196. #endif
  197. #ifdef CFG_INIT_DCACHE_CS
  198. /*
  199. * Flush and invalidate dcache, then disable CS for temporary stack.
  200. * Afterwards, this CS can be used for other purposes
  201. */
  202. dcache_disable(); /* flush and invalidate dcache */
  203. mtebc(PBxAP, 0);
  204. mtebc(PBxCR, 0); /* disable CS for temporary stack */
  205. #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
  206. /*
  207. * Write new value into CS register
  208. */
  209. mtebc(PBxAP, PBxAP_VAL);
  210. mtebc(PBxCR, PBxCR_VAL);
  211. #endif
  212. #endif /* CFG_INIT_DCACHE_CS */
  213. /*
  214. * Write Ethernetaddress into on-chip register
  215. */
  216. reg = 0x00000000;
  217. reg |= bd->bi_enetaddr[0]; /* set high address */
  218. reg = reg << 8;
  219. reg |= bd->bi_enetaddr[1];
  220. out32 (EMAC_IAH, reg);
  221. reg = 0x00000000;
  222. reg |= bd->bi_enetaddr[2]; /* set low address */
  223. reg = reg << 8;
  224. reg |= bd->bi_enetaddr[3];
  225. reg = reg << 8;
  226. reg |= bd->bi_enetaddr[4];
  227. reg = reg << 8;
  228. reg |= bd->bi_enetaddr[5];
  229. out32 (EMAC_IAL, reg);
  230. #if defined(CONFIG_405GP)
  231. /*
  232. * Set edge conditioning circuitry on PPC405GPr
  233. * for compatibility to existing PPC405GP designs.
  234. */
  235. if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
  236. mtdcr(ecr, 0x60606000);
  237. }
  238. #endif /* defined(CONFIG_405GP) */
  239. #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
  240. return (0);
  241. }