cpu.c 6.5 KB

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  1. /*
  2. * (C) Copyright 2000-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * CPU specific code
  25. *
  26. * written or collected and sometimes rewritten by
  27. * Magnus Damm <damm@bitsmart.com>
  28. *
  29. * minor modifications by
  30. * Wolfgang Denk <wd@denx.de>
  31. */
  32. #include <common.h>
  33. #include <watchdog.h>
  34. #include <command.h>
  35. #include <asm/cache.h>
  36. #include <ppc4xx.h>
  37. #if defined(CONFIG_440)
  38. static int do_chip_reset( unsigned long sys0, unsigned long sys1 );
  39. #endif
  40. /* ------------------------------------------------------------------------- */
  41. int checkcpu (void)
  42. {
  43. #if defined(CONFIG_405GP) || \
  44. defined(CONFIG_405CR) || \
  45. defined(CONFIG_405EP) || \
  46. defined(CONFIG_440) || \
  47. defined(CONFIG_IOP480)
  48. uint pvr = get_pvr();
  49. #endif
  50. #if defined(CONFIG_405GP) || \
  51. defined(CONFIG_405CR) || \
  52. defined(CONFIG_405EP) || \
  53. defined(CONFIG_IOP480)
  54. DECLARE_GLOBAL_DATA_PTR;
  55. ulong clock = gd->cpu_clk;
  56. char buf[32];
  57. #endif
  58. #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP)
  59. PPC405_SYS_INFO sys_info;
  60. puts ("CPU: ");
  61. get_sys_info(&sys_info);
  62. #ifdef CONFIG_405GP
  63. puts ("AMCC PowerPC 405GP");
  64. if (pvr == PVR_405GPR_RB) {
  65. putc('r');
  66. }
  67. puts (" Rev. ");
  68. #endif
  69. #ifdef CONFIG_405CR
  70. puts ("AMCC PowerPC 405CR Rev. ");
  71. #endif
  72. #ifdef CONFIG_405EP
  73. puts ("AMCC PowerPC 405EP Rev. ");
  74. #endif
  75. switch (pvr) {
  76. case PVR_405GP_RB:
  77. case PVR_405GPR_RB:
  78. putc('B');
  79. break;
  80. case PVR_405GP_RC:
  81. #ifdef CONFIG_405CR
  82. case PVR_405CR_RC:
  83. #endif
  84. putc('C');
  85. break;
  86. case PVR_405GP_RD:
  87. putc('D');
  88. break;
  89. #ifdef CONFIG_405GP
  90. case PVR_405GP_RE:
  91. putc('E');
  92. break;
  93. #endif
  94. case PVR_405CR_RA:
  95. putc('A');
  96. break;
  97. case PVR_405CR_RB:
  98. case PVR_405EP_RB:
  99. putc('B');
  100. break;
  101. default:
  102. printf ("? (PVR=%08x)", pvr);
  103. break;
  104. }
  105. printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
  106. sys_info.freqPLB / 1000000,
  107. sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
  108. sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
  109. #if defined(CONFIG_405GP)
  110. if (mfdcr(strap) & PSR_PCI_ASYNC_EN) {
  111. printf (" PCI async ext clock used, ");
  112. } else {
  113. printf (" PCI sync clock at %lu MHz, ",
  114. sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
  115. }
  116. printf ("%sternal PCI arbiter enabled\n",
  117. (mfdcr(strap) & PSR_PCI_ARBIT_EN) ? "in" : "ex");
  118. #elif defined(CONFIG_405EP)
  119. printf (" IIC Boot EEPROM %sabled\n",
  120. (mfdcr(cpc0_boot) & CPC0_BOOT_SEP) ? "en" : "dis");
  121. printf (" PCI async ext clock used, ");
  122. printf ("%sternal PCI arbiter enabled\n",
  123. (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) ? "in" : "ex");
  124. #endif
  125. #if defined(CONFIG_405EP)
  126. printf (" 16 kB I-Cache 16 kB D-Cache");
  127. #else
  128. printf (" 16 kB I-Cache %d kB D-Cache",
  129. ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
  130. #endif
  131. #endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
  132. #ifdef CONFIG_IOP480
  133. printf ("PLX IOP480 (PVR=%08x)", pvr);
  134. printf (" at %s MHz:", strmhz(buf, clock));
  135. printf (" %u kB I-Cache", 4);
  136. printf (" %u kB D-Cache", 2);
  137. #endif
  138. #if defined(CONFIG_440)
  139. puts ("AMCC PowerPC 440 ");
  140. switch(pvr) {
  141. case PVR_440GP_RB:
  142. puts("GP Rev. B");
  143. /* See errata 1.12: CHIP_4 */
  144. if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
  145. (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
  146. puts ( "\n\t CPC0_SYSx DCRs corrupted. "
  147. "Resetting chip ...\n");
  148. udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
  149. do_chip_reset ( mfdcr(cpc0_strp0),
  150. mfdcr(cpc0_strp1) );
  151. }
  152. break;
  153. case PVR_440GP_RC:
  154. puts("GP Rev. C");
  155. break;
  156. case PVR_440GX_RA:
  157. puts("GX Rev. A");
  158. break;
  159. case PVR_440GX_RB:
  160. puts("GX Rev. B");
  161. break;
  162. case PVR_440GX_RC:
  163. puts("GX Rev. C");
  164. break;
  165. #if defined(CONFIG_440_GR)
  166. case PVR_440EP_RA:
  167. puts("GR Rev. A");
  168. break;
  169. case PVR_440EP_RB:
  170. puts("GR Rev. B");
  171. break;
  172. #else
  173. case PVR_440EP_RA:
  174. puts("EP Rev. A");
  175. break;
  176. case PVR_440EP_RB:
  177. puts("EP Rev. B");
  178. break;
  179. #endif
  180. default:
  181. printf ("UNKNOWN (PVR=%08x)", pvr);
  182. break;
  183. }
  184. #endif
  185. puts ("\n");
  186. return 0;
  187. }
  188. /* ------------------------------------------------------------------------- */
  189. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  190. {
  191. #if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)
  192. /*give reset to BCSR*/
  193. *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09;
  194. #else
  195. /*
  196. * Initiate system reset in debug control register DBCR
  197. */
  198. __asm__ __volatile__("lis 3, 0x3000" ::: "r3");
  199. #if defined(CONFIG_440)
  200. __asm__ __volatile__("mtspr 0x134, 3");
  201. #else
  202. __asm__ __volatile__("mtspr 0x3f2, 3");
  203. #endif
  204. #endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/
  205. return 1;
  206. }
  207. #if defined(CONFIG_440)
  208. static
  209. int do_chip_reset (unsigned long sys0, unsigned long sys1)
  210. {
  211. /* Changes to cpc0_sys0 and cpc0_sys1 require chip
  212. * reset.
  213. */
  214. mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
  215. mtdcr (cpc0_sys0, sys0);
  216. mtdcr (cpc0_sys1, sys1);
  217. mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
  218. mtspr (dbcr0, 0x20000000); /* Reset the chip */
  219. return 1;
  220. }
  221. #endif
  222. /*
  223. * Get timebase clock frequency
  224. */
  225. unsigned long get_tbclk (void)
  226. {
  227. #if defined(CONFIG_440)
  228. sys_info_t sys_info;
  229. get_sys_info(&sys_info);
  230. return (sys_info.freqProcessor);
  231. #elif defined(CONFIG_405GP) || \
  232. defined(CONFIG_405CR) || \
  233. defined(CONFIG_405) || \
  234. defined(CONFIG_405EP)
  235. PPC405_SYS_INFO sys_info;
  236. get_sys_info(&sys_info);
  237. return (sys_info.freqProcessor);
  238. #elif defined(CONFIG_IOP480)
  239. return (66000000);
  240. #else
  241. # error get_tbclk() not implemented
  242. #endif
  243. }
  244. #if defined(CONFIG_WATCHDOG)
  245. void
  246. watchdog_reset(void)
  247. {
  248. int re_enable = disable_interrupts();
  249. reset_4xx_watchdog();
  250. if (re_enable) enable_interrupts();
  251. }
  252. void
  253. reset_4xx_watchdog(void)
  254. {
  255. /*
  256. * Clear TSR(WIS) bit
  257. */
  258. mtspr(tsr, 0x40000000);
  259. }
  260. #endif /* CONFIG_WATCHDOG */