440gx_enet.c 38 KB

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  1. /*-----------------------------------------------------------------------------+
  2. *
  3. * This source code has been made available to you by IBM on an AS-IS
  4. * basis. Anyone receiving this source is licensed under IBM
  5. * copyrights to use it in any way he or she deems fit, including
  6. * copying it, modifying it, compiling it, and redistributing it either
  7. * with or without modifications. No license under IBM patents or
  8. * patent applications is to be implied by the copyright license.
  9. *
  10. * Any user of this software should understand that IBM cannot provide
  11. * technical support for this software and will not be responsible for
  12. * any consequences resulting from the use of this software.
  13. *
  14. * Any person who transfers this source code or any derivative work
  15. * must include the IBM copyright notice, this paragraph, and the
  16. * preceding two paragraphs in the transferred software.
  17. *
  18. * COPYRIGHT I B M CORPORATION 1995
  19. * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  20. *-----------------------------------------------------------------------------*/
  21. /*-----------------------------------------------------------------------------+
  22. *
  23. * File Name: enetemac.c
  24. *
  25. * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
  26. *
  27. * Author: Mark Wisner
  28. *
  29. * Change Activity-
  30. *
  31. * Date Description of Change BY
  32. * --------- --------------------- ---
  33. * 05-May-99 Created MKW
  34. * 27-Jun-99 Clean up JWB
  35. * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
  36. * 29-Jul-99 Added Full duplex support MKW
  37. * 06-Aug-99 Changed names for Mal CR reg MKW
  38. * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
  39. * 24-Aug-99 Marked descriptor empty after call_xlc MKW
  40. * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
  41. * to avoid chaining maximum sized packets. Push starting
  42. * RX descriptor address up to the next cache line boundary.
  43. * 16-Jan-00 Added support for booting with IP of 0x0 MKW
  44. * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
  45. * EMAC_RXM register. JWB
  46. * 12-Mar-01 anne-sophie.harnois@nextream.fr
  47. * - Variables are compatible with those already defined in
  48. * include/net.h
  49. * - Receive buffer descriptor ring is used to send buffers
  50. * to the user
  51. * - Info print about send/received/handled packet number if
  52. * INFO_405_ENET is set
  53. * 17-Apr-01 stefan.roese@esd-electronics.com
  54. * - MAL reset in "eth_halt" included
  55. * - Enet speed and duplex output now in one line
  56. * 08-May-01 stefan.roese@esd-electronics.com
  57. * - MAL error handling added (eth_init called again)
  58. * 13-Nov-01 stefan.roese@esd-electronics.com
  59. * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
  60. * 04-Jan-02 stefan.roese@esd-electronics.com
  61. * - Wait for PHY auto negotiation to complete added
  62. * 06-Feb-02 stefan.roese@esd-electronics.com
  63. * - Bug fixed in waiting for auto negotiation to complete
  64. * 26-Feb-02 stefan.roese@esd-electronics.com
  65. * - rx and tx buffer descriptors now allocated (no fixed address
  66. * used anymore)
  67. * 17-Jun-02 stefan.roese@esd-electronics.com
  68. * - MAL error debug printf 'M' removed (rx de interrupt may
  69. * occur upon many incoming packets with only 4 rx buffers).
  70. *-----------------------------------------------------------------------------*
  71. * 17-Nov-03 travis.sawyer@sandburst.com
  72. * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
  73. * in the 440GX. This port should work with the 440GP
  74. * (2 EMACs) also
  75. *-----------------------------------------------------------------------------*/
  76. #include <config.h>
  77. #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
  78. #include <common.h>
  79. #include <net.h>
  80. #include <asm/processor.h>
  81. #include <ppc440.h>
  82. #include <commproc.h>
  83. #include <440gx_enet.h>
  84. #include <405_mal.h>
  85. #include <miiphy.h>
  86. #include <malloc.h>
  87. #include "vecnum.h"
  88. #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
  89. #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
  90. /* Ethernet Transmit and Receive Buffers */
  91. /* AS.HARNOIS
  92. * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
  93. * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
  94. */
  95. #define ENET_MAX_MTU PKTSIZE
  96. #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
  97. /* define the number of channels implemented */
  98. #define EMAC_RXCHL EMAC_NUM_DEV
  99. #define EMAC_TXCHL EMAC_NUM_DEV
  100. /*-----------------------------------------------------------------------------+
  101. * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
  102. * Interrupt Controller).
  103. *-----------------------------------------------------------------------------*/
  104. #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
  105. #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
  106. #define EMAC_UIC_DEF UIC_ENET
  107. #undef INFO_440_ENET
  108. #define BI_PHYMODE_NONE 0
  109. #define BI_PHYMODE_ZMII 1
  110. #define BI_PHYMODE_RGMII 2
  111. /*-----------------------------------------------------------------------------+
  112. * Global variables. TX and RX descriptors and buffers.
  113. *-----------------------------------------------------------------------------*/
  114. /* IER globals */
  115. static uint32_t mal_ier;
  116. /*-----------------------------------------------------------------------------+
  117. * Prototypes and externals.
  118. *-----------------------------------------------------------------------------*/
  119. static void enet_rcv (struct eth_device *dev, unsigned long malisr);
  120. int enetInt (struct eth_device *dev);
  121. static void mal_err (struct eth_device *dev, unsigned long isr,
  122. unsigned long uic, unsigned long maldef,
  123. unsigned long mal_errr);
  124. static void emac_err (struct eth_device *dev, unsigned long isr);
  125. /*-----------------------------------------------------------------------------+
  126. | ppc_440x_eth_halt
  127. | Disable MAL channel, and EMACn
  128. |
  129. |
  130. +-----------------------------------------------------------------------------*/
  131. static void ppc_440x_eth_halt (struct eth_device *dev)
  132. {
  133. EMAC_440GX_HW_PST hw_p = dev->priv;
  134. uint32_t failsafe = 10000;
  135. out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
  136. /* 1st reset MAL channel */
  137. /* Note: writing a 0 to a channel has no effect */
  138. mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
  139. mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
  140. /* wait for reset */
  141. while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
  142. udelay (1000); /* Delay 1 MS so as not to hammer the register */
  143. failsafe--;
  144. if (failsafe == 0)
  145. break;
  146. }
  147. /* EMAC RESET */
  148. out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
  149. hw_p->print_speed = 1; /* print speed message again next time */
  150. return;
  151. }
  152. extern int phy_setup_aneg (unsigned char addr);
  153. extern int miiphy_reset (unsigned char addr);
  154. #if defined (CONFIG_440_GX)
  155. int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
  156. {
  157. unsigned long pfc1;
  158. unsigned long zmiifer;
  159. unsigned long rmiifer;
  160. mfsdr(sdr_pfc1, pfc1);
  161. pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
  162. zmiifer = 0;
  163. rmiifer = 0;
  164. switch (pfc1) {
  165. case 1:
  166. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  167. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
  168. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
  169. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
  170. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  171. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  172. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  173. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  174. break;
  175. case 2:
  176. zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
  177. zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
  178. zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
  179. zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
  180. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  181. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  182. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  183. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  184. break;
  185. case 3:
  186. zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
  187. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  188. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  189. bis->bi_phymode[1] = BI_PHYMODE_NONE;
  190. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  191. bis->bi_phymode[3] = BI_PHYMODE_NONE;
  192. break;
  193. case 4:
  194. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
  195. zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
  196. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
  197. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
  198. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  199. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  200. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  201. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  202. break;
  203. case 5:
  204. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  205. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  206. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
  207. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
  208. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  209. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  210. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  211. bis->bi_phymode[3] = BI_PHYMODE_RGMII;
  212. break;
  213. case 6:
  214. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
  215. zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
  216. rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
  217. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  218. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  219. bis->bi_phymode[2] = BI_PHYMODE_RGMII;
  220. break;
  221. case 0:
  222. default:
  223. zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
  224. rmiifer = 0x0;
  225. bis->bi_phymode[0] = BI_PHYMODE_ZMII;
  226. bis->bi_phymode[1] = BI_PHYMODE_ZMII;
  227. bis->bi_phymode[2] = BI_PHYMODE_ZMII;
  228. bis->bi_phymode[3] = BI_PHYMODE_ZMII;
  229. break;
  230. }
  231. /* Ensure we setup mdio for this devnum and ONLY this devnum */
  232. zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
  233. out32 (ZMII_FER, zmiifer);
  234. out32 (RGMII_FER, rmiifer);
  235. return ((int)pfc1);
  236. }
  237. #endif
  238. static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
  239. {
  240. int i;
  241. unsigned long reg;
  242. unsigned long msr;
  243. unsigned long speed;
  244. unsigned long duplex;
  245. unsigned long failsafe;
  246. unsigned mode_reg;
  247. unsigned short devnum;
  248. unsigned short reg_short;
  249. sys_info_t sysinfo;
  250. #if defined(CONFIG_440_GX)
  251. int ethgroup;
  252. #endif
  253. EMAC_440GX_HW_PST hw_p = dev->priv;
  254. /* before doing anything, figure out if we have a MAC address */
  255. /* if not, bail */
  256. if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
  257. return -1;
  258. /* Need to get the OPB frequency so we can access the PHY */
  259. get_sys_info (&sysinfo);
  260. msr = mfmsr ();
  261. mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
  262. devnum = hw_p->devnum;
  263. #ifdef INFO_440_ENET
  264. /* AS.HARNOIS
  265. * We should have :
  266. * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
  267. * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
  268. * is possible that new packets (without relationship with
  269. * current transfer) have got the time to arrived before
  270. * netloop calls eth_halt
  271. */
  272. printf ("About preceeding transfer (eth%d):\n"
  273. "- Sent packet number %d\n"
  274. "- Received packet number %d\n"
  275. "- Handled packet number %d\n",
  276. hw_p->devnum,
  277. hw_p->stats.pkts_tx,
  278. hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
  279. hw_p->stats.pkts_tx = 0;
  280. hw_p->stats.pkts_rx = 0;
  281. hw_p->stats.pkts_handled = 0;
  282. #endif
  283. /* MAL Channel RESET */
  284. /* 1st reset MAL channel */
  285. /* Note: writing a 0 to a channel has no effect */
  286. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  287. mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
  288. #else
  289. mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
  290. #endif
  291. mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
  292. /* wait for reset */
  293. /* TBS: should have udelay and failsafe here */
  294. failsafe = 10000;
  295. /* wait for reset */
  296. while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
  297. udelay (1000); /* Delay 1 MS so as not to hammer the register */
  298. failsafe--;
  299. if (failsafe == 0)
  300. break;
  301. }
  302. hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
  303. hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
  304. hw_p->rx_slot = 0; /* MAL Receive Slot */
  305. hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
  306. hw_p->rx_u_index = 0; /* Receive User Queue Index */
  307. hw_p->tx_slot = 0; /* MAL Transmit Slot */
  308. hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
  309. hw_p->tx_u_index = 0; /* Transmit User Queue Index */
  310. /* set RMII mode */
  311. /* NOTE: 440GX spec states that mode is mutually exclusive */
  312. /* NOTE: Therefore, disable all other EMACS, since we handle */
  313. /* NOTE: only one emac at a time */
  314. reg = 0;
  315. out32 (ZMII_FER, 0);
  316. udelay (100);
  317. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  318. out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
  319. #elif defined(CONFIG_440_GX)
  320. ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
  321. #else
  322. if ((devnum == 0) || (devnum == 1)) {
  323. out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
  324. }
  325. else { /* ((devnum == 2) || (devnum == 3)) */
  326. out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
  327. out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
  328. (RGMII_FER_RGMII << RGMII_FER_V (3))));
  329. }
  330. #endif
  331. out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
  332. __asm__ volatile ("eieio");
  333. /* reset emac so we have access to the phy */
  334. out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
  335. __asm__ volatile ("eieio");
  336. failsafe = 1000;
  337. while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
  338. udelay (1000);
  339. failsafe--;
  340. }
  341. /* Whack the M1 register */
  342. mode_reg = 0x0;
  343. mode_reg &= ~0x00000038;
  344. if (sysinfo.freqOPB <= 50000000);
  345. else if (sysinfo.freqOPB <= 66666667)
  346. mode_reg |= EMAC_M1_OBCI_66;
  347. else if (sysinfo.freqOPB <= 83333333)
  348. mode_reg |= EMAC_M1_OBCI_83;
  349. else if (sysinfo.freqOPB <= 100000000)
  350. mode_reg |= EMAC_M1_OBCI_100;
  351. else
  352. mode_reg |= EMAC_M1_OBCI_GT100;
  353. out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
  354. /* wait for PHY to complete auto negotiation */
  355. reg_short = 0;
  356. #ifndef CONFIG_CS8952_PHY
  357. switch (devnum) {
  358. case 0:
  359. reg = CONFIG_PHY_ADDR;
  360. break;
  361. case 1:
  362. reg = CONFIG_PHY1_ADDR;
  363. break;
  364. #if defined (CONFIG_440_GX)
  365. case 2:
  366. reg = CONFIG_PHY2_ADDR;
  367. break;
  368. case 3:
  369. reg = CONFIG_PHY3_ADDR;
  370. break;
  371. #endif
  372. default:
  373. reg = CONFIG_PHY_ADDR;
  374. break;
  375. }
  376. bis->bi_phynum[devnum] = reg;
  377. /*
  378. * Reset the phy, only if its the first time through
  379. * otherwise, just check the speeds & feeds
  380. */
  381. if (hw_p->first_init == 0) {
  382. miiphy_reset (reg);
  383. #if defined(CONFIG_440_GX)
  384. #if defined(CONFIG_CIS8201_PHY)
  385. /*
  386. * Cicada 8201 PHY needs to have an extended register whacked
  387. * for RGMII mode.
  388. */
  389. if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
  390. miiphy_write (reg, 23, 0x1200);
  391. /*
  392. * Vitesse VSC8201/Cicada CIS8201 errata:
  393. * Interoperability problem with Intel 82547EI phys
  394. * This work around (provided by Vitesse) changes
  395. * the default timer convergence from 8ms to 12ms
  396. */
  397. miiphy_write (reg, 0x1f, 0x2a30);
  398. miiphy_write (reg, 0x08, 0x0200);
  399. miiphy_write (reg, 0x1f, 0x52b5);
  400. miiphy_write (reg, 0x02, 0x0004);
  401. miiphy_write (reg, 0x01, 0x0671);
  402. miiphy_write (reg, 0x00, 0x8fae);
  403. miiphy_write (reg, 0x1f, 0x2a30);
  404. miiphy_write (reg, 0x08, 0x0000);
  405. miiphy_write (reg, 0x1f, 0x0000);
  406. /* end Vitesse/Cicada errata */
  407. }
  408. #endif
  409. #endif
  410. /* Start/Restart autonegotiation */
  411. phy_setup_aneg (reg);
  412. udelay (1000);
  413. }
  414. miiphy_read (reg, PHY_BMSR, &reg_short);
  415. /*
  416. * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
  417. */
  418. if ((reg_short & PHY_BMSR_AUTN_ABLE)
  419. && !(reg_short & PHY_BMSR_AUTN_COMP)) {
  420. puts ("Waiting for PHY auto negotiation to complete");
  421. i = 0;
  422. while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
  423. /*
  424. * Timeout reached ?
  425. */
  426. if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
  427. puts (" TIMEOUT !\n");
  428. break;
  429. }
  430. if ((i++ % 1000) == 0) {
  431. putc ('.');
  432. }
  433. udelay (1000); /* 1 ms */
  434. miiphy_read (reg, PHY_BMSR, &reg_short);
  435. }
  436. puts (" done\n");
  437. udelay (500000); /* another 500 ms (results in faster booting) */
  438. }
  439. #endif
  440. speed = miiphy_speed (reg);
  441. duplex = miiphy_duplex (reg);
  442. if (hw_p->print_speed) {
  443. hw_p->print_speed = 0;
  444. printf ("ENET Speed is %d Mbps - %s duplex connection\n",
  445. (int) speed, (duplex == HALF) ? "HALF" : "FULL");
  446. }
  447. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  448. mfsdr(sdr_mfr, reg);
  449. if (speed == 100) {
  450. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
  451. } else {
  452. reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
  453. }
  454. mtsdr(sdr_mfr, reg);
  455. #endif
  456. /* Set ZMII/RGMII speed according to the phy link speed */
  457. reg = in32 (ZMII_SSR);
  458. if ( (speed == 100) || (speed == 1000) )
  459. out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
  460. else
  461. out32 (ZMII_SSR,
  462. reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
  463. if ((devnum == 2) || (devnum == 3)) {
  464. if (speed == 1000)
  465. reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
  466. else if (speed == 100)
  467. reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
  468. else
  469. reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
  470. out32 (RGMII_SSR, reg);
  471. }
  472. /* set the Mal configuration reg */
  473. /* Errata 1.12: MAL_1 -- Disable MAL bursting */
  474. if (get_pvr () == PVR_440GP_RB)
  475. mtdcr (malmcr,
  476. MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
  477. else
  478. mtdcr (malmcr,
  479. MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
  480. MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
  481. /* Free "old" buffers */
  482. if (hw_p->alloc_tx_buf)
  483. free (hw_p->alloc_tx_buf);
  484. if (hw_p->alloc_rx_buf)
  485. free (hw_p->alloc_rx_buf);
  486. /*
  487. * Malloc MAL buffer desciptors, make sure they are
  488. * aligned on cache line boundary size
  489. * (401/403/IOP480 = 16, 405 = 32)
  490. * and doesn't cross cache block boundaries.
  491. */
  492. hw_p->alloc_tx_buf =
  493. (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
  494. ((2 * CFG_CACHELINE_SIZE) - 2));
  495. if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
  496. hw_p->tx =
  497. (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
  498. CFG_CACHELINE_SIZE -
  499. ((int) hw_p->
  500. alloc_tx_buf & CACHELINE_MASK));
  501. } else {
  502. hw_p->tx = hw_p->alloc_tx_buf;
  503. }
  504. hw_p->alloc_rx_buf =
  505. (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
  506. ((2 * CFG_CACHELINE_SIZE) - 2));
  507. if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
  508. hw_p->rx =
  509. (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
  510. CFG_CACHELINE_SIZE -
  511. ((int) hw_p->
  512. alloc_rx_buf & CACHELINE_MASK));
  513. } else {
  514. hw_p->rx = hw_p->alloc_rx_buf;
  515. }
  516. for (i = 0; i < NUM_TX_BUFF; i++) {
  517. hw_p->tx[i].ctrl = 0;
  518. hw_p->tx[i].data_len = 0;
  519. if (hw_p->first_init == 0)
  520. hw_p->txbuf_ptr =
  521. (char *) malloc (ENET_MAX_MTU_ALIGNED);
  522. hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
  523. if ((NUM_TX_BUFF - 1) == i)
  524. hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
  525. hw_p->tx_run[i] = -1;
  526. #if 0
  527. printf ("TX_BUFF %d @ 0x%08lx\n", i,
  528. (ulong) hw_p->tx[i].data_ptr);
  529. #endif
  530. }
  531. for (i = 0; i < NUM_RX_BUFF; i++) {
  532. hw_p->rx[i].ctrl = 0;
  533. hw_p->rx[i].data_len = 0;
  534. /* rx[i].data_ptr = (char *) &rx_buff[i]; */
  535. hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
  536. if ((NUM_RX_BUFF - 1) == i)
  537. hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
  538. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
  539. hw_p->rx_ready[i] = -1;
  540. #if 0
  541. printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
  542. #endif
  543. }
  544. reg = 0x00000000;
  545. reg |= dev->enetaddr[0]; /* set high address */
  546. reg = reg << 8;
  547. reg |= dev->enetaddr[1];
  548. out32 (EMAC_IAH + hw_p->hw_addr, reg);
  549. reg = 0x00000000;
  550. reg |= dev->enetaddr[2]; /* set low address */
  551. reg = reg << 8;
  552. reg |= dev->enetaddr[3];
  553. reg = reg << 8;
  554. reg |= dev->enetaddr[4];
  555. reg = reg << 8;
  556. reg |= dev->enetaddr[5];
  557. out32 (EMAC_IAL + hw_p->hw_addr, reg);
  558. switch (devnum) {
  559. case 1:
  560. /* setup MAL tx & rx channel pointers */
  561. #if defined (CONFIG_440_EP) || defined (CONFIG_440_GR)
  562. mtdcr (maltxctp2r, hw_p->tx);
  563. #else
  564. mtdcr (maltxctp1r, hw_p->tx);
  565. #endif
  566. mtdcr (maltxbattr, 0x0);
  567. mtdcr (malrxbattr, 0x0);
  568. mtdcr (malrxctp1r, hw_p->rx);
  569. /* set RX buffer size */
  570. mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
  571. break;
  572. #if defined (CONFIG_440_GX)
  573. case 2:
  574. /* setup MAL tx & rx channel pointers */
  575. mtdcr (maltxbattr, 0x0);
  576. mtdcr (maltxctp2r, hw_p->tx);
  577. mtdcr (malrxbattr, 0x0);
  578. mtdcr (malrxctp2r, hw_p->rx);
  579. /* set RX buffer size */
  580. mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
  581. break;
  582. case 3:
  583. /* setup MAL tx & rx channel pointers */
  584. mtdcr (maltxbattr, 0x0);
  585. mtdcr (maltxctp3r, hw_p->tx);
  586. mtdcr (malrxbattr, 0x0);
  587. mtdcr (malrxctp3r, hw_p->rx);
  588. /* set RX buffer size */
  589. mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
  590. break;
  591. #endif /*CONFIG_440_GX */
  592. case 0:
  593. default:
  594. /* setup MAL tx & rx channel pointers */
  595. mtdcr (maltxbattr, 0x0);
  596. mtdcr (maltxctp0r, hw_p->tx);
  597. mtdcr (malrxbattr, 0x0);
  598. mtdcr (malrxctp0r, hw_p->rx);
  599. /* set RX buffer size */
  600. mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
  601. break;
  602. }
  603. /* Enable MAL transmit and receive channels */
  604. #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
  605. mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
  606. #else
  607. mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
  608. #endif
  609. mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
  610. /* set transmit enable & receive enable */
  611. out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
  612. /* set receive fifo to 4k and tx fifo to 2k */
  613. mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
  614. mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
  615. /* set speed */
  616. if (speed == _1000BASET)
  617. mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
  618. else if (speed == _100BASET)
  619. mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
  620. else
  621. mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
  622. if (duplex == FULL)
  623. mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
  624. out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
  625. /* Enable broadcast and indvidual address */
  626. /* TBS: enabling runts as some misbehaved nics will send runts */
  627. out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
  628. /* we probably need to set the tx mode1 reg? maybe at tx time */
  629. /* set transmit request threshold register */
  630. out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
  631. /* set receive low/high water mark register */
  632. /* 440GP has a 64 byte burst length */
  633. out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
  634. out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
  635. /* Set fifo limit entry in tx mode 0 */
  636. out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
  637. /* Frame gap set */
  638. out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
  639. /* Set EMAC IER */
  640. hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
  641. EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
  642. if (speed == _100BASET)
  643. hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
  644. out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
  645. out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
  646. if (hw_p->first_init == 0) {
  647. /*
  648. * Connect interrupt service routines
  649. */
  650. irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
  651. (interrupt_handler_t *) enetInt, dev);
  652. irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
  653. (interrupt_handler_t *) enetInt, dev);
  654. }
  655. mtmsr (msr); /* enable interrupts again */
  656. hw_p->bis = bis;
  657. hw_p->first_init = 1;
  658. return (1);
  659. }
  660. static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
  661. int len)
  662. {
  663. struct enet_frame *ef_ptr;
  664. ulong time_start, time_now;
  665. unsigned long temp_txm0;
  666. EMAC_440GX_HW_PST hw_p = dev->priv;
  667. ef_ptr = (struct enet_frame *) ptr;
  668. /*-----------------------------------------------------------------------+
  669. * Copy in our address into the frame.
  670. *-----------------------------------------------------------------------*/
  671. (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
  672. /*-----------------------------------------------------------------------+
  673. * If frame is too long or too short, modify length.
  674. *-----------------------------------------------------------------------*/
  675. /* TBS: where does the fragment go???? */
  676. if (len > ENET_MAX_MTU)
  677. len = ENET_MAX_MTU;
  678. /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
  679. memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
  680. /*-----------------------------------------------------------------------+
  681. * set TX Buffer busy, and send it
  682. *-----------------------------------------------------------------------*/
  683. hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
  684. EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
  685. ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
  686. if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
  687. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
  688. hw_p->tx[hw_p->tx_slot].data_len = (short) len;
  689. hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
  690. __asm__ volatile ("eieio");
  691. out32 (EMAC_TXM0 + hw_p->hw_addr,
  692. in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
  693. #ifdef INFO_440_ENET
  694. hw_p->stats.pkts_tx++;
  695. #endif
  696. /*-----------------------------------------------------------------------+
  697. * poll unitl the packet is sent and then make sure it is OK
  698. *-----------------------------------------------------------------------*/
  699. time_start = get_timer (0);
  700. while (1) {
  701. temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
  702. /* loop until either TINT turns on or 3 seconds elapse */
  703. if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
  704. /* transmit is done, so now check for errors
  705. * If there is an error, an interrupt should
  706. * happen when we return
  707. */
  708. time_now = get_timer (0);
  709. if ((time_now - time_start) > 3000) {
  710. return (-1);
  711. }
  712. } else {
  713. return (len);
  714. }
  715. }
  716. }
  717. int enetInt (struct eth_device *dev)
  718. {
  719. int serviced;
  720. int rc = -1; /* default to not us */
  721. unsigned long mal_isr;
  722. unsigned long emac_isr = 0;
  723. unsigned long mal_rx_eob;
  724. unsigned long my_uic0msr, my_uic1msr;
  725. #if defined(CONFIG_440_GX)
  726. unsigned long my_uic2msr;
  727. #endif
  728. EMAC_440GX_HW_PST hw_p;
  729. /*
  730. * Because the mal is generic, we need to get the current
  731. * eth device
  732. */
  733. dev = eth_get_dev ();
  734. hw_p = dev->priv;
  735. /* enter loop that stays in interrupt code until nothing to service */
  736. do {
  737. serviced = 0;
  738. my_uic0msr = mfdcr (uic0msr);
  739. my_uic1msr = mfdcr (uic1msr);
  740. #if defined(CONFIG_440_GX)
  741. my_uic2msr = mfdcr (uic2msr);
  742. #endif
  743. if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
  744. && !(my_uic1msr &
  745. (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
  746. UIC_MRDE))) {
  747. /* not for us */
  748. return (rc);
  749. }
  750. #if defined (CONFIG_440_GX)
  751. if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
  752. && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
  753. /* not for us */
  754. return (rc);
  755. }
  756. #endif
  757. /* get and clear controller status interrupts */
  758. /* look at Mal and EMAC interrupts */
  759. if ((my_uic0msr & (UIC_MRE | UIC_MTE))
  760. || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
  761. /* we have a MAL interrupt */
  762. mal_isr = mfdcr (malesr);
  763. /* look for mal error */
  764. if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
  765. mal_err (dev, mal_isr, my_uic0msr,
  766. MAL_UIC_DEF, MAL_UIC_ERR);
  767. serviced = 1;
  768. rc = 0;
  769. }
  770. }
  771. /* port by port dispatch of emac interrupts */
  772. if (hw_p->devnum == 0) {
  773. if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
  774. emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
  775. if ((hw_p->emac_ier & emac_isr) != 0) {
  776. emac_err (dev, emac_isr);
  777. serviced = 1;
  778. rc = 0;
  779. }
  780. }
  781. if ((hw_p->emac_ier & emac_isr)
  782. || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
  783. mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
  784. mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
  785. return (rc); /* we had errors so get out */
  786. }
  787. }
  788. if (hw_p->devnum == 1) {
  789. if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
  790. emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
  791. if ((hw_p->emac_ier & emac_isr) != 0) {
  792. emac_err (dev, emac_isr);
  793. serviced = 1;
  794. rc = 0;
  795. }
  796. }
  797. if ((hw_p->emac_ier & emac_isr)
  798. || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
  799. mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
  800. mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
  801. return (rc); /* we had errors so get out */
  802. }
  803. }
  804. #if defined (CONFIG_440_GX)
  805. if (hw_p->devnum == 2) {
  806. if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
  807. emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
  808. if ((hw_p->emac_ier & emac_isr) != 0) {
  809. emac_err (dev, emac_isr);
  810. serviced = 1;
  811. rc = 0;
  812. }
  813. }
  814. if ((hw_p->emac_ier & emac_isr)
  815. || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
  816. mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
  817. mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
  818. mtdcr (uic2sr, UIC_ETH2);
  819. return (rc); /* we had errors so get out */
  820. }
  821. }
  822. if (hw_p->devnum == 3) {
  823. if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
  824. emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
  825. if ((hw_p->emac_ier & emac_isr) != 0) {
  826. emac_err (dev, emac_isr);
  827. serviced = 1;
  828. rc = 0;
  829. }
  830. }
  831. if ((hw_p->emac_ier & emac_isr)
  832. || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
  833. mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
  834. mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
  835. mtdcr (uic2sr, UIC_ETH3);
  836. return (rc); /* we had errors so get out */
  837. }
  838. }
  839. #endif /* CONFIG_440_GX */
  840. /* handle MAX TX EOB interrupt from a tx */
  841. if (my_uic0msr & UIC_MTE) {
  842. mal_rx_eob = mfdcr (maltxeobisr);
  843. mtdcr (maltxeobisr, mal_rx_eob);
  844. mtdcr (uic0sr, UIC_MTE);
  845. }
  846. /* handle MAL RX EOB interupt from a receive */
  847. /* check for EOB on valid channels */
  848. if (my_uic0msr & UIC_MRE) {
  849. mal_rx_eob = mfdcr (malrxeobisr);
  850. if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
  851. /* clear EOB
  852. mtdcr(malrxeobisr, mal_rx_eob); */
  853. enet_rcv (dev, emac_isr);
  854. /* indicate that we serviced an interrupt */
  855. serviced = 1;
  856. rc = 0;
  857. }
  858. }
  859. mtdcr (uic0sr, UIC_MRE); /* Clear */
  860. mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
  861. switch (hw_p->devnum) {
  862. case 0:
  863. mtdcr (uic1sr, UIC_ETH0);
  864. break;
  865. case 1:
  866. mtdcr (uic1sr, UIC_ETH1);
  867. break;
  868. #if defined (CONFIG_440_GX)
  869. case 2:
  870. mtdcr (uic2sr, UIC_ETH2);
  871. break;
  872. case 3:
  873. mtdcr (uic2sr, UIC_ETH3);
  874. break;
  875. #endif /* CONFIG_440_GX */
  876. default:
  877. break;
  878. }
  879. } while (serviced);
  880. return (rc);
  881. }
  882. /*-----------------------------------------------------------------------------+
  883. * MAL Error Routine
  884. *-----------------------------------------------------------------------------*/
  885. static void mal_err (struct eth_device *dev, unsigned long isr,
  886. unsigned long uic, unsigned long maldef,
  887. unsigned long mal_errr)
  888. {
  889. EMAC_440GX_HW_PST hw_p = dev->priv;
  890. mtdcr (malesr, isr); /* clear interrupt */
  891. /* clear DE interrupt */
  892. mtdcr (maltxdeir, 0xC0000000);
  893. mtdcr (malrxdeir, 0x80000000);
  894. #ifdef INFO_440_ENET
  895. printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
  896. #endif
  897. eth_init (hw_p->bis); /* start again... */
  898. }
  899. /*-----------------------------------------------------------------------------+
  900. * EMAC Error Routine
  901. *-----------------------------------------------------------------------------*/
  902. static void emac_err (struct eth_device *dev, unsigned long isr)
  903. {
  904. EMAC_440GX_HW_PST hw_p = dev->priv;
  905. printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
  906. out32 (EMAC_ISR + hw_p->hw_addr, isr);
  907. }
  908. /*-----------------------------------------------------------------------------+
  909. * enet_rcv() handles the ethernet receive data
  910. *-----------------------------------------------------------------------------*/
  911. static void enet_rcv (struct eth_device *dev, unsigned long malisr)
  912. {
  913. struct enet_frame *ef_ptr;
  914. unsigned long data_len;
  915. unsigned long rx_eob_isr;
  916. EMAC_440GX_HW_PST hw_p = dev->priv;
  917. int handled = 0;
  918. int i;
  919. int loop_count = 0;
  920. rx_eob_isr = mfdcr (malrxeobisr);
  921. if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
  922. /* clear EOB */
  923. mtdcr (malrxeobisr, rx_eob_isr);
  924. /* EMAC RX done */
  925. while (1) { /* do all */
  926. i = hw_p->rx_slot;
  927. if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
  928. || (loop_count >= NUM_RX_BUFF))
  929. break;
  930. loop_count++;
  931. hw_p->rx_slot++;
  932. if (NUM_RX_BUFF == hw_p->rx_slot)
  933. hw_p->rx_slot = 0;
  934. handled++;
  935. data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
  936. if (data_len) {
  937. if (data_len > ENET_MAX_MTU) /* Check len */
  938. data_len = 0;
  939. else {
  940. if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
  941. data_len = 0;
  942. hw_p->stats.rx_err_log[hw_p->
  943. rx_err_index]
  944. = hw_p->rx[i].ctrl;
  945. hw_p->rx_err_index++;
  946. if (hw_p->rx_err_index ==
  947. MAX_ERR_LOG)
  948. hw_p->rx_err_index =
  949. 0;
  950. } /* emac_erros */
  951. } /* data_len < max mtu */
  952. } /* if data_len */
  953. if (!data_len) { /* no data */
  954. hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
  955. hw_p->stats.data_len_err++; /* Error at Rx */
  956. }
  957. /* !data_len */
  958. /* AS.HARNOIS */
  959. /* Check if user has already eaten buffer */
  960. /* if not => ERROR */
  961. else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
  962. if (hw_p->is_receiving)
  963. printf ("ERROR : Receive buffers are full!\n");
  964. break;
  965. } else {
  966. hw_p->stats.rx_frames++;
  967. hw_p->stats.rx += data_len;
  968. ef_ptr = (struct enet_frame *) hw_p->rx[i].
  969. data_ptr;
  970. #ifdef INFO_440_ENET
  971. hw_p->stats.pkts_rx++;
  972. #endif
  973. /* AS.HARNOIS
  974. * use ring buffer
  975. */
  976. hw_p->rx_ready[hw_p->rx_i_index] = i;
  977. hw_p->rx_i_index++;
  978. if (NUM_RX_BUFF == hw_p->rx_i_index)
  979. hw_p->rx_i_index = 0;
  980. /* printf("X"); /|* test-only *|/ */
  981. /* AS.HARNOIS
  982. * free receive buffer only when
  983. * buffer has been handled (eth_rx)
  984. rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
  985. */
  986. } /* if data_len */
  987. } /* while */
  988. } /* if EMACK_RXCHL */
  989. }
  990. static int ppc_440x_eth_rx (struct eth_device *dev)
  991. {
  992. int length;
  993. int user_index;
  994. unsigned long msr;
  995. EMAC_440GX_HW_PST hw_p = dev->priv;
  996. hw_p->is_receiving = 1; /* tell driver */
  997. for (;;) {
  998. /* AS.HARNOIS
  999. * use ring buffer and
  1000. * get index from rx buffer desciptor queue
  1001. */
  1002. user_index = hw_p->rx_ready[hw_p->rx_u_index];
  1003. if (user_index == -1) {
  1004. length = -1;
  1005. break; /* nothing received - leave for() loop */
  1006. }
  1007. msr = mfmsr ();
  1008. mtmsr (msr & ~(MSR_EE));
  1009. length = hw_p->rx[user_index].data_len;
  1010. /* Pass the packet up to the protocol layers. */
  1011. /* NetReceive(NetRxPackets[rxIdx], length - 4); */
  1012. /* NetReceive(NetRxPackets[i], length); */
  1013. NetReceive (NetRxPackets[user_index], length - 4);
  1014. /* Free Recv Buffer */
  1015. hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
  1016. /* Free rx buffer descriptor queue */
  1017. hw_p->rx_ready[hw_p->rx_u_index] = -1;
  1018. hw_p->rx_u_index++;
  1019. if (NUM_RX_BUFF == hw_p->rx_u_index)
  1020. hw_p->rx_u_index = 0;
  1021. #ifdef INFO_440_ENET
  1022. hw_p->stats.pkts_handled++;
  1023. #endif
  1024. mtmsr (msr); /* Enable IRQ's */
  1025. }
  1026. hw_p->is_receiving = 0; /* tell driver */
  1027. return length;
  1028. }
  1029. int ppc_440x_eth_initialize (bd_t * bis)
  1030. {
  1031. static int virgin = 0;
  1032. struct eth_device *dev;
  1033. int eth_num = 0;
  1034. EMAC_440GX_HW_PST hw = NULL;
  1035. #if defined(CONFIG_440_GX)
  1036. unsigned long pfc1;
  1037. mfsdr (sdr_pfc1, pfc1);
  1038. pfc1 &= ~(0x01e00000);
  1039. pfc1 |= 0x01200000;
  1040. mtsdr (sdr_pfc1, pfc1);
  1041. #endif
  1042. /* set phy num and mode */
  1043. bis->bi_phynum[0] = CONFIG_PHY_ADDR;
  1044. #if defined(CONFIG_PHY1_ADDR)
  1045. bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
  1046. #endif
  1047. #if defined(CONFIG_440_GX)
  1048. bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
  1049. bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
  1050. bis->bi_phymode[0] = 0;
  1051. bis->bi_phymode[1] = 0;
  1052. bis->bi_phymode[2] = 2;
  1053. bis->bi_phymode[3] = 2;
  1054. #if defined (CONFIG_440_GX)
  1055. ppc_440x_eth_setup_bridge(0, bis);
  1056. #endif
  1057. #endif
  1058. for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
  1059. /* See if we can actually bring up the interface, otherwise, skip it */
  1060. switch (eth_num) {
  1061. default: /* fall through */
  1062. case 0:
  1063. if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
  1064. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1065. continue;
  1066. }
  1067. break;
  1068. #ifdef CONFIG_HAS_ETH1
  1069. case 1:
  1070. if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
  1071. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1072. continue;
  1073. }
  1074. break;
  1075. #endif
  1076. #ifdef CONFIG_HAS_ETH2
  1077. case 2:
  1078. if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
  1079. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1080. continue;
  1081. }
  1082. break;
  1083. #endif
  1084. #ifdef CONFIG_HAS_ETH3
  1085. case 3:
  1086. if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
  1087. bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
  1088. continue;
  1089. }
  1090. break;
  1091. #endif
  1092. }
  1093. /* Allocate device structure */
  1094. dev = (struct eth_device *) malloc (sizeof (*dev));
  1095. if (dev == NULL) {
  1096. printf ("ppc_440x_eth_initialize: "
  1097. "Cannot allocate eth_device %d\n", eth_num);
  1098. return (-1);
  1099. }
  1100. memset(dev, 0, sizeof(*dev));
  1101. /* Allocate our private use data */
  1102. hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
  1103. if (hw == NULL) {
  1104. printf ("ppc_440x_eth_initialize: "
  1105. "Cannot allocate private hw data for eth_device %d",
  1106. eth_num);
  1107. free (dev);
  1108. return (-1);
  1109. }
  1110. memset(hw, 0, sizeof(*hw));
  1111. switch (eth_num) {
  1112. default: /* fall through */
  1113. case 0:
  1114. hw->hw_addr = 0;
  1115. memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
  1116. break;
  1117. #ifdef CONFIG_HAS_ETH1
  1118. case 1:
  1119. hw->hw_addr = 0x100;
  1120. memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
  1121. break;
  1122. #endif
  1123. #ifdef CONFIG_HAS_ETH2
  1124. case 2:
  1125. hw->hw_addr = 0x400;
  1126. memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
  1127. break;
  1128. #endif
  1129. #ifdef CONFIG_HAS_ETH3
  1130. case 3:
  1131. hw->hw_addr = 0x600;
  1132. memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
  1133. break;
  1134. #endif
  1135. }
  1136. hw->devnum = eth_num;
  1137. hw->print_speed = 1;
  1138. sprintf (dev->name, "ppc_440x_eth%d", eth_num);
  1139. dev->priv = (void *) hw;
  1140. dev->init = ppc_440x_eth_init;
  1141. dev->halt = ppc_440x_eth_halt;
  1142. dev->send = ppc_440x_eth_send;
  1143. dev->recv = ppc_440x_eth_rx;
  1144. if (0 == virgin) {
  1145. /* set the MAL IER ??? names may change with new spec ??? */
  1146. mal_ier =
  1147. MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
  1148. MAL_IER_OPBE | MAL_IER_PLBE;
  1149. mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
  1150. mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
  1151. mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
  1152. mtdcr (malier, mal_ier);
  1153. /* install MAL interrupt handler */
  1154. irq_install_handler (VECNUM_MS,
  1155. (interrupt_handler_t *) enetInt,
  1156. dev);
  1157. irq_install_handler (VECNUM_MTE,
  1158. (interrupt_handler_t *) enetInt,
  1159. dev);
  1160. irq_install_handler (VECNUM_MRE,
  1161. (interrupt_handler_t *) enetInt,
  1162. dev);
  1163. irq_install_handler (VECNUM_TXDE,
  1164. (interrupt_handler_t *) enetInt,
  1165. dev);
  1166. irq_install_handler (VECNUM_RXDE,
  1167. (interrupt_handler_t *) enetInt,
  1168. dev);
  1169. virgin = 1;
  1170. }
  1171. eth_register (dev);
  1172. } /* end for each supported device */
  1173. return (1);
  1174. }
  1175. #endif /* CONFIG_440 && CONFIG_NET_MULTI */