yellowstone.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426
  1. /*
  2. *
  3. * See file CREDITS for list of people who contributed to this
  4. * project.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #include <common.h>
  22. #include <asm/processor.h>
  23. #include <spd_sdram.h>
  24. int board_early_init_f(void)
  25. {
  26. register uint reg;
  27. /*--------------------------------------------------------------------
  28. * Setup the external bus controller/chip selects
  29. *-------------------------------------------------------------------*/
  30. mtdcr(ebccfga, xbcfg);
  31. reg = mfdcr(ebccfgd);
  32. mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
  33. mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
  34. mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
  35. mtebc(pb1ap, 0x00000000);
  36. mtebc(pb1cr, 0x00000000);
  37. mtebc(pb2ap, 0x04814500);
  38. /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
  39. mtebc(pb3ap, 0x00000000);
  40. mtebc(pb3cr, 0x00000000);
  41. mtebc(pb4ap, 0x00000000);
  42. mtebc(pb4cr, 0x00000000);
  43. mtebc(pb5ap, 0x00000000);
  44. mtebc(pb5cr, 0x00000000);
  45. /*--------------------------------------------------------------------
  46. * Setup the interrupt controller polarities, triggers, etc.
  47. *-------------------------------------------------------------------*/
  48. mtdcr(uic0sr, 0xffffffff); /* clear all */
  49. mtdcr(uic0er, 0x00000000); /* disable all */
  50. mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
  51. mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
  52. mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
  53. mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
  54. mtdcr(uic0sr, 0xffffffff); /* clear all */
  55. mtdcr(uic1sr, 0xffffffff); /* clear all */
  56. mtdcr(uic1er, 0x00000000); /* disable all */
  57. mtdcr(uic1cr, 0x00000000); /* all non-critical */
  58. mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
  59. mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
  60. mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
  61. mtdcr(uic1sr, 0xffffffff); /* clear all */
  62. /*--------------------------------------------------------------------
  63. * Setup the GPIO pins
  64. *-------------------------------------------------------------------*/
  65. /*CPLD cs */
  66. /*setup Address lines for flash sizes larger than 16Meg. */
  67. out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
  68. out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
  69. out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
  70. /*setup emac */
  71. out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  72. out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  73. out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  74. out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  75. out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  76. /*UART1 */
  77. out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
  78. out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
  79. out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
  80. /*setup USB 2.0 */
  81. out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
  82. out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
  83. out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
  84. out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
  85. out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
  86. /*--------------------------------------------------------------------
  87. * Setup other serial configuration
  88. *-------------------------------------------------------------------*/
  89. mfsdr(sdr_pci0, reg);
  90. mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
  91. mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
  92. mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
  93. /*clear tmrclk divisor */
  94. *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
  95. /*enable ethernet */
  96. *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
  97. /*enable usb 1.1 fs device and remove usb 2.0 reset */
  98. *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
  99. /*get rid of flash write protect */
  100. *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
  101. return 0;
  102. }
  103. int checkboard(void)
  104. {
  105. sys_info_t sysinfo;
  106. get_sys_info(&sysinfo);
  107. printf("Board: AMCC YELLOWSTONE\n");
  108. printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
  109. printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
  110. printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
  111. printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
  112. printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000);
  113. printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
  114. return (0);
  115. }
  116. /*************************************************************************
  117. * sdram_init -- doesn't use serial presence detect.
  118. *
  119. * Assumes: 256 MB, ECC, non-registered
  120. * PLB @ 133 MHz
  121. *
  122. ************************************************************************/
  123. void sdram_init(void)
  124. {
  125. register uint reg;
  126. /*--------------------------------------------------------------------
  127. * Setup some default
  128. *------------------------------------------------------------------*/
  129. mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
  130. mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
  131. mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
  132. mtsdram(mem_clktr, 0x40000000); /* ?? */
  133. mtsdram(mem_wddctr, 0x40000000); /* ?? */
  134. /*clear this first, if the DDR is enabled by a debugger
  135. then you can not make changes. */
  136. mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
  137. /*--------------------------------------------------------------------
  138. * Setup for board-specific specific mem
  139. *------------------------------------------------------------------*/
  140. /*
  141. * Following for CAS Latency = 2.5 @ 133 MHz PLB
  142. */
  143. mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
  144. mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
  145. mtsdram(mem_tr0, 0x410a4012); /* ?? */
  146. mtsdram(mem_tr1, 0x8080080b); /* ?? */
  147. mtsdram(mem_rtr, 0x04080000); /* ?? */
  148. mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
  149. mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
  150. udelay(400); /* Delay 200 usecs (min) */
  151. /*--------------------------------------------------------------------
  152. * Enable the controller, then wait for DCEN to complete
  153. *------------------------------------------------------------------*/
  154. mtsdram(mem_cfg0, 0x84000000); /* Enable */
  155. for (;;) {
  156. mfsdram(mem_mcsts, reg);
  157. if (reg & 0x80000000)
  158. break;
  159. }
  160. }
  161. /*************************************************************************
  162. * long int initdram
  163. *
  164. ************************************************************************/
  165. long int initdram(int board)
  166. {
  167. sdram_init();
  168. return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
  169. }
  170. #if defined(CFG_DRAM_TEST)
  171. int testdram(void)
  172. {
  173. unsigned long *mem = (unsigned long *)0;
  174. const unsigned long kend = (1024 / sizeof(unsigned long));
  175. unsigned long k, n;
  176. mtmsr(0);
  177. for (k = 0; k < CFG_KBYTES_SDRAM;
  178. ++k, mem += (1024 / sizeof(unsigned long))) {
  179. if ((k & 1023) == 0) {
  180. printf("%3d MB\r", k / 1024);
  181. }
  182. memset(mem, 0xaaaaaaaa, 1024);
  183. for (n = 0; n < kend; ++n) {
  184. if (mem[n] != 0xaaaaaaaa) {
  185. printf("SDRAM test fails at: %08x\n",
  186. (uint) & mem[n]);
  187. return 1;
  188. }
  189. }
  190. memset(mem, 0x55555555, 1024);
  191. for (n = 0; n < kend; ++n) {
  192. if (mem[n] != 0x55555555) {
  193. printf("SDRAM test fails at: %08x\n",
  194. (uint) & mem[n]);
  195. return 1;
  196. }
  197. }
  198. }
  199. printf("SDRAM test passes\n");
  200. return 0;
  201. }
  202. #endif
  203. /*************************************************************************
  204. * pci_pre_init
  205. *
  206. * This routine is called just prior to registering the hose and gives
  207. * the board the opportunity to check things. Returning a value of zero
  208. * indicates that things are bad & PCI initialization should be aborted.
  209. *
  210. * Different boards may wish to customize the pci controller structure
  211. * (add regions, override default access routines, etc) or perform
  212. * certain pre-initialization actions.
  213. *
  214. ************************************************************************/
  215. #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
  216. int pci_pre_init(struct pci_controller *hose)
  217. {
  218. unsigned long strap;
  219. unsigned long addr;
  220. /*--------------------------------------------------------------------------+
  221. * Bamboo is always configured as the host & requires the
  222. * PCI arbiter to be enabled.
  223. *--------------------------------------------------------------------------*/
  224. mfsdr(sdr_sdstp1, strap);
  225. if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
  226. printf("PCI: SDR0_STRP1[PAE] not set.\n");
  227. printf("PCI: Configuration aborted.\n");
  228. return 0;
  229. }
  230. /*-------------------------------------------------------------------------+
  231. | Set priority for all PLB3 devices to 0.
  232. | Set PLB3 arbiter to fair mode.
  233. +-------------------------------------------------------------------------*/
  234. mfsdr(sdr_amp1, addr);
  235. mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
  236. addr = mfdcr(plb3_acr);
  237. mtdcr(plb3_acr, addr | 0x80000000);
  238. /*-------------------------------------------------------------------------+
  239. | Set priority for all PLB4 devices to 0.
  240. +-------------------------------------------------------------------------*/
  241. mfsdr(sdr_amp0, addr);
  242. mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
  243. addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
  244. mtdcr(plb4_acr, addr);
  245. /*-------------------------------------------------------------------------+
  246. | Set Nebula PLB4 arbiter to fair mode.
  247. +-------------------------------------------------------------------------*/
  248. /* Segment0 */
  249. addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
  250. addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
  251. addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
  252. addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
  253. mtdcr(plb0_acr, addr);
  254. /* Segment1 */
  255. addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
  256. addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
  257. addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
  258. addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
  259. mtdcr(plb1_acr, addr);
  260. return 1;
  261. }
  262. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
  263. /*************************************************************************
  264. * pci_target_init
  265. *
  266. * The bootstrap configuration provides default settings for the pci
  267. * inbound map (PIM). But the bootstrap config choices are limited and
  268. * may not be sufficient for a given board.
  269. *
  270. ************************************************************************/
  271. #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
  272. void pci_target_init(struct pci_controller *hose)
  273. {
  274. u16 cmdstat;
  275. DECLARE_GLOBAL_DATA_PTR;
  276. /*--------------------------------------------------------------------------+
  277. * Set up Direct MMIO registers
  278. *--------------------------------------------------------------------------*/
  279. /*--------------------------------------------------------------------------+
  280. | PowerPC440 EP PCI Master configuration.
  281. | Map one 1Gig range of PLB/processor addresses to PCI memory space.
  282. | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
  283. | Use byte reversed out routines to handle endianess.
  284. | Make this region non-prefetchable.
  285. +--------------------------------------------------------------------------*/
  286. out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  287. out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
  288. out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
  289. out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
  290. out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  291. out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
  292. out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
  293. out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
  294. out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
  295. out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
  296. out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
  297. out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
  298. out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
  299. out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
  300. /*--------------------------------------------------------------------------+
  301. * Set up Configuration registers
  302. *--------------------------------------------------------------------------*/
  303. /* Program the board's subsystem id/vendor id */
  304. pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
  305. CFG_PCI_SUBSYS_VENDORID);
  306. pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
  307. /* Configure command register as bus master */
  308. pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
  309. /* 240nS PCI clock */
  310. pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
  311. /* No error reporting */
  312. pci_write_config_word(0, PCI_ERREN, 0);
  313. pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
  314. }
  315. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
  316. /*************************************************************************
  317. * pci_master_init
  318. *
  319. ************************************************************************/
  320. #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
  321. void pci_master_init(struct pci_controller *hose)
  322. {
  323. unsigned short temp_short;
  324. /*--------------------------------------------------------------------------+
  325. | Write the PowerPC440 EP PCI Configuration regs.
  326. | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
  327. | Enable PowerPC440 EP to act as a PCI memory target (PTM).
  328. +--------------------------------------------------------------------------*/
  329. pci_read_config_word(0, PCI_COMMAND, &temp_short);
  330. pci_write_config_word(0, PCI_COMMAND,
  331. temp_short | PCI_COMMAND_MASTER |
  332. PCI_COMMAND_MEMORY);
  333. }
  334. #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
  335. /*************************************************************************
  336. * is_pci_host
  337. *
  338. * This routine is called to determine if a pci scan should be
  339. * performed. With various hardware environments (especially cPCI and
  340. * PPMC) it's insufficient to depend on the state of the arbiter enable
  341. * bit in the strap register, or generic host/adapter assumptions.
  342. *
  343. * Rather than hard-code a bad assumption in the general 440 code, the
  344. * 440 pci code requires the board to decide at runtime.
  345. *
  346. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  347. *
  348. *
  349. ************************************************************************/
  350. #if defined(CONFIG_PCI)
  351. int is_pci_host(struct pci_controller *hose)
  352. {
  353. /* Bamboo is always configured as host. */
  354. return (1);
  355. }
  356. #endif /* defined(CONFIG_PCI) */
  357. /*************************************************************************
  358. * hw_watchdog_reset
  359. *
  360. * This routine is called to reset (keep alive) the watchdog timer
  361. *
  362. ************************************************************************/
  363. #if defined(CONFIG_HW_WATCHDOG)
  364. void hw_watchdog_reset(void)
  365. {
  366. }
  367. #endif