clock.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010-2015
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. /* Tegra30 Clock control functions */
  7. #include <common.h>
  8. #include <errno.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <asm/arch-tegra/timer.h>
  16. #include <div64.h>
  17. #include <fdtdec.h>
  18. #include <linux/delay.h>
  19. /*
  20. * Clock types that we can use as a source. The Tegra30 has muxes for the
  21. * peripheral clocks, and in most cases there are four options for the clock
  22. * source. This gives us a clock 'type' and exploits what commonality exists
  23. * in the device.
  24. *
  25. * Letters are obvious, except for T which means CLK_M, and S which means the
  26. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  27. * datasheet) and PLL_M are different things. The former is the basic
  28. * clock supplied to the SOC from an external oscillator. The latter is the
  29. * memory clock PLL.
  30. *
  31. * See definitions in clock_id in the header file.
  32. */
  33. enum clock_type_id {
  34. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  35. CLOCK_TYPE_MCPA, /* and so on */
  36. CLOCK_TYPE_MCPT,
  37. CLOCK_TYPE_PCM,
  38. CLOCK_TYPE_PCMT,
  39. CLOCK_TYPE_PCMT16,
  40. CLOCK_TYPE_PDCT,
  41. CLOCK_TYPE_ACPT,
  42. CLOCK_TYPE_ASPTE,
  43. CLOCK_TYPE_PMDACD2T,
  44. CLOCK_TYPE_PCST,
  45. CLOCK_TYPE_COUNT,
  46. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  47. };
  48. enum {
  49. CLOCK_MAX_MUX = 8 /* number of source options for each clock */
  50. };
  51. /*
  52. * Clock source mux for each clock type. This just converts our enum into
  53. * a list of mux sources for use by the code.
  54. *
  55. * Note:
  56. * The extra column in each clock source array is used to store the mask
  57. * bits in its register for the source.
  58. */
  59. #define CLK(x) CLOCK_ID_ ## x
  60. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  61. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
  62. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  63. MASK_BITS_31_30},
  64. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
  65. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  66. MASK_BITS_31_30},
  67. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  68. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  69. MASK_BITS_31_30},
  70. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
  71. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  72. MASK_BITS_31_30},
  73. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  74. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  75. MASK_BITS_31_30},
  76. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
  77. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  78. MASK_BITS_31_30},
  79. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
  80. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  81. MASK_BITS_31_30},
  82. { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
  83. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  84. MASK_BITS_31_30},
  85. { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
  86. CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
  87. MASK_BITS_31_29},
  88. { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
  89. CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
  90. MASK_BITS_31_29},
  91. { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
  92. CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
  93. MASK_BITS_31_28}
  94. };
  95. /*
  96. * Clock type for each peripheral clock source. We put the name in each
  97. * record just so it is easy to match things up
  98. */
  99. #define TYPE(name, type) type
  100. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  101. /* 0x00 */
  102. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  103. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  104. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  105. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
  106. TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
  107. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  108. TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
  109. TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
  110. /* 0x08 */
  111. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  112. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
  113. TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
  114. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  115. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  116. TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
  117. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
  118. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
  119. /* 0x10 */
  120. TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
  121. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  122. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  123. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  124. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
  125. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
  126. TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
  127. TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
  128. /* 0x18 */
  129. TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
  130. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
  131. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
  132. TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
  133. TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
  134. TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
  135. TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
  136. TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
  137. /* 0x20 */
  138. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
  139. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  140. TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
  141. TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
  142. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  143. TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
  144. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
  145. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
  146. /* 0x28 */
  147. TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
  148. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  149. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  150. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  151. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  152. TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
  153. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
  154. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
  155. /* 0x30 */
  156. TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
  157. TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
  158. TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
  159. TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
  160. TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
  161. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
  162. TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
  163. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  164. /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
  165. TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
  166. TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
  167. TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
  168. TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
  169. TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
  170. TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
  171. TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
  172. TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
  173. /* 0x40 */
  174. TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
  175. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  176. TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
  177. TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
  178. TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
  179. TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
  180. TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
  181. TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
  182. /* 0x48 */
  183. TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
  184. TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
  185. TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
  186. TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
  187. TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
  188. TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
  189. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  190. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  191. /* 0x50 */
  192. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  193. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  194. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  195. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  196. TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
  197. TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
  198. TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
  199. };
  200. /*
  201. * This array translates a periph_id to a periphc_internal_id
  202. *
  203. * Not present/matched up:
  204. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  205. * SPDIF - which is both 0x08 and 0x0c
  206. *
  207. */
  208. #define NONE(name) (-1)
  209. #define OFFSET(name, value) PERIPHC_ ## name
  210. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  211. /* Low word: 31:0 */
  212. NONE(CPU),
  213. NONE(COP),
  214. NONE(TRIGSYS),
  215. NONE(RESERVED3),
  216. NONE(RESERVED4),
  217. NONE(TMR),
  218. PERIPHC_UART1,
  219. PERIPHC_UART2, /* and vfir 0x68 */
  220. /* 8 */
  221. NONE(GPIO),
  222. PERIPHC_SDMMC2,
  223. NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
  224. PERIPHC_I2S1,
  225. PERIPHC_I2C1,
  226. PERIPHC_NDFLASH,
  227. PERIPHC_SDMMC1,
  228. PERIPHC_SDMMC4,
  229. /* 16 */
  230. NONE(RESERVED16),
  231. PERIPHC_PWM,
  232. PERIPHC_I2S2,
  233. PERIPHC_EPP,
  234. PERIPHC_VI,
  235. PERIPHC_G2D,
  236. NONE(USBD),
  237. NONE(ISP),
  238. /* 24 */
  239. PERIPHC_G3D,
  240. NONE(RESERVED25),
  241. PERIPHC_DISP2,
  242. PERIPHC_DISP1,
  243. PERIPHC_HOST1X,
  244. NONE(VCP),
  245. PERIPHC_I2S0,
  246. NONE(CACHE2),
  247. /* Middle word: 63:32 */
  248. NONE(MEM),
  249. NONE(AHBDMA),
  250. NONE(APBDMA),
  251. NONE(RESERVED35),
  252. NONE(RESERVED36),
  253. NONE(STAT_MON),
  254. NONE(RESERVED38),
  255. NONE(RESERVED39),
  256. /* 40 */
  257. NONE(KFUSE),
  258. PERIPHC_SBC1,
  259. PERIPHC_NOR,
  260. NONE(RESERVED43),
  261. PERIPHC_SBC2,
  262. NONE(RESERVED45),
  263. PERIPHC_SBC3,
  264. PERIPHC_DVC_I2C,
  265. /* 48 */
  266. NONE(DSI),
  267. PERIPHC_TVO, /* also CVE 0x40 */
  268. PERIPHC_MIPI,
  269. PERIPHC_HDMI,
  270. NONE(CSI),
  271. PERIPHC_TVDAC,
  272. PERIPHC_I2C2,
  273. PERIPHC_UART3,
  274. /* 56 */
  275. NONE(RESERVED56),
  276. PERIPHC_EMC,
  277. NONE(USB2),
  278. NONE(USB3),
  279. PERIPHC_MPE,
  280. PERIPHC_VDE,
  281. NONE(BSEA),
  282. NONE(BSEV),
  283. /* Upper word 95:64 */
  284. PERIPHC_SPEEDO,
  285. PERIPHC_UART4,
  286. PERIPHC_UART5,
  287. PERIPHC_I2C3,
  288. PERIPHC_SBC4,
  289. PERIPHC_SDMMC3,
  290. NONE(PCIE),
  291. PERIPHC_OWR,
  292. /* 72 */
  293. NONE(AFI),
  294. PERIPHC_CSITE,
  295. NONE(PCIEXCLK),
  296. NONE(AVPUCQ),
  297. NONE(RESERVED76),
  298. NONE(RESERVED77),
  299. NONE(RESERVED78),
  300. NONE(DTV),
  301. /* 80 */
  302. PERIPHC_NANDSPEED,
  303. PERIPHC_I2CSLOW,
  304. NONE(DSIB),
  305. NONE(RESERVED83),
  306. NONE(IRAMA),
  307. NONE(IRAMB),
  308. NONE(IRAMC),
  309. NONE(IRAMD),
  310. /* 88 */
  311. NONE(CRAM2),
  312. NONE(RESERVED89),
  313. NONE(MDOUBLER),
  314. NONE(RESERVED91),
  315. NONE(SUSOUT),
  316. NONE(RESERVED93),
  317. NONE(RESERVED94),
  318. NONE(RESERVED95),
  319. /* V word: 31:0 */
  320. NONE(CPUG),
  321. NONE(CPULP),
  322. PERIPHC_G3D2,
  323. PERIPHC_MSELECT,
  324. PERIPHC_TSENSOR,
  325. PERIPHC_I2S3,
  326. PERIPHC_I2S4,
  327. PERIPHC_I2C4,
  328. /* 08 */
  329. PERIPHC_SBC5,
  330. PERIPHC_SBC6,
  331. PERIPHC_AUDIO,
  332. NONE(APBIF),
  333. PERIPHC_DAM0,
  334. PERIPHC_DAM1,
  335. PERIPHC_DAM2,
  336. PERIPHC_HDA2CODEC2X,
  337. /* 16 */
  338. NONE(ATOMICS),
  339. NONE(RESERVED17),
  340. NONE(RESERVED18),
  341. NONE(RESERVED19),
  342. NONE(RESERVED20),
  343. NONE(RESERVED21),
  344. NONE(RESERVED22),
  345. PERIPHC_ACTMON,
  346. /* 24 */
  347. NONE(RESERVED24),
  348. NONE(RESERVED25),
  349. NONE(RESERVED26),
  350. NONE(RESERVED27),
  351. PERIPHC_SATA,
  352. PERIPHC_HDA,
  353. NONE(RESERVED30),
  354. NONE(RESERVED31),
  355. /* W word: 31:0 */
  356. NONE(HDA2HDMICODEC),
  357. NONE(SATACOLD),
  358. NONE(RESERVED0_PCIERX0),
  359. NONE(RESERVED1_PCIERX1),
  360. NONE(RESERVED2_PCIERX2),
  361. NONE(RESERVED3_PCIERX3),
  362. NONE(RESERVED4_PCIERX4),
  363. NONE(RESERVED5_PCIERX5),
  364. /* 40 */
  365. NONE(CEC),
  366. NONE(RESERVED6_PCIE2),
  367. NONE(RESERVED7_EMC),
  368. NONE(RESERVED8_HDMI),
  369. NONE(RESERVED9_SATA),
  370. NONE(RESERVED10_MIPI),
  371. NONE(EX_RESERVED46),
  372. NONE(EX_RESERVED47),
  373. };
  374. /*
  375. * PLL divider shift/mask tables for all PLL IDs.
  376. */
  377. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  378. /*
  379. * T30: some deviations from T2x.
  380. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
  381. * If lock_ena or lock_det are >31, they're not used in that PLL.
  382. */
  383. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
  384. .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
  385. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
  386. .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  387. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  388. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
  389. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  390. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
  391. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
  392. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
  393. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  394. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
  395. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
  396. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
  397. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  398. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  399. { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  400. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
  401. };
  402. /*
  403. * Get the oscillator frequency, from the corresponding hardware configuration
  404. * field. Note that T30 supports 3 new higher freqs, but we map back
  405. * to the old T20 freqs. Support for the higher oscillators is TBD.
  406. */
  407. enum clock_osc_freq clock_get_osc_freq(void)
  408. {
  409. struct clk_rst_ctlr *clkrst =
  410. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  411. u32 reg;
  412. reg = readl(&clkrst->crc_osc_ctrl);
  413. reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  414. if (reg & 1) /* one of the newer freqs */
  415. printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
  416. return reg >> 2; /* Map to most common (T20) freqs */
  417. }
  418. /* Returns a pointer to the clock source register for a peripheral */
  419. u32 *get_periph_source_reg(enum periph_id periph_id)
  420. {
  421. struct clk_rst_ctlr *clkrst =
  422. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  423. enum periphc_internal_id internal_id;
  424. /* Coresight is a special case */
  425. if (periph_id == PERIPH_ID_CSI)
  426. return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
  427. assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
  428. internal_id = periph_id_to_internal_id[periph_id];
  429. assert(internal_id != -1);
  430. if (internal_id >= PERIPHC_VW_FIRST) {
  431. internal_id -= PERIPHC_VW_FIRST;
  432. return &clkrst->crc_clk_src_vw[internal_id];
  433. } else
  434. return &clkrst->crc_clk_src[internal_id];
  435. }
  436. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  437. int *divider_bits, int *type)
  438. {
  439. enum periphc_internal_id internal_id;
  440. if (!clock_periph_id_isvalid(periph_id))
  441. return -1;
  442. internal_id = periph_id_to_internal_id[periph_id];
  443. if (!periphc_internal_id_isvalid(internal_id))
  444. return -1;
  445. *type = clock_periph_type[internal_id];
  446. if (!clock_type_id_isvalid(*type))
  447. return -1;
  448. *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
  449. if (*type == CLOCK_TYPE_PCMT16)
  450. *divider_bits = 16;
  451. else
  452. *divider_bits = 8;
  453. return 0;
  454. }
  455. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  456. {
  457. enum periphc_internal_id internal_id;
  458. int type;
  459. if (!clock_periph_id_isvalid(periph_id))
  460. return CLOCK_ID_NONE;
  461. internal_id = periph_id_to_internal_id[periph_id];
  462. if (!periphc_internal_id_isvalid(internal_id))
  463. return CLOCK_ID_NONE;
  464. type = clock_periph_type[internal_id];
  465. if (!clock_type_id_isvalid(type))
  466. return CLOCK_ID_NONE;
  467. return clock_source[type][source];
  468. }
  469. /**
  470. * Given a peripheral ID and the required source clock, this returns which
  471. * value should be programmed into the source mux for that peripheral.
  472. *
  473. * There is special code here to handle the one source type with 5 sources.
  474. *
  475. * @param periph_id peripheral to start
  476. * @param source PLL id of required parent clock
  477. * @param mux_bits Set to number of bits in mux register: 2 or 4
  478. * @param divider_bits Set to number of divider bits (8 or 16)
  479. * @return mux value (0-4, or -1 if not found)
  480. */
  481. int get_periph_clock_source(enum periph_id periph_id,
  482. enum clock_id parent, int *mux_bits, int *divider_bits)
  483. {
  484. enum clock_type_id type;
  485. int mux, err;
  486. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  487. assert(!err);
  488. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  489. if (clock_source[type][mux] == parent)
  490. return mux;
  491. /* if we get here, either us or the caller has made a mistake */
  492. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  493. parent);
  494. return -1;
  495. }
  496. void clock_set_enable(enum periph_id periph_id, int enable)
  497. {
  498. struct clk_rst_ctlr *clkrst =
  499. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  500. u32 *clk;
  501. u32 reg;
  502. /* Enable/disable the clock to this peripheral */
  503. assert(clock_periph_id_isvalid(periph_id));
  504. if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
  505. clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  506. else
  507. clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
  508. reg = readl(clk);
  509. if (enable)
  510. reg |= PERIPH_MASK(periph_id);
  511. else
  512. reg &= ~PERIPH_MASK(periph_id);
  513. writel(reg, clk);
  514. }
  515. void reset_set_enable(enum periph_id periph_id, int enable)
  516. {
  517. struct clk_rst_ctlr *clkrst =
  518. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  519. u32 *reset;
  520. u32 reg;
  521. /* Enable/disable reset to the peripheral */
  522. assert(clock_periph_id_isvalid(periph_id));
  523. if (periph_id < PERIPH_ID_VW_FIRST)
  524. reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  525. else
  526. reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
  527. reg = readl(reset);
  528. if (enable)
  529. reg |= PERIPH_MASK(periph_id);
  530. else
  531. reg &= ~PERIPH_MASK(periph_id);
  532. writel(reg, reset);
  533. }
  534. #if CONFIG_IS_ENABLED(OF_CONTROL)
  535. /*
  536. * Convert a device tree clock ID to our peripheral ID. They are mostly
  537. * the same but we are very cautious so we check that a valid clock ID is
  538. * provided.
  539. *
  540. * @param clk_id Clock ID according to tegra30 device tree binding
  541. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  542. */
  543. enum periph_id clk_id_to_periph_id(int clk_id)
  544. {
  545. if (clk_id > PERIPH_ID_COUNT)
  546. return PERIPH_ID_NONE;
  547. switch (clk_id) {
  548. case PERIPH_ID_RESERVED3:
  549. case PERIPH_ID_RESERVED4:
  550. case PERIPH_ID_RESERVED16:
  551. case PERIPH_ID_RESERVED24:
  552. case PERIPH_ID_RESERVED35:
  553. case PERIPH_ID_RESERVED43:
  554. case PERIPH_ID_RESERVED45:
  555. case PERIPH_ID_RESERVED56:
  556. case PERIPH_ID_PCIEXCLK:
  557. case PERIPH_ID_RESERVED76:
  558. case PERIPH_ID_RESERVED77:
  559. case PERIPH_ID_RESERVED78:
  560. case PERIPH_ID_RESERVED83:
  561. case PERIPH_ID_RESERVED89:
  562. case PERIPH_ID_RESERVED91:
  563. case PERIPH_ID_RESERVED93:
  564. case PERIPH_ID_RESERVED94:
  565. case PERIPH_ID_RESERVED95:
  566. return PERIPH_ID_NONE;
  567. default:
  568. return clk_id;
  569. }
  570. }
  571. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  572. void clock_early_init(void)
  573. {
  574. tegra30_set_up_pllp();
  575. }
  576. void arch_timer_init(void)
  577. {
  578. }
  579. #define PMC_SATA_PWRGT 0x1ac
  580. #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
  581. #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
  582. #define PLLE_SS_CNTL 0x68
  583. #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
  584. #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
  585. #define PLLE_SS_CNTL_SSCBYP (1 << 12)
  586. #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
  587. #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
  588. #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
  589. #define PLLE_BASE 0x0e8
  590. #define PLLE_BASE_ENABLE_CML (1 << 31)
  591. #define PLLE_BASE_ENABLE (1 << 30)
  592. #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
  593. #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
  594. #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
  595. #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
  596. #define PLLE_MISC 0x0ec
  597. #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
  598. #define PLLE_MISC_PLL_READY (1 << 15)
  599. #define PLLE_MISC_LOCK (1 << 11)
  600. #define PLLE_MISC_LOCK_ENABLE (1 << 9)
  601. #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
  602. static int tegra_plle_train(void)
  603. {
  604. unsigned int timeout = 2000;
  605. unsigned long value;
  606. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  607. value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
  608. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  609. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  610. value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
  611. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  612. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  613. value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
  614. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  615. do {
  616. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  617. if (value & PLLE_MISC_PLL_READY)
  618. break;
  619. udelay(100);
  620. } while (--timeout);
  621. if (timeout == 0) {
  622. pr_err("timeout waiting for PLLE to become ready");
  623. return -ETIMEDOUT;
  624. }
  625. return 0;
  626. }
  627. int tegra_plle_enable(void)
  628. {
  629. unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
  630. u32 value;
  631. int err;
  632. /* disable PLLE clock */
  633. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  634. value &= ~PLLE_BASE_ENABLE_CML;
  635. value &= ~PLLE_BASE_ENABLE;
  636. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  637. /* clear lock enable and setup field */
  638. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  639. value &= ~PLLE_MISC_LOCK_ENABLE;
  640. value &= ~PLLE_MISC_SETUP_BASE(0xffff);
  641. value &= ~PLLE_MISC_SETUP_EXT(0x3);
  642. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  643. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  644. if ((value & PLLE_MISC_PLL_READY) == 0) {
  645. err = tegra_plle_train();
  646. if (err < 0) {
  647. pr_err("failed to train PLLE: %d", err);
  648. return err;
  649. }
  650. }
  651. /* configure PLLE */
  652. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  653. value &= ~PLLE_BASE_PLDIV_CML(0x0f);
  654. value |= PLLE_BASE_PLDIV_CML(cpcon);
  655. value &= ~PLLE_BASE_PLDIV(0x3f);
  656. value |= PLLE_BASE_PLDIV(p);
  657. value &= ~PLLE_BASE_NDIV(0xff);
  658. value |= PLLE_BASE_NDIV(n);
  659. value &= ~PLLE_BASE_MDIV(0xff);
  660. value |= PLLE_BASE_MDIV(m);
  661. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  662. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  663. value |= PLLE_MISC_SETUP_BASE(0x7);
  664. value |= PLLE_MISC_LOCK_ENABLE;
  665. value |= PLLE_MISC_SETUP_EXT(0);
  666. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  667. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  668. value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
  669. PLLE_SS_CNTL_BYPASS_SS;
  670. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  671. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  672. value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
  673. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  674. do {
  675. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  676. if (value & PLLE_MISC_LOCK)
  677. break;
  678. udelay(2);
  679. } while (--timeout);
  680. if (timeout == 0) {
  681. pr_err("timeout waiting for PLLE to lock");
  682. return -ETIMEDOUT;
  683. }
  684. udelay(50);
  685. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  686. value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
  687. value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
  688. value &= ~PLLE_SS_CNTL_SSCINC(0xff);
  689. value |= PLLE_SS_CNTL_SSCINC(0x01);
  690. value &= ~PLLE_SS_CNTL_SSCBYP;
  691. value &= ~PLLE_SS_CNTL_INTERP_RESET;
  692. value &= ~PLLE_SS_CNTL_BYPASS_SS;
  693. value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
  694. value |= PLLE_SS_CNTL_SSCMAX(0x24);
  695. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  696. return 0;
  697. }
  698. struct periph_clk_init periph_clk_init_table[] = {
  699. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  700. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  701. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  702. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  703. { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
  704. { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
  705. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  706. { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
  707. { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
  708. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  709. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  710. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  711. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  712. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  713. { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
  714. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  715. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  716. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  717. { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
  718. { -1, },
  719. };