cpu.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/tegra.h>
  8. #include <asm/arch-tegra/pmc.h>
  9. #include <linux/delay.h>
  10. #include "../cpu.h"
  11. static void enable_cpu_power_rail(void)
  12. {
  13. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  14. u32 reg;
  15. reg = readl(&pmc->pmc_cntrl);
  16. reg |= CPUPWRREQ_OE;
  17. writel(reg, &pmc->pmc_cntrl);
  18. /*
  19. * The TI PMU65861C needs a 3.75ms delay between enabling
  20. * the power rail and enabling the CPU clock. This delay
  21. * between SM1EN and SM1 is for switching time + the ramp
  22. * up of the voltage to the CPU (VDD_CPU from PMU).
  23. */
  24. udelay(3750);
  25. }
  26. void start_cpu(u32 reset_vector)
  27. {
  28. /* Enable VDD_CPU */
  29. enable_cpu_power_rail();
  30. /* Hold the CPUs in reset */
  31. reset_A9_cpu(1);
  32. /* Disable the CPU clock */
  33. enable_cpu_clock(0);
  34. /* Enable CoreSight */
  35. clock_enable_coresight(1);
  36. /*
  37. * Set the entry point for CPU execution from reset,
  38. * if it's a non-zero value.
  39. */
  40. if (reset_vector)
  41. writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
  42. /* Enable the CPU clock */
  43. enable_cpu_clock(1);
  44. /* If the CPU doesn't already have power, power it up */
  45. powerup_cpu();
  46. /* Take the CPU out of reset */
  47. reset_A9_cpu(0);
  48. }