clock.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2010-2015
  5. * NVIDIA Corporation <www.nvidia.com>
  6. */
  7. /* Tegra20 Clock control functions */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/tegra.h>
  15. #include <asm/arch-tegra/clk_rst.h>
  16. #include <asm/arch-tegra/timer.h>
  17. #include <div64.h>
  18. #include <fdtdec.h>
  19. #include <linux/delay.h>
  20. /*
  21. * Clock types that we can use as a source. The Tegra20 has muxes for the
  22. * peripheral clocks, and in most cases there are four options for the clock
  23. * source. This gives us a clock 'type' and exploits what commonality exists
  24. * in the device.
  25. *
  26. * Letters are obvious, except for T which means CLK_M, and S which means the
  27. * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  28. * datasheet) and PLL_M are different things. The former is the basic
  29. * clock supplied to the SOC from an external oscillator. The latter is the
  30. * memory clock PLL.
  31. *
  32. * See definitions in clock_id in the header file.
  33. */
  34. enum clock_type_id {
  35. CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
  36. CLOCK_TYPE_MCPA, /* and so on */
  37. CLOCK_TYPE_MCPT,
  38. CLOCK_TYPE_PCM,
  39. CLOCK_TYPE_PCMT,
  40. CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
  41. CLOCK_TYPE_PCXTS,
  42. CLOCK_TYPE_PDCT,
  43. CLOCK_TYPE_COUNT,
  44. CLOCK_TYPE_NONE = -1, /* invalid clock type */
  45. };
  46. enum {
  47. CLOCK_MAX_MUX = 4 /* number of source options for each clock */
  48. };
  49. /*
  50. * Clock source mux for each clock type. This just converts our enum into
  51. * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
  52. * is special as it has 5 sources. Since it also has a different number of
  53. * bits in its register for the source, we just handle it with a special
  54. * case in the code.
  55. */
  56. #define CLK(x) CLOCK_ID_ ## x
  57. static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
  58. { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
  59. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
  60. { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
  61. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
  62. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
  63. { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
  64. { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
  65. { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
  66. };
  67. /*
  68. * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
  69. * not in the header file since it is for purely internal use - we want
  70. * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
  71. * confusion bewteen PERIPH_ID_... and PERIPHC_...
  72. *
  73. * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
  74. * confusing.
  75. *
  76. * Note to SOC vendors: perhaps define a unified numbering for peripherals and
  77. * use it for reset, clock enable, clock source/divider and even pinmuxing
  78. * if you can.
  79. */
  80. enum periphc_internal_id {
  81. /* 0x00 */
  82. PERIPHC_I2S1,
  83. PERIPHC_I2S2,
  84. PERIPHC_SPDIF_OUT,
  85. PERIPHC_SPDIF_IN,
  86. PERIPHC_PWM,
  87. PERIPHC_SPI1,
  88. PERIPHC_SPI2,
  89. PERIPHC_SPI3,
  90. /* 0x08 */
  91. PERIPHC_XIO,
  92. PERIPHC_I2C1,
  93. PERIPHC_DVC_I2C,
  94. PERIPHC_TWC,
  95. PERIPHC_0c,
  96. PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
  97. PERIPHC_DISP1,
  98. PERIPHC_DISP2,
  99. /* 0x10 */
  100. PERIPHC_CVE,
  101. PERIPHC_IDE0,
  102. PERIPHC_VI,
  103. PERIPHC_1c,
  104. PERIPHC_SDMMC1,
  105. PERIPHC_SDMMC2,
  106. PERIPHC_G3D,
  107. PERIPHC_G2D,
  108. /* 0x18 */
  109. PERIPHC_NDFLASH,
  110. PERIPHC_SDMMC4,
  111. PERIPHC_VFIR,
  112. PERIPHC_EPP,
  113. PERIPHC_MPE,
  114. PERIPHC_MIPI,
  115. PERIPHC_UART1,
  116. PERIPHC_UART2,
  117. /* 0x20 */
  118. PERIPHC_HOST1X,
  119. PERIPHC_21,
  120. PERIPHC_TVO,
  121. PERIPHC_HDMI,
  122. PERIPHC_24,
  123. PERIPHC_TVDAC,
  124. PERIPHC_I2C2,
  125. PERIPHC_EMC,
  126. /* 0x28 */
  127. PERIPHC_UART3,
  128. PERIPHC_29,
  129. PERIPHC_VI_SENSOR,
  130. PERIPHC_2b,
  131. PERIPHC_2c,
  132. PERIPHC_SPI4,
  133. PERIPHC_I2C3,
  134. PERIPHC_SDMMC3,
  135. /* 0x30 */
  136. PERIPHC_UART4,
  137. PERIPHC_UART5,
  138. PERIPHC_VDE,
  139. PERIPHC_OWR,
  140. PERIPHC_NOR,
  141. PERIPHC_CSITE,
  142. PERIPHC_COUNT,
  143. PERIPHC_NONE = -1,
  144. };
  145. /*
  146. * Clock type for each peripheral clock source. We put the name in each
  147. * record just so it is easy to match things up
  148. */
  149. #define TYPE(name, type) type
  150. static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
  151. /* 0x00 */
  152. TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
  153. TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
  154. TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
  155. TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
  156. TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
  157. TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
  158. TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
  159. TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
  160. /* 0x08 */
  161. TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
  162. TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
  163. TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
  164. TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
  165. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  166. TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
  167. TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
  168. TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
  169. /* 0x10 */
  170. TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
  171. TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
  172. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  173. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  174. TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
  175. TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
  176. TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
  177. TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
  178. /* 0x18 */
  179. TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
  180. TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
  181. TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
  182. TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
  183. TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
  184. TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
  185. TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
  186. TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
  187. /* 0x20 */
  188. TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
  189. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  190. TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
  191. TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
  192. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  193. TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
  194. TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
  195. TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
  196. /* 0x28 */
  197. TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
  198. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  199. TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
  200. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  201. TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
  202. TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
  203. TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
  204. TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
  205. /* 0x30 */
  206. TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
  207. TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
  208. TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
  209. TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
  210. TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
  211. TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
  212. };
  213. /*
  214. * This array translates a periph_id to a periphc_internal_id
  215. *
  216. * Not present/matched up:
  217. * uint vi_sensor; _VI_SENSOR_0, 0x1A8
  218. * SPDIF - which is both 0x08 and 0x0c
  219. *
  220. */
  221. #define NONE(name) (-1)
  222. #define OFFSET(name, value) PERIPHC_ ## name
  223. static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
  224. /* Low word: 31:0 */
  225. NONE(CPU),
  226. NONE(RESERVED1),
  227. NONE(RESERVED2),
  228. NONE(AC97),
  229. NONE(RTC),
  230. NONE(TMR),
  231. PERIPHC_UART1,
  232. PERIPHC_UART2, /* and vfir 0x68 */
  233. /* 0x08 */
  234. NONE(GPIO),
  235. PERIPHC_SDMMC2,
  236. NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
  237. PERIPHC_I2S1,
  238. PERIPHC_I2C1,
  239. PERIPHC_NDFLASH,
  240. PERIPHC_SDMMC1,
  241. PERIPHC_SDMMC4,
  242. /* 0x10 */
  243. PERIPHC_TWC,
  244. PERIPHC_PWM,
  245. PERIPHC_I2S2,
  246. PERIPHC_EPP,
  247. PERIPHC_VI,
  248. PERIPHC_G2D,
  249. NONE(USBD),
  250. NONE(ISP),
  251. /* 0x18 */
  252. PERIPHC_G3D,
  253. PERIPHC_IDE0,
  254. PERIPHC_DISP2,
  255. PERIPHC_DISP1,
  256. PERIPHC_HOST1X,
  257. NONE(VCP),
  258. NONE(RESERVED30),
  259. NONE(CACHE2),
  260. /* Middle word: 63:32 */
  261. NONE(MEM),
  262. NONE(AHBDMA),
  263. NONE(APBDMA),
  264. NONE(RESERVED35),
  265. NONE(KBC),
  266. NONE(STAT_MON),
  267. NONE(PMC),
  268. NONE(FUSE),
  269. /* 0x28 */
  270. NONE(KFUSE),
  271. NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
  272. PERIPHC_NOR,
  273. PERIPHC_SPI1,
  274. PERIPHC_SPI2,
  275. PERIPHC_XIO,
  276. PERIPHC_SPI3,
  277. PERIPHC_DVC_I2C,
  278. /* 0x30 */
  279. NONE(DSI),
  280. PERIPHC_TVO, /* also CVE 0x40 */
  281. PERIPHC_MIPI,
  282. PERIPHC_HDMI,
  283. PERIPHC_CSITE,
  284. PERIPHC_TVDAC,
  285. PERIPHC_I2C2,
  286. PERIPHC_UART3,
  287. /* 0x38 */
  288. NONE(RESERVED56),
  289. PERIPHC_EMC,
  290. NONE(USB2),
  291. NONE(USB3),
  292. PERIPHC_MPE,
  293. PERIPHC_VDE,
  294. NONE(BSEA),
  295. NONE(BSEV),
  296. /* Upper word 95:64 */
  297. NONE(SPEEDO),
  298. PERIPHC_UART4,
  299. PERIPHC_UART5,
  300. PERIPHC_I2C3,
  301. PERIPHC_SPI4,
  302. PERIPHC_SDMMC3,
  303. NONE(PCIE),
  304. PERIPHC_OWR,
  305. /* 0x48 */
  306. NONE(AFI),
  307. NONE(CORESIGHT),
  308. NONE(PCIEXCLK),
  309. NONE(AVPUCQ),
  310. NONE(RESERVED76),
  311. NONE(RESERVED77),
  312. NONE(RESERVED78),
  313. NONE(RESERVED79),
  314. /* 0x50 */
  315. NONE(RESERVED80),
  316. NONE(RESERVED81),
  317. NONE(RESERVED82),
  318. NONE(RESERVED83),
  319. NONE(IRAMA),
  320. NONE(IRAMB),
  321. NONE(IRAMC),
  322. NONE(IRAMD),
  323. /* 0x58 */
  324. NONE(CRAM2),
  325. };
  326. /*
  327. * PLL divider shift/mask tables for all PLL IDs.
  328. */
  329. struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
  330. /*
  331. * T20 and T25
  332. * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
  333. * If lock_ena or lock_det are >31, they're not used in that PLL.
  334. */
  335. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
  336. .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
  337. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
  338. .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
  339. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  340. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
  341. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  342. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
  343. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
  344. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
  345. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  346. .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
  347. { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
  348. .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
  349. { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
  350. .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
  351. { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
  352. .lock_ena = 18, .lock_det = 0, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS */
  353. };
  354. /*
  355. * Get the oscillator frequency, from the corresponding hardware configuration
  356. * field. T20 has 4 frequencies that it supports.
  357. */
  358. enum clock_osc_freq clock_get_osc_freq(void)
  359. {
  360. struct clk_rst_ctlr *clkrst =
  361. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  362. u32 reg;
  363. reg = readl(&clkrst->crc_osc_ctrl);
  364. return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
  365. }
  366. /* Returns a pointer to the clock source register for a peripheral */
  367. u32 *get_periph_source_reg(enum periph_id periph_id)
  368. {
  369. struct clk_rst_ctlr *clkrst =
  370. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  371. enum periphc_internal_id internal_id;
  372. assert(clock_periph_id_isvalid(periph_id));
  373. internal_id = periph_id_to_internal_id[periph_id];
  374. assert(internal_id != -1);
  375. return &clkrst->crc_clk_src[internal_id];
  376. }
  377. int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
  378. int *divider_bits, int *type)
  379. {
  380. enum periphc_internal_id internal_id;
  381. if (!clock_periph_id_isvalid(periph_id))
  382. return -1;
  383. internal_id = periph_id_to_internal_id[periph_id];
  384. if (!periphc_internal_id_isvalid(internal_id))
  385. return -1;
  386. *type = clock_periph_type[internal_id];
  387. if (!clock_type_id_isvalid(*type))
  388. return -1;
  389. /*
  390. * Special cases here for the clock with a 4-bit source mux and I2C
  391. * with its 16-bit divisor
  392. */
  393. if (*type == CLOCK_TYPE_PCXTS)
  394. *mux_bits = MASK_BITS_31_28;
  395. else
  396. *mux_bits = MASK_BITS_31_30;
  397. if (*type == CLOCK_TYPE_PCMT16)
  398. *divider_bits = 16;
  399. else
  400. *divider_bits = 8;
  401. return 0;
  402. }
  403. enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
  404. {
  405. enum periphc_internal_id internal_id;
  406. int type;
  407. if (!clock_periph_id_isvalid(periph_id))
  408. return CLOCK_ID_NONE;
  409. internal_id = periph_id_to_internal_id[periph_id];
  410. if (!periphc_internal_id_isvalid(internal_id))
  411. return CLOCK_ID_NONE;
  412. type = clock_periph_type[internal_id];
  413. if (!clock_type_id_isvalid(type))
  414. return CLOCK_ID_NONE;
  415. return clock_source[type][source];
  416. }
  417. /**
  418. * Given a peripheral ID and the required source clock, this returns which
  419. * value should be programmed into the source mux for that peripheral.
  420. *
  421. * There is special code here to handle the one source type with 5 sources.
  422. *
  423. * @param periph_id peripheral to start
  424. * @param source PLL id of required parent clock
  425. * @param mux_bits Set to number of bits in mux register: 2 or 4
  426. * @param divider_bits Set to number of divider bits (8 or 16)
  427. * @return mux value (0-4, or -1 if not found)
  428. */
  429. int get_periph_clock_source(enum periph_id periph_id,
  430. enum clock_id parent, int *mux_bits, int *divider_bits)
  431. {
  432. enum clock_type_id type;
  433. int mux, err;
  434. err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
  435. assert(!err);
  436. for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
  437. if (clock_source[type][mux] == parent)
  438. return mux;
  439. /*
  440. * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
  441. * which is not in our table. If not, then they are asking for a
  442. * source which this peripheral can't access through its mux.
  443. */
  444. assert(type == CLOCK_TYPE_PCXTS);
  445. assert(parent == CLOCK_ID_SFROM32KHZ);
  446. if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
  447. return 4; /* mux value for this clock */
  448. /* if we get here, either us or the caller has made a mistake */
  449. printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
  450. parent);
  451. return -1;
  452. }
  453. void clock_set_enable(enum periph_id periph_id, int enable)
  454. {
  455. struct clk_rst_ctlr *clkrst =
  456. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  457. u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
  458. u32 reg;
  459. /* Enable/disable the clock to this peripheral */
  460. assert(clock_periph_id_isvalid(periph_id));
  461. reg = readl(clk);
  462. if (enable)
  463. reg |= PERIPH_MASK(periph_id);
  464. else
  465. reg &= ~PERIPH_MASK(periph_id);
  466. writel(reg, clk);
  467. }
  468. void reset_set_enable(enum periph_id periph_id, int enable)
  469. {
  470. struct clk_rst_ctlr *clkrst =
  471. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  472. u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
  473. u32 reg;
  474. /* Enable/disable reset to the peripheral */
  475. assert(clock_periph_id_isvalid(periph_id));
  476. reg = readl(reset);
  477. if (enable)
  478. reg |= PERIPH_MASK(periph_id);
  479. else
  480. reg &= ~PERIPH_MASK(periph_id);
  481. writel(reg, reset);
  482. }
  483. #if CONFIG_IS_ENABLED(OF_CONTROL)
  484. /*
  485. * Convert a device tree clock ID to our peripheral ID. They are mostly
  486. * the same but we are very cautious so we check that a valid clock ID is
  487. * provided.
  488. *
  489. * @param clk_id Clock ID according to tegra20 device tree binding
  490. * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
  491. */
  492. enum periph_id clk_id_to_periph_id(int clk_id)
  493. {
  494. if (clk_id > PERIPH_ID_COUNT)
  495. return PERIPH_ID_NONE;
  496. switch (clk_id) {
  497. case PERIPH_ID_RESERVED1:
  498. case PERIPH_ID_RESERVED2:
  499. case PERIPH_ID_RESERVED30:
  500. case PERIPH_ID_RESERVED35:
  501. case PERIPH_ID_RESERVED56:
  502. case PERIPH_ID_PCIEXCLK:
  503. case PERIPH_ID_RESERVED76:
  504. case PERIPH_ID_RESERVED77:
  505. case PERIPH_ID_RESERVED78:
  506. case PERIPH_ID_RESERVED79:
  507. case PERIPH_ID_RESERVED80:
  508. case PERIPH_ID_RESERVED81:
  509. case PERIPH_ID_RESERVED82:
  510. case PERIPH_ID_RESERVED83:
  511. case PERIPH_ID_RESERVED91:
  512. return PERIPH_ID_NONE;
  513. default:
  514. return clk_id;
  515. }
  516. }
  517. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  518. void clock_early_init(void)
  519. {
  520. /*
  521. * PLLP output frequency set to 216MHz
  522. * PLLC output frequency set to 600Mhz
  523. *
  524. * TODO: Can we calculate these values instead of hard-coding?
  525. */
  526. switch (clock_get_osc_freq()) {
  527. case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
  528. clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
  529. clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
  530. break;
  531. case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
  532. clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
  533. clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
  534. break;
  535. case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
  536. clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
  537. clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
  538. break;
  539. case CLOCK_OSC_FREQ_19_2:
  540. default:
  541. /*
  542. * These are not supported. It is too early to print a
  543. * message and the UART likely won't work anyway due to the
  544. * oscillator being wrong.
  545. */
  546. break;
  547. }
  548. }
  549. void arch_timer_init(void)
  550. {
  551. }
  552. #define PMC_SATA_PWRGT 0x1ac
  553. #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
  554. #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
  555. #define PLLE_SS_CNTL 0x68
  556. #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
  557. #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
  558. #define PLLE_SS_CNTL_SSCBYP (1 << 12)
  559. #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
  560. #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
  561. #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
  562. #define PLLE_BASE 0x0e8
  563. #define PLLE_BASE_ENABLE_CML (1 << 31)
  564. #define PLLE_BASE_ENABLE (1 << 30)
  565. #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
  566. #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
  567. #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
  568. #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
  569. #define PLLE_MISC 0x0ec
  570. #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
  571. #define PLLE_MISC_PLL_READY (1 << 15)
  572. #define PLLE_MISC_LOCK (1 << 11)
  573. #define PLLE_MISC_LOCK_ENABLE (1 << 9)
  574. #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
  575. static int tegra_plle_train(void)
  576. {
  577. unsigned int timeout = 2000;
  578. unsigned long value;
  579. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  580. value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
  581. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  582. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  583. value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
  584. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  585. value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  586. value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
  587. writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
  588. do {
  589. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  590. if (value & PLLE_MISC_PLL_READY)
  591. break;
  592. udelay(100);
  593. } while (--timeout);
  594. if (timeout == 0) {
  595. pr_err("timeout waiting for PLLE to become ready");
  596. return -ETIMEDOUT;
  597. }
  598. return 0;
  599. }
  600. int tegra_plle_enable(void)
  601. {
  602. unsigned int timeout = 1000;
  603. u32 value;
  604. int err;
  605. /* disable PLLE clock */
  606. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  607. value &= ~PLLE_BASE_ENABLE_CML;
  608. value &= ~PLLE_BASE_ENABLE;
  609. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  610. /* clear lock enable and setup field */
  611. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  612. value &= ~PLLE_MISC_LOCK_ENABLE;
  613. value &= ~PLLE_MISC_SETUP_BASE(0xffff);
  614. value &= ~PLLE_MISC_SETUP_EXT(0x3);
  615. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  616. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  617. if ((value & PLLE_MISC_PLL_READY) == 0) {
  618. err = tegra_plle_train();
  619. if (err < 0) {
  620. pr_err("failed to train PLLE: %d", err);
  621. return err;
  622. }
  623. }
  624. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  625. value |= PLLE_MISC_SETUP_BASE(0x7);
  626. value |= PLLE_MISC_LOCK_ENABLE;
  627. value |= PLLE_MISC_SETUP_EXT(0);
  628. writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
  629. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  630. value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
  631. PLLE_SS_CNTL_BYPASS_SS;
  632. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  633. value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
  634. value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
  635. writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
  636. do {
  637. value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
  638. if (value & PLLE_MISC_LOCK)
  639. break;
  640. udelay(2);
  641. } while (--timeout);
  642. if (timeout == 0) {
  643. pr_err("timeout waiting for PLLE to lock");
  644. return -ETIMEDOUT;
  645. }
  646. udelay(50);
  647. value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  648. value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
  649. value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
  650. value &= ~PLLE_SS_CNTL_SSCINC(0xff);
  651. value |= PLLE_SS_CNTL_SSCINC(0x01);
  652. value &= ~PLLE_SS_CNTL_SSCBYP;
  653. value &= ~PLLE_SS_CNTL_INTERP_RESET;
  654. value &= ~PLLE_SS_CNTL_BYPASS_SS;
  655. value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
  656. value |= PLLE_SS_CNTL_SSCMAX(0x24);
  657. writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
  658. return 0;
  659. }
  660. struct periph_clk_init periph_clk_init_table[] = {
  661. { PERIPH_ID_SPI1, CLOCK_ID_PERIPH },
  662. { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
  663. { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
  664. { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
  665. { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
  666. { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
  667. { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
  668. { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
  669. { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
  670. { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
  671. { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
  672. { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
  673. { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
  674. { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
  675. { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
  676. { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
  677. { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
  678. { -1, },
  679. };