xusb-padctl.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <dm/of_access.h>
  10. #include <dm/ofnode.h>
  11. #include <linux/delay.h>
  12. #include "../xusb-padctl-common.h"
  13. #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  14. #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
  15. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
  16. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
  17. #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
  18. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
  19. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
  20. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
  21. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
  22. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
  23. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
  24. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
  25. #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
  26. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
  27. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
  28. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
  29. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
  30. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
  31. #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
  32. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
  33. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
  34. #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
  35. enum tegra124_function {
  36. TEGRA124_FUNC_SNPS,
  37. TEGRA124_FUNC_XUSB,
  38. TEGRA124_FUNC_UART,
  39. TEGRA124_FUNC_PCIE,
  40. TEGRA124_FUNC_USB3,
  41. TEGRA124_FUNC_SATA,
  42. TEGRA124_FUNC_RSVD,
  43. };
  44. static const char *const tegra124_functions[] = {
  45. "snps",
  46. "xusb",
  47. "uart",
  48. "pcie",
  49. "usb3",
  50. "sata",
  51. "rsvd",
  52. };
  53. static const unsigned int tegra124_otg_functions[] = {
  54. TEGRA124_FUNC_SNPS,
  55. TEGRA124_FUNC_XUSB,
  56. TEGRA124_FUNC_UART,
  57. TEGRA124_FUNC_RSVD,
  58. };
  59. static const unsigned int tegra124_usb_functions[] = {
  60. TEGRA124_FUNC_SNPS,
  61. TEGRA124_FUNC_XUSB,
  62. };
  63. static const unsigned int tegra124_pci_functions[] = {
  64. TEGRA124_FUNC_PCIE,
  65. TEGRA124_FUNC_USB3,
  66. TEGRA124_FUNC_SATA,
  67. TEGRA124_FUNC_RSVD,
  68. };
  69. #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
  70. { \
  71. .name = _name, \
  72. .offset = _offset, \
  73. .shift = _shift, \
  74. .mask = _mask, \
  75. .iddq = _iddq, \
  76. .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
  77. .funcs = tegra124_##_funcs##_functions, \
  78. }
  79. static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
  80. TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
  81. TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
  82. TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
  83. TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
  84. TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
  85. TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
  86. TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
  87. TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
  88. TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
  89. TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
  90. TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
  91. TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
  92. };
  93. static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
  94. {
  95. u32 value;
  96. if (padctl->enable++ > 0)
  97. return 0;
  98. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  99. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  100. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  101. udelay(100);
  102. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  103. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  104. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  105. udelay(100);
  106. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  107. value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  108. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  109. return 0;
  110. }
  111. static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
  112. {
  113. u32 value;
  114. if (padctl->enable == 0) {
  115. pr_err("unbalanced enable/disable");
  116. return 0;
  117. }
  118. if (--padctl->enable > 0)
  119. return 0;
  120. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  121. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
  122. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  123. udelay(100);
  124. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  125. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
  126. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  127. udelay(100);
  128. value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
  129. value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
  130. padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
  131. return 0;
  132. }
  133. static int phy_prepare(struct tegra_xusb_phy *phy)
  134. {
  135. return tegra_xusb_padctl_enable(phy->padctl);
  136. }
  137. static int phy_unprepare(struct tegra_xusb_phy *phy)
  138. {
  139. return tegra_xusb_padctl_disable(phy->padctl);
  140. }
  141. static int pcie_phy_enable(struct tegra_xusb_phy *phy)
  142. {
  143. struct tegra_xusb_padctl *padctl = phy->padctl;
  144. int err = -ETIMEDOUT;
  145. unsigned long start;
  146. u32 value;
  147. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  148. value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
  149. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  150. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
  151. value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
  152. XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
  153. XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
  154. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
  155. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  156. value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
  157. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  158. start = get_timer(0);
  159. while (get_timer(start) < 50) {
  160. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  161. if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
  162. err = 0;
  163. break;
  164. }
  165. }
  166. return err;
  167. }
  168. static int pcie_phy_disable(struct tegra_xusb_phy *phy)
  169. {
  170. struct tegra_xusb_padctl *padctl = phy->padctl;
  171. u32 value;
  172. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  173. value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
  174. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
  175. return 0;
  176. }
  177. static int sata_phy_enable(struct tegra_xusb_phy *phy)
  178. {
  179. struct tegra_xusb_padctl *padctl = phy->padctl;
  180. int err = -ETIMEDOUT;
  181. unsigned long start;
  182. u32 value;
  183. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  184. value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
  185. value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
  186. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  187. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  188. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
  189. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
  190. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  191. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  192. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
  193. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  194. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  195. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
  196. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  197. start = get_timer(0);
  198. while (get_timer(start) < 50) {
  199. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  200. if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
  201. err = 0;
  202. break;
  203. }
  204. }
  205. return err;
  206. }
  207. static int sata_phy_disable(struct tegra_xusb_phy *phy)
  208. {
  209. struct tegra_xusb_padctl *padctl = phy->padctl;
  210. u32 value;
  211. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  212. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
  213. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  214. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  215. value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
  216. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  217. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  218. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
  219. value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
  220. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
  221. value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  222. value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
  223. value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
  224. padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
  225. return 0;
  226. }
  227. static const struct tegra_xusb_phy_ops pcie_phy_ops = {
  228. .prepare = phy_prepare,
  229. .enable = pcie_phy_enable,
  230. .disable = pcie_phy_disable,
  231. .unprepare = phy_unprepare,
  232. };
  233. static const struct tegra_xusb_phy_ops sata_phy_ops = {
  234. .prepare = phy_prepare,
  235. .enable = sata_phy_enable,
  236. .disable = sata_phy_disable,
  237. .unprepare = phy_unprepare,
  238. };
  239. static struct tegra_xusb_phy tegra124_phys[] = {
  240. {
  241. .type = TEGRA_XUSB_PADCTL_PCIE,
  242. .ops = &pcie_phy_ops,
  243. .padctl = &padctl,
  244. },
  245. {
  246. .type = TEGRA_XUSB_PADCTL_SATA,
  247. .ops = &sata_phy_ops,
  248. .padctl = &padctl,
  249. },
  250. };
  251. static const struct tegra_xusb_padctl_soc tegra124_socdata = {
  252. .lanes = tegra124_lanes,
  253. .num_lanes = ARRAY_SIZE(tegra124_lanes),
  254. .functions = tegra124_functions,
  255. .num_functions = ARRAY_SIZE(tegra124_functions),
  256. .phys = tegra124_phys,
  257. .num_phys = ARRAY_SIZE(tegra124_phys),
  258. };
  259. void tegra_xusb_padctl_init(void)
  260. {
  261. ofnode nodes[1];
  262. int count = 0;
  263. int ret;
  264. debug("%s: start\n", __func__);
  265. if (of_live_active()) {
  266. struct device_node *np = of_find_compatible_node(NULL, NULL,
  267. "nvidia,tegra124-xusb-padctl");
  268. debug("np=%p\n", np);
  269. if (np) {
  270. nodes[0] = np_to_ofnode(np);
  271. count = 1;
  272. }
  273. } else {
  274. int node_offsets[1];
  275. int i;
  276. count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl",
  277. COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
  278. node_offsets, ARRAY_SIZE(node_offsets));
  279. for (i = 0; i < count; i++)
  280. nodes[i] = offset_to_ofnode(node_offsets[i]);
  281. }
  282. ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata);
  283. debug("%s: done, ret=%d\n", __func__, ret);
  284. }